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c4d0e811 SL |
1 | /* |
2 | * Copyright 2013 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef __DDR_H__ | |
8 | #define __DDR_H__ | |
9 | struct board_specific_parameters { | |
10 | u32 n_ranks; | |
11 | u32 datarate_mhz_high; | |
12 | u32 rank_gb; | |
13 | u32 clk_adjust; | |
14 | u32 wrlvl_start; | |
15 | u32 wrlvl_ctl_2; | |
16 | u32 wrlvl_ctl_3; | |
c4d0e811 SL |
17 | }; |
18 | ||
19 | /* | |
20 | * These tables contain all valid speeds we want to override with board | |
21 | * specific parameters. datarate_mhz_high values need to be in ascending order | |
22 | * for each n_ranks group. | |
23 | */ | |
24 | ||
25 | static const struct board_specific_parameters udimm0[] = { | |
26 | /* | |
27 | * memory controller 0 | |
40483e1e SL |
28 | * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | |
29 | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | | |
c4d0e811 | 30 | */ |
40483e1e SL |
31 | {2, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, |
32 | {2, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, | |
33 | {2, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, | |
34 | {2, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, | |
35 | {2, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c}, | |
36 | {2, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, | |
37 | {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a}, | |
38 | {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09}, | |
39 | {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b}, | |
40 | {1, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a}, | |
41 | {1, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c}, | |
42 | {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b}, | |
c4d0e811 SL |
43 | {} |
44 | }; | |
45 | ||
46 | static const struct board_specific_parameters rdimm0[] = { | |
47 | /* | |
48 | * memory controller 0 | |
3fdc827c SL |
49 | * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | |
50 | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | | |
c4d0e811 | 51 | */ |
3fdc827c SL |
52 | /* TODO: need tuning these parameters if RDIMM is used */ |
53 | {4, 1350, 0, 5, 9, 0x08070605, 0x06070806}, | |
54 | {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906}, | |
55 | {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, | |
56 | {2, 1350, 0, 5, 9, 0x08070605, 0x06070806}, | |
57 | {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, | |
58 | {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07}, | |
59 | {1, 1350, 0, 5, 9, 0x08070605, 0x06070806}, | |
60 | {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06}, | |
61 | {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07}, | |
c4d0e811 SL |
62 | {} |
63 | }; | |
64 | ||
c4d0e811 SL |
65 | static const struct board_specific_parameters *udimms[] = { |
66 | udimm0, | |
67 | }; | |
68 | ||
c4d0e811 SL |
69 | static const struct board_specific_parameters *rdimms[] = { |
70 | rdimm0, | |
71 | }; | |
c4d0e811 | 72 | #endif |