[people/ms/u-boot.git] / board / freescale / t208xqds / t208xqds.c

/*
 * Copyright 2009-2013 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:     GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <i2c.h>
#include <netdev.h>
#include <linux/compiler.h>
#include <asm/mmu.h>
#include <asm/processor.h>
#include <asm/immap_85xx.h>
#include <asm/fsl_law.h>
#include <asm/fsl_serdes.h>
#include <asm/fsl_liodn.h>
#include <fm_eth.h>

#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
#include "../common/vid.h"
#include "t208xqds.h"
#include "t208xqds_qixis.h"

DECLARE_GLOBAL_DATA_PTR;

int checkboard(void)
{
	char buf[64];
	u8 sw;
	struct cpu_type *cpu = gd->arch.cpu;
	static const char *freq[4] = {
		"100.00MHZ(from 8T49N222A)", "125.00MHz",
		"156.25MHZ", "100.00MHz"
	};

	printf("Board: %sQDS, ", cpu->name);
	sw = QIXIS_READ(arch);
	printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
	printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);

#ifdef CONFIG_SDCARD
	puts("SD/MMC\n");
#elif CONFIG_SPIFLASH
	puts("SPI\n");
#else
	sw = QIXIS_READ(brdcfg[0]);
	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;

	if (sw < 0x8)
		printf("vBank%d\n", sw);
	else if (sw == 0x8)
		puts("Promjet\n");
	else if (sw == 0x9)
		puts("NAND\n");
	else
		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
#endif

	printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
	       qixis_read_tag(buf), (int)qixis_read_minor());
	/* the timestamp string contains "\n" at the end */
	printf(" on %s", qixis_read_time(buf));

	puts("SERDES Reference Clocks:\n");
	sw = QIXIS_READ(brdcfg[2]);
	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
	       freq[(sw >> 4) & 0x3]);
	printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
	       freq[sw & 0x3]);

	return 0;
}

int select_i2c_ch_pca9547(u8 ch)
{
	int ret;

	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	if (ret) {
		puts("PCA: failed to select proper channel\n");
		return ret;
	}

	return 0;
}

int i2c_multiplexer_select_vid_channel(u8 channel)
{
	return select_i2c_ch_pca9547(channel);
}

int brd_mux_lane_to_slot(void)
{
	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
	u32 srds_prtcl_s1;

	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
				FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
#if defined(CONFIG_T2080QDS)
	u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
				FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
#endif

	switch (srds_prtcl_s1) {
	case 0:
		/* SerDes1 is not enabled */
		break;
#if defined(CONFIG_T2080QDS)
	case 0x1b:
	case 0x1c:
	case 0xa2:
		/* SD1(A:D) => SLOT3 SGMII
		 * SD1(G:H) => SLOT1 SGMII
		 */
		QIXIS_WRITE(brdcfg[12], 0x1a);
		break;
	case 0x94:
	case 0x95:
		/* SD1(A:B) => SLOT3 SGMII@1.25bps
		 * SD1(C:D) => SFP Module, SGMII@3.125bps
		 * SD1(E:H) => SLOT1 SGMII@1.25bps
		 */
	case 0x96:
		/* SD1(A:B) => SLOT3 SGMII@1.25bps
		 * SD1(C)   => SFP Module, SGMII@3.125bps
		 * SD1(D)   => SFP Module, SGMII@1.25bps
		 * SD1(E:H) => SLOT1 PCIe4 x4
		 */
		QIXIS_WRITE(brdcfg[12], 0x3a);
		break;
	case 0x50:
	case 0x51:
		/* SD1(A:D) => SLOT3 XAUI
		 * SD1(E)   => SLOT1 PCIe4
		 * SD1(F:H) => SLOT2 SGMII
		 */
		QIXIS_WRITE(brdcfg[12], 0x15);
		break;
	case 0x66:
	case 0x67:
		/* SD1(A:D) => XFI cage
		 * SD1(E:H) => SLOT1 PCIe4
		 */
		QIXIS_WRITE(brdcfg[12], 0xfe);
		break;
	case 0x6a:
	case 0x6b:
		/* SD1(A:D) => XFI cage
		 * SD1(E)   => SLOT1 PCIe4
		 * SD1(F:H) => SLOT2 SGMII
		 */
		QIXIS_WRITE(brdcfg[12], 0xf1);
		break;
	case 0x6c:
	case 0x6d:
		/* SD1(A:B) => XFI cage
		 * SD1(C:D) => SLOT3 SGMII
		 * SD1(E:H) => SLOT1 PCIe4
		 */
		QIXIS_WRITE(brdcfg[12], 0xda);
		break;
	case 0x6e:
		/* SD1(A:B) => SFP Module, XFI
		 * SD1(C:D) => SLOT3 SGMII
		 * SD1(E:F) => SLOT1 PCIe4 x2
		 * SD1(G:H) => SLOT2 SGMII
		 */
		QIXIS_WRITE(brdcfg[12], 0xd9);
		break;
	case 0xda:
		/* SD1(A:H) => SLOT3 PCIe3 x8
		 */
		 QIXIS_WRITE(brdcfg[12], 0x0);
		 break;
	case 0xc8:
		/* SD1(A)   => SLOT3 PCIe3 x1
		 * SD1(B)   => SFP Module, SGMII@1.25bps
		 * SD1(C:D) => SFP Module, SGMII@3.125bps
		 * SD1(E:F) => SLOT1 PCIe4 x2
		 * SD1(G:H) => SLOT2 SGMII
		 */
		 QIXIS_WRITE(brdcfg[12], 0x79);
		 break;
	case 0xab:
		/* SD1(A:D) => SLOT3 PCIe3 x4
		 * SD1(E:H) => SLOT1 PCIe4 x4
		 */
		 QIXIS_WRITE(brdcfg[12], 0x1a);
		 break;
#elif defined(CONFIG_T2081QDS)
	case 0x50:
	case 0x51:
		/* SD1(A:D) => SLOT2 XAUI
		 * SD1(E)   => SLOT1 PCIe4 x1
		 * SD1(F:H) => SLOT3 SGMII
		 */
		QIXIS_WRITE(brdcfg[12], 0x98);
		QIXIS_WRITE(brdcfg[13], 0x70);
		break;
	case 0x6a:
	case 0x6b:
		/* SD1(A:D) => XFI SFP Module
		 * SD1(E)   => SLOT1 PCIe4 x1
		 * SD1(F:H) => SLOT3 SGMII
		 */
		QIXIS_WRITE(brdcfg[12], 0x80);
		QIXIS_WRITE(brdcfg[13], 0x70);
		break;
	case 0x6c:
	case 0x6d:
		/* SD1(A:B) => XFI SFP Module
		 * SD1(C:D) => SLOT2 SGMII
		 * SD1(E:H) => SLOT1 PCIe4 x4
		 */
		QIXIS_WRITE(brdcfg[12], 0xe8);
		QIXIS_WRITE(brdcfg[13], 0x0);
		break;
	case 0xaa:
	case 0xab:
		/* SD1(A:D) => SLOT2 PCIe3 x4
		 * SD1(F:H) => SLOT1 SGMI4 x4
		 */
		QIXIS_WRITE(brdcfg[12], 0xf8);
		QIXIS_WRITE(brdcfg[13], 0x0);
		break;
	case 0xca:
	case 0xcb:
		/* SD1(A)   => SLOT2 PCIe3 x1
		 * SD1(B)   => SLOT7 SGMII
		 * SD1(C)   => SLOT6 SGMII
		 * SD1(D)   => SLOT5 SGMII
		 * SD1(E)   => SLOT1 PCIe4 x1
		 * SD1(F:H) => SLOT3 SGMII
		 */
		QIXIS_WRITE(brdcfg[12], 0x80);
		QIXIS_WRITE(brdcfg[13], 0x70);
		break;
	case 0xde:
	case 0xdf:
		/* SD1(A:D) => SLOT2 PCIe3 x4
		 * SD1(E)   => SLOT1 PCIe4 x1
		 * SD1(F)   => SLOT4 PCIe1 x1
		 * SD1(G)   => SLOT3 PCIe2 x1
		 * SD1(H)   => SLOT7 SGMII
		 */
		QIXIS_WRITE(brdcfg[12], 0x98);
		QIXIS_WRITE(brdcfg[13], 0x25);
		break;
	case 0xf2:
		/* SD1(A)   => SLOT2 PCIe3 x1
		 * SD1(B:D) => SLOT7 SGMII
		 * SD1(E)   => SLOT1 PCIe4 x1
		 * SD1(F)   => SLOT4 PCIe1 x1
		 * SD1(G)   => SLOT3 PCIe2 x1
		 * SD1(H)   => SLOT7 SGMII
		 */
		QIXIS_WRITE(brdcfg[12], 0x81);
		QIXIS_WRITE(brdcfg[13], 0xa5);
		break;
#endif
	default:
		printf("WARNING: unsupported for SerDes1 Protocol %d\n",
		       srds_prtcl_s1);
		return -1;
	}

#ifdef CONFIG_T2080QDS
	switch (srds_prtcl_s2) {
	case 0:
		/* SerDes2 is not enabled */
		break;
	case 0x01:
	case 0x02:
		/* SD2(A:H) => SLOT4 PCIe1 */
		QIXIS_WRITE(brdcfg[13], 0x10);
		break;
	case 0x15:
	case 0x16:
		/*
		 * SD2(A:D) => SLOT4 PCIe1
		 * SD2(E:F) => SLOT5 PCIe2
		 * SD2(G:H) => SATA1,SATA2
		 */
		QIXIS_WRITE(brdcfg[13], 0xb0);
		break;
	case 0x18:
		/*
		 * SD2(A:D) => SLOT4 PCIe1
		 * SD2(E:F) => SLOT5 Aurora
		 * SD2(G:H) => SATA1,SATA2
		 */
		QIXIS_WRITE(brdcfg[13], 0x78);
		break;
	case 0x1f:
		/*
		 * SD2(A:D) => SLOT4 PCIe1
		 * SD2(E:H) => SLOT5 PCIe2
		 */
		QIXIS_WRITE(brdcfg[13], 0xa0);
		break;
	case 0x29:
	case 0x2d:
	case 0x2e:
		/*
		 * SD2(A:D) => SLOT4 SRIO2
		 * SD2(E:H) => SLOT5 SRIO1
		 */
		QIXIS_WRITE(brdcfg[13], 0xa0);
		break;
	case 0x36:
		/*
		 * SD2(A:D) => SLOT4 SRIO2
		 * SD2(E:F) => Aurora
		 * SD2(G:H) => SATA1,SATA2
		 */
		QIXIS_WRITE(brdcfg[13], 0x78);
		break;
	default:
		printf("WARNING: unsupported for SerDes2 Protocol %d\n",
		       srds_prtcl_s2);
		return -1;
	}
#endif
	return 0;
}

int board_early_init_r(void)
{
	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
	int flash_esel = find_tlb_idx((void *)flashbase, 1);

	/*
	 * Remap Boot flash + PROMJET region to caching-inhibited
	 * so that flash can be erased properly.
	 */

	/* Flush d-cache and invalidate i-cache of any FLASH data */
	flush_dcache();
	invalidate_icache();

	if (flash_esel == -1) {
		/* very unlikely unless something is messed up */
		puts("Error: Could not find TLB for FLASH BASE\n");
		flash_esel = 2;	/* give our best effort to continue */
	} else {
		/* invalidate existing TLB entry for flash + promjet */
		disable_tlb(flash_esel);
	}

	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
		MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
		0, flash_esel, BOOKE_PAGESZ_256M, 1);

	/* Disable remote I2C connection to qixis fpga */
	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);

	/*
	 * Adjust core voltage according to voltage ID
	 * This function changes I2C mux to channel 2.
	 */
	if (adjust_vdd(0))
		printf("Warning: Adjusting core voltage failed.\n");

	brd_mux_lane_to_slot();
	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);

	return 0;
}

unsigned long get_board_sys_clk(void)
{
	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
	/* use accurate clock measurement */
	int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
	u32 val;

	val =  freq * base;
	if (val) {
		debug("SYS Clock measurement is: %d\n", val);
		return val;
	} else {
		printf("Warning: SYS clock measurement is invalid, ");
		printf("using value from brdcfg1.\n");
	}
#endif

	switch (sysclk_conf & 0x0F) {
	case QIXIS_SYSCLK_83:
		return 83333333;
	case QIXIS_SYSCLK_100:
		return 100000000;
	case QIXIS_SYSCLK_125:
		return 125000000;
	case QIXIS_SYSCLK_133:
		return 133333333;
	case QIXIS_SYSCLK_150:
		return 150000000;
	case QIXIS_SYSCLK_160:
		return 160000000;
	case QIXIS_SYSCLK_166:
		return 166666666;
	}
	return 66666666;
}

unsigned long get_board_ddr_clk(void)
{
	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
	/* use accurate clock measurement */
	int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
	int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
	u32 val;

	val =  freq * base;
	if (val) {
		debug("DDR Clock measurement is: %d\n", val);
		return val;
	} else {
		printf("Warning: DDR clock measurement is invalid, ");
		printf("using value from brdcfg1.\n");
	}
#endif

	switch ((ddrclk_conf & 0x30) >> 4) {
	case QIXIS_DDRCLK_100:
		return 100000000;
	case QIXIS_DDRCLK_125:
		return 125000000;
	case QIXIS_DDRCLK_133:
		return 133333333;
	}
	return 66666666;
}

int misc_init_r(void)
{
	return 0;
}

int ft_board_setup(void *blob, bd_t *bd)
{
	phys_addr_t base;
	phys_size_t size;

	ft_cpu_setup(blob, bd);

	base = getenv_bootm_low();
	size = getenv_bootm_size();

	fdt_fixup_memory(blob, (u64)base, (u64)size);

#ifdef CONFIG_PCI
	pci_of_setup(blob, bd);
#endif

	fdt_fixup_liodn(blob);
	fdt_fixup_dr_usb(blob, bd);

#ifdef CONFIG_SYS_DPAA_FMAN
	fdt_fixup_fman_ethernet(blob);
	fdt_fixup_board_enet(blob);
#endif

	return 0;
}
Commit	Line	Data
c4d0e811 SL	1	/*
	2	* Copyright 2009-2013 Freescale Semiconductor, Inc.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <command.h>
	9	#include <i2c.h>
	10	#include <netdev.h>
	11	#include <linux/compiler.h>
	12	#include <asm/mmu.h>
	13	#include <asm/processor.h>
	14	#include <asm/immap_85xx.h>
	15	#include <asm/fsl_law.h>
	16	#include <asm/fsl_serdes.h>
c4d0e811 SL	17	#include <asm/fsl_liodn.h>
	18	#include <fm_eth.h>
	19
	20	#include "../common/qixis.h"
	21	#include "../common/vsc3316_3308.h"
3ad2737e	22	#include "../common/vid.h"
254887a5 SL	23	#include "t208xqds.h"
254887a5 SL	24	#include "t208xqds_qixis.h"
c4d0e811 SL	25
	26	DECLARE_GLOBAL_DATA_PTR;
	27
	28	int checkboard(void)
	29	{
	30	char buf[64];
	31	u8 sw;
	32	struct cpu_type *cpu = gd->arch.cpu;
	33	static const char *freq[4] = {
	34	"100.00MHZ(from 8T49N222A)", "125.00MHz",
	35	"156.25MHZ", "100.00MHz"
	36	};
	37
	38	printf("Board: %sQDS, ", cpu->name);
	39	sw = QIXIS_READ(arch);
	40	printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
	41	printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
	42
1576b558 SL	43	#ifdef CONFIG_SDCARD
	44	puts("SD/MMC\n");
	45	#elif CONFIG_SPIFLASH
	46	puts("SPI\n");
	47	#else
c4d0e811 SL	48	sw = QIXIS_READ(brdcfg[0]);
	49	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
	50
	51	if (sw < 0x8)
	52	printf("vBank%d\n", sw);
	53	else if (sw == 0x8)
	54	puts("Promjet\n");
	55	else if (sw == 0x9)
	56	puts("NAND\n");
	57	else
	58	printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
1576b558	59	#endif
c4d0e811 SL	60
	61	printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
	62	qixis_read_tag(buf), (int)qixis_read_minor());
	63	/* the timestamp string contains "\n" at the end */
	64	printf(" on %s", qixis_read_time(buf));
	65
	66	puts("SERDES Reference Clocks:\n");
	67	sw = QIXIS_READ(brdcfg[2]);
	68	printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
	69	freq[(sw >> 4) & 0x3]);
	70	printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
	71	freq[sw & 0x3]);
	72
	73	return 0;
	74	}
	75
	76	int select_i2c_ch_pca9547(u8 ch)
	77	{
	78	int ret;
	79
	80	ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
	81	if (ret) {
	82	puts("PCA: failed to select proper channel\n");
	83	return ret;
	84	}
	85
	86	return 0;
	87	}
	88
3ad2737e YZ	89	int i2c_multiplexer_select_vid_channel(u8 channel)
	90	{
	91	return select_i2c_ch_pca9547(channel);
	92	}
	93
c4d0e811 SL	94	int brd_mux_lane_to_slot(void)
	95	{
	96	ccsr_gur_t gur = (void )(CONFIG_SYS_MPC85xx_GUTS_ADDR);
254887a5	97	u32 srds_prtcl_s1;
c4d0e811 SL	98
	99	srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
	100	FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
	101	srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
254887a5 SL	102	#if defined(CONFIG_T2080QDS)
254887a5 SL	103	u32 srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
c4d0e811 SL	104	FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
c4d0e811 SL	105	srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
254887a5	106	#endif
c4d0e811 SL	107
	108	switch (srds_prtcl_s1) {
	109	case 0:
	110	/* SerDes1 is not enabled */
	111	break;
254887a5	112	#if defined(CONFIG_T2080QDS)
9752eb64	113	case 0x1b:
c4d0e811	114	case 0x1c:
c4d0e811	115	case 0xa2:
c4d0e811 SL	116	/* SD1(A:D) => SLOT3 SGMII
	117	* SD1(G:H) => SLOT1 SGMII
	118	*/
1576b558 SL	119	QIXIS_WRITE(brdcfg[12], 0x1a);
	120	break;
	121	case 0x94:
	122	case 0x95:
	123	/* SD1(A:B) => SLOT3 SGMII@1.25bps
	124	* SD1(C:D) => SFP Module, SGMII@3.125bps
	125	* SD1(E:H) => SLOT1 SGMII@1.25bps
	126	*/
	127	case 0x96:
	128	/* SD1(A:B) => SLOT3 SGMII@1.25bps
	129	* SD1(C) => SFP Module, SGMII@3.125bps
	130	* SD1(D) => SFP Module, SGMII@1.25bps
	131	* SD1(E:H) => SLOT1 PCIe4 x4
	132	*/
	133	QIXIS_WRITE(brdcfg[12], 0x3a);
c4d0e811	134	break;
9752eb64	135	case 0x50:
c4d0e811 SL	136	case 0x51:
	137	/* SD1(A:D) => SLOT3 XAUI
	138	* SD1(E) => SLOT1 PCIe4
	139	* SD1(F:H) => SLOT2 SGMII
	140	*/
	141	QIXIS_WRITE(brdcfg[12], 0x15);
	142	break;
	143	case 0x66:
	144	case 0x67:
	145	/* SD1(A:D) => XFI cage
	146	* SD1(E:H) => SLOT1 PCIe4
	147	*/
	148	QIXIS_WRITE(brdcfg[12], 0xfe);
	149	break;
9752eb64	150	case 0x6a:
c4d0e811 SL	151	case 0x6b:
	152	/* SD1(A:D) => XFI cage
	153	* SD1(E) => SLOT1 PCIe4
	154	* SD1(F:H) => SLOT2 SGMII
	155	*/
	156	QIXIS_WRITE(brdcfg[12], 0xf1);
	157	break;
	158	case 0x6c:
	159	case 0x6d:
	160	/* SD1(A:B) => XFI cage
	161	* SD1(C:D) => SLOT3 SGMII
	162	* SD1(E:H) => SLOT1 PCIe4
	163	*/
	164	QIXIS_WRITE(brdcfg[12], 0xda);
	165	break;
1576b558 SL	166	case 0x6e:
	167	/* SD1(A:B) => SFP Module, XFI
	168	* SD1(C:D) => SLOT3 SGMII
	169	* SD1(E:F) => SLOT1 PCIe4 x2
	170	* SD1(G:H) => SLOT2 SGMII
	171	*/
	172	QIXIS_WRITE(brdcfg[12], 0xd9);
	173	break;
	174	case 0xda:
	175	/* SD1(A:H) => SLOT3 PCIe3 x8
	176	*/
	177	QIXIS_WRITE(brdcfg[12], 0x0);
	178	break;
	179	case 0xc8:
	180	/* SD1(A) => SLOT3 PCIe3 x1
	181	* SD1(B) => SFP Module, SGMII@1.25bps
	182	* SD1(C:D) => SFP Module, SGMII@3.125bps
	183	* SD1(E:F) => SLOT1 PCIe4 x2
	184	* SD1(G:H) => SLOT2 SGMII
	185	*/
	186	QIXIS_WRITE(brdcfg[12], 0x79);
	187	break;
	188	case 0xab:
	189	/* SD1(A:D) => SLOT3 PCIe3 x4
	190	* SD1(E:H) => SLOT1 PCIe4 x4
	191	*/
	192	QIXIS_WRITE(brdcfg[12], 0x1a);
	193	break;
254887a5	194	#elif defined(CONFIG_T2081QDS)
9752eb64	195	case 0x50:
254887a5 SL	196	case 0x51:
	197	/* SD1(A:D) => SLOT2 XAUI
	198	* SD1(E) => SLOT1 PCIe4 x1
	199	* SD1(F:H) => SLOT3 SGMII
	200	*/
	201	QIXIS_WRITE(brdcfg[12], 0x98);
	202	QIXIS_WRITE(brdcfg[13], 0x70);
	203	break;
9752eb64	204	case 0x6a:
254887a5 SL	205	case 0x6b:
	206	/* SD1(A:D) => XFI SFP Module
	207	* SD1(E) => SLOT1 PCIe4 x1
	208	* SD1(F:H) => SLOT3 SGMII
	209	*/
	210	QIXIS_WRITE(brdcfg[12], 0x80);
	211	QIXIS_WRITE(brdcfg[13], 0x70);
	212	break;
	213	case 0x6c:
254887a5 SL	214	case 0x6d:
	215	/* SD1(A:B) => XFI SFP Module
	216	* SD1(C:D) => SLOT2 SGMII
	217	* SD1(E:H) => SLOT1 PCIe4 x4
	218	*/
	219	QIXIS_WRITE(brdcfg[12], 0xe8);
	220	QIXIS_WRITE(brdcfg[13], 0x0);
	221	break;
	222	case 0xaa:
	223	case 0xab:
	224	/* SD1(A:D) => SLOT2 PCIe3 x4
	225	* SD1(F:H) => SLOT1 SGMI4 x4
	226	*/
	227	QIXIS_WRITE(brdcfg[12], 0xf8);
	228	QIXIS_WRITE(brdcfg[13], 0x0);
	229	break;
	230	case 0xca:
	231	case 0xcb:
	232	/* SD1(A) => SLOT2 PCIe3 x1
	233	* SD1(B) => SLOT7 SGMII
	234	* SD1(C) => SLOT6 SGMII
	235	* SD1(D) => SLOT5 SGMII
	236	* SD1(E) => SLOT1 PCIe4 x1
	237	* SD1(F:H) => SLOT3 SGMII
	238	*/
	239	QIXIS_WRITE(brdcfg[12], 0x80);
	240	QIXIS_WRITE(brdcfg[13], 0x70);
	241	break;
	242	case 0xde:
	243	case 0xdf:
	244	/* SD1(A:D) => SLOT2 PCIe3 x4
	245	* SD1(E) => SLOT1 PCIe4 x1
	246	* SD1(F) => SLOT4 PCIe1 x1
	247	* SD1(G) => SLOT3 PCIe2 x1
	248	* SD1(H) => SLOT7 SGMII
	249	*/
	250	QIXIS_WRITE(brdcfg[12], 0x98);
	251	QIXIS_WRITE(brdcfg[13], 0x25);
	252	break;
	253	case 0xf2:
	254	/* SD1(A) => SLOT2 PCIe3 x1
	255	* SD1(B:D) => SLOT7 SGMII
	256	* SD1(E) => SLOT1 PCIe4 x1
	257	* SD1(F) => SLOT4 PCIe1 x1
	258	* SD1(G) => SLOT3 PCIe2 x1
	259	* SD1(H) => SLOT7 SGMII
	260	*/
	261	QIXIS_WRITE(brdcfg[12], 0x81);
	262	QIXIS_WRITE(brdcfg[13], 0xa5);
	263	break;
	264	#endif
c4d0e811 SL	265	default:
	266	printf("WARNING: unsupported for SerDes1 Protocol %d\n",
	267	srds_prtcl_s1);
	268	return -1;
	269	}
	270
254887a5	271	#ifdef CONFIG_T2080QDS
c4d0e811 SL	272	switch (srds_prtcl_s2) {
	273	case 0:
	274	/* SerDes2 is not enabled */
	275	break;
	276	case 0x01:
	277	case 0x02:
	278	/* SD2(A:H) => SLOT4 PCIe1 */
1576b558	279	QIXIS_WRITE(brdcfg[13], 0x10);
c4d0e811 SL	280	break;
	281	case 0x15:
	282	case 0x16:
	283	/*
	284	* SD2(A:D) => SLOT4 PCIe1
	285	* SD2(E:F) => SLOT5 PCIe2
	286	* SD2(G:H) => SATA1,SATA2
	287	*/
	288	QIXIS_WRITE(brdcfg[13], 0xb0);
	289	break;
	290	case 0x18:
	291	/*
	292	* SD2(A:D) => SLOT4 PCIe1
	293	* SD2(E:F) => SLOT5 Aurora
	294	* SD2(G:H) => SATA1,SATA2
	295	*/
1576b558	296	QIXIS_WRITE(brdcfg[13], 0x78);
c4d0e811 SL	297	break;
	298	case 0x1f:
	299	/*
	300	* SD2(A:D) => SLOT4 PCIe1
	301	* SD2(E:H) => SLOT5 PCIe2
	302	*/
	303	QIXIS_WRITE(brdcfg[13], 0xa0);
	304	break;
	305	case 0x29:
	306	case 0x2d:
	307	case 0x2e:
	308	/*
	309	* SD2(A:D) => SLOT4 SRIO2
	310	* SD2(E:H) => SLOT5 SRIO1
	311	*/
1576b558 SL	312	QIXIS_WRITE(brdcfg[13], 0xa0);
	313	break;
	314	case 0x36:
	315	/*
	316	* SD2(A:D) => SLOT4 SRIO2
	317	* SD2(E:F) => Aurora
	318	* SD2(G:H) => SATA1,SATA2
	319	*/
	320	QIXIS_WRITE(brdcfg[13], 0x78);
c4d0e811 SL	321	break;
	322	default:
	323	printf("WARNING: unsupported for SerDes2 Protocol %d\n",
	324	srds_prtcl_s2);
	325	return -1;
	326	}
254887a5	327	#endif
c4d0e811 SL	328	return 0;
	329	}
	330
	331	int board_early_init_r(void)
	332	{
	333	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
9d045682	334	int flash_esel = find_tlb_idx((void *)flashbase, 1);
c4d0e811 SL	335
	336	/*
	337	* Remap Boot flash + PROMJET region to caching-inhibited
	338	* so that flash can be erased properly.
	339	*/
	340
	341	/* Flush d-cache and invalidate i-cache of any FLASH data */
	342	flush_dcache();
	343	invalidate_icache();
	344
9d045682 YS	345	if (flash_esel == -1) {
	346	/* very unlikely unless something is messed up */
	347	puts("Error: Could not find TLB for FLASH BASE\n");
	348	flash_esel = 2; /* give our best effort to continue */
	349	} else {
	350	/* invalidate existing TLB entry for flash + promjet */
	351	disable_tlb(flash_esel);
	352	}
c4d0e811 SL	353
	354	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
	355	MAS3_SX\|MAS3_SW\|MAS3_SR, MAS2_I\|MAS2_G,
	356	0, flash_esel, BOOKE_PAGESZ_256M, 1);
	357
c4d0e811 SL	358	/* Disable remote I2C connection to qixis fpga */
	359	QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
	360
3ad2737e YZ	361	/*
	362	* Adjust core voltage according to voltage ID
	363	* This function changes I2C mux to channel 2.
	364	*/
	365	if (adjust_vdd(0))
	366	printf("Warning: Adjusting core voltage failed.\n");
	367
c4d0e811 SL	368	brd_mux_lane_to_slot();
	369	select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
	370
	371	return 0;
	372	}
	373
	374	unsigned long get_board_sys_clk(void)
	375	{
	376	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
	377	#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
	378	/* use accurate clock measurement */
	379	int freq = QIXIS_READ(clk_freq[0]) << 8 \| QIXIS_READ(clk_freq[1]);
	380	int base = QIXIS_READ(clk_base[0]) << 8 \| QIXIS_READ(clk_base[1]);
	381	u32 val;
	382
	383	val = freq * base;
	384	if (val) {
	385	debug("SYS Clock measurement is: %d\n", val);
	386	return val;
	387	} else {
	388	printf("Warning: SYS clock measurement is invalid, ");
	389	printf("using value from brdcfg1.\n");
	390	}
	391	#endif
	392
	393	switch (sysclk_conf & 0x0F) {
	394	case QIXIS_SYSCLK_83:
	395	return 83333333;
	396	case QIXIS_SYSCLK_100:
	397	return 100000000;
	398	case QIXIS_SYSCLK_125:
	399	return 125000000;
	400	case QIXIS_SYSCLK_133:
	401	return 133333333;
	402	case QIXIS_SYSCLK_150:
	403	return 150000000;
	404	case QIXIS_SYSCLK_160:
	405	return 160000000;
	406	case QIXIS_SYSCLK_166:
	407	return 166666666;
	408	}
	409	return 66666666;
	410	}
	411
	412	unsigned long get_board_ddr_clk(void)
	413	{
	414	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
	415	#ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
	416	/* use accurate clock measurement */
	417	int freq = QIXIS_READ(clk_freq[2]) << 8 \| QIXIS_READ(clk_freq[3]);
	418	int base = QIXIS_READ(clk_base[0]) << 8 \| QIXIS_READ(clk_base[1]);
	419	u32 val;
	420
	421	val = freq * base;
	422	if (val) {
	423	debug("DDR Clock measurement is: %d\n", val);
	424	return val;
	425	} else {
	426	printf("Warning: DDR clock measurement is invalid, ");
	427	printf("using value from brdcfg1.\n");
	428	}
	429	#endif
	430
	431	switch ((ddrclk_conf & 0x30) >> 4) {
432	case QIXIS_DDRCLK_100:
433	return 100000000;
434	case QIXIS_DDRCLK_125:
435	return 125000000;
436	case QIXIS_DDRCLK_133:
437	return 133333333;
438	}
439	return 66666666;
440	}
441
442	int misc_init_r(void)
443	{
444	return 0;
445	}
446
e895a4b0	447	int ft_board_setup(void blob, bd_t bd)
c4d0e811 SL	448	{
	449	phys_addr_t base;
	450	phys_size_t size;
	451
	452	ft_cpu_setup(blob, bd);
	453
	454	base = getenv_bootm_low();
	455	size = getenv_bootm_size();
	456
	457	fdt_fixup_memory(blob, (u64)base, (u64)size);
	458
	459	#ifdef CONFIG_PCI
	460	pci_of_setup(blob, bd);
	461	#endif
	462
	463	fdt_fixup_liodn(blob);
	464	fdt_fixup_dr_usb(blob, bd);
	465
	466	#ifdef CONFIG_SYS_DPAA_FMAN
	467	fdt_fixup_fman_ethernet(blob);
	468	fdt_fixup_board_enet(blob);
	469	#endif
e895a4b0 SG	470
e895a4b0 SG	471	return 0;
c4d0e811	472	}