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e56c5791 TH |
1 | /* |
2 | * Copyright (C) 2013 Gateworks Corporation | |
3 | * | |
4 | * Author: Tim Harvey <tharvey@gateworks.com> | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | */ | |
8 | ||
65da5c3b | 9 | #include <asm/arch/clock.h> |
e56c5791 TH |
10 | #include <asm/arch/mx6-pins.h> |
11 | #include <asm/arch/sys_proto.h> | |
12 | #include <asm/gpio.h> | |
13 | #include <asm/imx-common/mxc_i2c.h> | |
65da5c3b | 14 | #include <fsl_esdhc.h> |
e56c5791 TH |
15 | #include <hwconfig.h> |
16 | #include <power/pmic.h> | |
17 | #include <power/ltc3676_pmic.h> | |
18 | #include <power/pfuze100_pmic.h> | |
19 | ||
20 | #include "common.h" | |
21 | ||
22 | /* UART1: Function varies per baseboard */ | |
23 | static iomux_v3_cfg_t const uart1_pads[] = { | |
24 | IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
25 | IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
26 | }; | |
27 | ||
28 | /* UART2: Serial Console */ | |
29 | static iomux_v3_cfg_t const uart2_pads[] = { | |
30 | IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
31 | IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), | |
32 | }; | |
33 | ||
34 | void setup_iomux_uart(void) | |
35 | { | |
36 | SETUP_IOMUX_PADS(uart1_pads); | |
37 | SETUP_IOMUX_PADS(uart2_pads); | |
38 | } | |
39 | ||
65da5c3b | 40 | /* MMC */ |
8d1a6ff8 TH |
41 | static iomux_v3_cfg_t const gw5904_emmc_pads[] = { |
42 | IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
43 | IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
44 | IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
45 | IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
46 | IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
47 | IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
48 | IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
49 | IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
50 | IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
51 | IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
52 | IOMUX_PADS(PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
53 | }; | |
94a1d6c6 TH |
54 | /* 8-bit eMMC on SD2/NAND */ |
55 | static iomux_v3_cfg_t const gw560x_emmc_sd2_pads[] = { | |
56 | IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
57 | IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
58 | IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
59 | IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
60 | IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
61 | IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
62 | IOMUX_PADS(PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
63 | IOMUX_PADS(PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
64 | IOMUX_PADS(PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
65 | IOMUX_PADS(PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
66 | }; | |
67 | ||
65da5c3b TH |
68 | static iomux_v3_cfg_t const usdhc3_pads[] = { |
69 | IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
70 | IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
71 | IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
72 | IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
73 | IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
74 | IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
75 | IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), | |
76 | }; | |
77 | ||
e56c5791 TH |
78 | /* I2C1: GSC */ |
79 | static struct i2c_pads_info mx6q_i2c_pad_info0 = { | |
80 | .scl = { | |
81 | .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC, | |
82 | .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC, | |
83 | .gp = IMX_GPIO_NR(3, 21) | |
84 | }, | |
85 | .sda = { | |
86 | .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC, | |
87 | .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC, | |
88 | .gp = IMX_GPIO_NR(3, 28) | |
89 | } | |
90 | }; | |
91 | static struct i2c_pads_info mx6dl_i2c_pad_info0 = { | |
92 | .scl = { | |
93 | .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC, | |
94 | .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC, | |
95 | .gp = IMX_GPIO_NR(3, 21) | |
96 | }, | |
97 | .sda = { | |
98 | .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC, | |
99 | .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC, | |
100 | .gp = IMX_GPIO_NR(3, 28) | |
101 | } | |
102 | }; | |
103 | ||
104 | /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */ | |
105 | static struct i2c_pads_info mx6q_i2c_pad_info1 = { | |
106 | .scl = { | |
107 | .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC, | |
108 | .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC, | |
109 | .gp = IMX_GPIO_NR(4, 12) | |
110 | }, | |
111 | .sda = { | |
112 | .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC, | |
113 | .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC, | |
114 | .gp = IMX_GPIO_NR(4, 13) | |
115 | } | |
116 | }; | |
117 | static struct i2c_pads_info mx6dl_i2c_pad_info1 = { | |
118 | .scl = { | |
119 | .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC, | |
120 | .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC, | |
121 | .gp = IMX_GPIO_NR(4, 12) | |
122 | }, | |
123 | .sda = { | |
124 | .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC, | |
125 | .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC, | |
126 | .gp = IMX_GPIO_NR(4, 13) | |
127 | } | |
128 | }; | |
129 | ||
130 | /* I2C3: Misc/Expansion */ | |
131 | static struct i2c_pads_info mx6q_i2c_pad_info2 = { | |
132 | .scl = { | |
133 | .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC, | |
134 | .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC, | |
135 | .gp = IMX_GPIO_NR(1, 3) | |
136 | }, | |
137 | .sda = { | |
138 | .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC, | |
139 | .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC, | |
140 | .gp = IMX_GPIO_NR(1, 6) | |
141 | } | |
142 | }; | |
143 | static struct i2c_pads_info mx6dl_i2c_pad_info2 = { | |
144 | .scl = { | |
145 | .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC, | |
146 | .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC, | |
147 | .gp = IMX_GPIO_NR(1, 3) | |
148 | }, | |
149 | .sda = { | |
150 | .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC, | |
151 | .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC, | |
152 | .gp = IMX_GPIO_NR(1, 6) | |
153 | } | |
154 | }; | |
155 | ||
156 | void setup_ventana_i2c(void) | |
157 | { | |
158 | if (is_cpu_type(MXC_CPU_MX6Q)) { | |
159 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0); | |
160 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1); | |
161 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2); | |
162 | } else { | |
163 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0); | |
164 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1); | |
165 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2); | |
166 | } | |
167 | } | |
168 | ||
169 | /* | |
170 | * Baseboard specific GPIO | |
171 | */ | |
172 | ||
e56c5791 TH |
173 | /* prototype */ |
174 | static iomux_v3_cfg_t const gwproto_gpio_pads[] = { | |
e49621b3 TH |
175 | /* RS232_EN# */ |
176 | IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), | |
e56c5791 TH |
177 | /* PANLEDG# */ |
178 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
179 | /* PANLEDR# */ | |
180 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
181 | /* LOCLED# */ | |
182 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
183 | /* RS485_EN */ | |
184 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
185 | /* IOEXP_PWREN# */ | |
186 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
187 | /* IOEXP_IRQ# */ | |
188 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
189 | /* VID_EN */ | |
190 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
191 | /* DIOI2C_DIS# */ | |
192 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
193 | /* PCICK_SSON */ | |
194 | IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | DIO_PAD_CFG), | |
195 | /* PCI_RST# */ | |
196 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
197 | }; | |
198 | ||
199 | static iomux_v3_cfg_t const gw51xx_gpio_pads[] = { | |
200 | /* PANLEDG# */ | |
201 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
202 | /* PANLEDR# */ | |
203 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
204 | /* IOEXP_PWREN# */ | |
205 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
206 | /* IOEXP_IRQ# */ | |
207 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
208 | ||
209 | /* GPS_SHDN */ | |
210 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
211 | /* VID_PWR */ | |
212 | IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), | |
213 | /* PCI_RST# */ | |
214 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), | |
215 | /* PCIESKT_WDIS# */ | |
216 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
217 | }; | |
218 | ||
219 | static iomux_v3_cfg_t const gw52xx_gpio_pads[] = { | |
f3a8546b TH |
220 | /* SD3_VSELECT */ |
221 | IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), | |
e49621b3 TH |
222 | /* RS232_EN# */ |
223 | IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), | |
5c55572f TH |
224 | /* MSATA_EN */ |
225 | IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), | |
e56c5791 TH |
226 | /* PANLEDG# */ |
227 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
228 | /* PANLEDR# */ | |
229 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
230 | /* IOEXP_PWREN# */ | |
231 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
232 | /* IOEXP_IRQ# */ | |
233 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
9a83a815 TH |
234 | /* CAN_STBY */ |
235 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
236 | /* MX6_LOCLED# */ |
237 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
238 | /* GPS_SHDN */ | |
239 | IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), | |
240 | /* USBOTG_SEL */ | |
241 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
242 | /* VID_PWR */ | |
243 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
244 | /* PCI_RST# */ | |
245 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
246 | /* PCI_RST# (GW522x) */ | |
247 | IOMUX_PADS(PAD_EIM_D23__GPIO3_IO23 | DIO_PAD_CFG), | |
9a83a815 TH |
248 | /* RS485_EN */ |
249 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
e56c5791 TH |
250 | /* PCIESKT_WDIS# */ |
251 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
252 | }; | |
253 | ||
254 | static iomux_v3_cfg_t const gw53xx_gpio_pads[] = { | |
f3a8546b TH |
255 | /* SD3_VSELECT */ |
256 | IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), | |
e49621b3 TH |
257 | /* RS232_EN# */ |
258 | IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), | |
5c55572f TH |
259 | /* MSATA_EN */ |
260 | IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), | |
9a83a815 TH |
261 | /* CAN_STBY */ |
262 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
263 | /* USB_HUBRST# */ | |
264 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
265 | /* PANLEDG# */ |
266 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
267 | /* PANLEDR# */ | |
268 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
269 | /* MX6_LOCLED# */ | |
270 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
271 | /* IOEXP_PWREN# */ | |
272 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
273 | /* IOEXP_IRQ# */ | |
274 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
275 | /* DIOI2C_DIS# */ | |
276 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
277 | /* GPS_SHDN */ | |
278 | IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | DIO_PAD_CFG), | |
279 | /* VID_EN */ | |
280 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
281 | /* PCI_RST# */ | |
282 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
9a83a815 TH |
283 | /* RS485_EN */ |
284 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
e56c5791 TH |
285 | /* PCIESKT_WDIS# */ |
286 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
287 | }; | |
288 | ||
289 | static iomux_v3_cfg_t const gw54xx_gpio_pads[] = { | |
f3a8546b TH |
290 | /* SD3_VSELECT */ |
291 | IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), | |
e49621b3 TH |
292 | /* RS232_EN# */ |
293 | IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), | |
5c55572f TH |
294 | /* MSATA_EN */ |
295 | IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), | |
9a83a815 TH |
296 | /* CAN_STBY */ |
297 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
e56c5791 TH |
298 | /* PANLEDG# */ |
299 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
300 | /* PANLEDR# */ | |
9a83a815 | 301 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), |
e56c5791 TH |
302 | /* MX6_LOCLED# */ |
303 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
9a83a815 TH |
304 | /* USB_HUBRST# */ |
305 | IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16 | DIO_PAD_CFG), | |
e56c5791 TH |
306 | /* MIPI_DIO */ |
307 | IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | DIO_PAD_CFG), | |
308 | /* RS485_EN */ | |
309 | IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | DIO_PAD_CFG), | |
310 | /* IOEXP_PWREN# */ | |
9a83a815 | 311 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), |
e56c5791 | 312 | /* IOEXP_IRQ# */ |
9a83a815 | 313 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), |
e56c5791 TH |
314 | /* DIOI2C_DIS# */ |
315 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
316 | /* PCI_RST# */ | |
317 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
318 | /* VID_EN */ | |
319 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
9a83a815 TH |
320 | /* RS485_EN */ |
321 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
e56c5791 TH |
322 | /* PCIESKT_WDIS# */ |
323 | IOMUX_PADS(PAD_DISP0_DAT23__GPIO5_IO17 | DIO_PAD_CFG), | |
324 | }; | |
325 | ||
326 | static iomux_v3_cfg_t const gw551x_gpio_pads[] = { | |
9a83a815 TH |
327 | /* CAN_STBY */ |
328 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
329 | /* PANLED# */ |
330 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
331 | /* PCI_RST# */ | |
332 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), | |
333 | /* PCIESKT_WDIS# */ | |
334 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
335 | }; | |
336 | ||
337 | static iomux_v3_cfg_t const gw552x_gpio_pads[] = { | |
5c55572f TH |
338 | /* MSATA_EN */ |
339 | IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | DIO_PAD_CFG), | |
9a83a815 TH |
340 | /* USBOTG_SEL */ |
341 | IOMUX_PADS(PAD_GPIO_7__GPIO1_IO07 | DIO_PAD_CFG), | |
342 | /* USB_HUBRST# */ | |
343 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
e56c5791 TH |
344 | /* PANLEDG# */ |
345 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
346 | /* PANLEDR# */ | |
347 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
348 | /* MX6_LOCLED# */ | |
349 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
350 | /* PCI_RST# */ | |
351 | IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | DIO_PAD_CFG), | |
352 | /* MX6_DIO[4:9] */ | |
353 | IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18 | DIO_PAD_CFG), | |
354 | IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), | |
355 | IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21 | DIO_PAD_CFG), | |
356 | IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22 | DIO_PAD_CFG), | |
357 | IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23 | DIO_PAD_CFG), | |
358 | IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25 | DIO_PAD_CFG), | |
359 | /* PCIEGBE1_OFF# */ | |
360 | IOMUX_PADS(PAD_GPIO_1__GPIO1_IO01 | DIO_PAD_CFG), | |
361 | /* PCIEGBE2_OFF# */ | |
362 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
363 | /* PCIESKT_WDIS# */ | |
364 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
365 | }; | |
366 | ||
385575bc | 367 | static iomux_v3_cfg_t const gw553x_gpio_pads[] = { |
f3a8546b TH |
368 | /* SD3_VSELECT */ |
369 | IOMUX_PADS(PAD_NANDF_CS1__GPIO6_IO14 | DIO_PAD_CFG), | |
385575bc TH |
370 | /* PANLEDG# */ |
371 | IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | DIO_PAD_CFG), | |
372 | /* PANLEDR# */ | |
373 | IOMUX_PADS(PAD_KEY_ROW2__GPIO4_IO11 | DIO_PAD_CFG), | |
385575bc TH |
374 | /* VID_PWR */ |
375 | IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | DIO_PAD_CFG), | |
376 | /* PCI_RST# */ | |
377 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), | |
378 | /* PCIESKT_WDIS# */ | |
379 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
380 | }; | |
381 | ||
94a1d6c6 TH |
382 | static iomux_v3_cfg_t const gw560x_gpio_pads[] = { |
383 | /* RS232_EN# */ | |
384 | IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | DIO_PAD_CFG), | |
385 | /* CAN_STBY */ | |
386 | IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | DIO_PAD_CFG), | |
387 | /* USB_HUBRST# */ | |
388 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
389 | /* PANLEDG# */ | |
390 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
391 | /* PANLEDR# */ | |
392 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
393 | /* MX6_LOCLED# */ | |
394 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
395 | /* IOEXP_PWREN# */ | |
396 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
397 | /* IOEXP_IRQ# */ | |
398 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
399 | /* DIOI2C_DIS# */ | |
400 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
401 | /* VID_EN */ | |
402 | IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | DIO_PAD_CFG), | |
403 | /* PCI_RST# */ | |
404 | IOMUX_PADS(PAD_DISP0_DAT10__GPIO4_IO31 | DIO_PAD_CFG), | |
405 | /* RS485_EN */ | |
406 | IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | DIO_PAD_CFG), | |
407 | /* PCIESKT_WDIS# */ | |
408 | IOMUX_PADS(PAD_GPIO_17__GPIO7_IO12 | DIO_PAD_CFG), | |
409 | /* USBH2_PEN (OTG) */ | |
410 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
411 | /* 12V0_PWR_EN */ | |
412 | IOMUX_PADS(PAD_DISP0_DAT5__GPIO4_IO26 | DIO_PAD_CFG), | |
413 | }; | |
414 | ||
8d1a6ff8 TH |
415 | static iomux_v3_cfg_t const gw5904_gpio_pads[] = { |
416 | /* USB_HUBRST# */ | |
417 | IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09 | DIO_PAD_CFG), | |
418 | /* PANLEDG# */ | |
419 | IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | DIO_PAD_CFG), | |
420 | /* PANLEDR# */ | |
421 | IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | DIO_PAD_CFG), | |
422 | /* MX6_LOCLED# */ | |
423 | IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | DIO_PAD_CFG), | |
424 | /* IOEXP_PWREN# */ | |
425 | IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | DIO_PAD_CFG), | |
426 | /* IOEXP_IRQ# */ | |
427 | IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(IRQ_PAD_CTRL)), | |
428 | /* DIOI2C_DIS# */ | |
429 | IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | DIO_PAD_CFG), | |
430 | /* UART_RS485 */ | |
431 | IOMUX_PADS(PAD_DISP0_DAT2__GPIO4_IO23 | DIO_PAD_CFG), | |
432 | /* UART_HALF */ | |
433 | IOMUX_PADS(PAD_DISP0_DAT3__GPIO4_IO24 | DIO_PAD_CFG), | |
434 | /* SKT1_WDIS# */ | |
435 | IOMUX_PADS(PAD_DISP0_DAT17__GPIO5_IO11 | DIO_PAD_CFG), | |
436 | /* SKT1_RST# */ | |
437 | IOMUX_PADS(PAD_DISP0_DAT18__GPIO5_IO12 | DIO_PAD_CFG), | |
438 | /* SKT2_WDIS# */ | |
439 | IOMUX_PADS(PAD_DISP0_DAT19__GPIO5_IO13 | DIO_PAD_CFG), | |
440 | /* SKT2_RST# */ | |
441 | IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | DIO_PAD_CFG), | |
442 | /* M2_OFF# */ | |
443 | IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | DIO_PAD_CFG), | |
444 | /* M2_WDIS# */ | |
445 | IOMUX_PADS(PAD_SD2_DAT1__GPIO1_IO14 | DIO_PAD_CFG), | |
446 | /* M2_RST# */ | |
447 | IOMUX_PADS(PAD_SD2_DAT2__GPIO1_IO13 | DIO_PAD_CFG), | |
448 | }; | |
449 | ||
1800ffa8 TH |
450 | /* Digital I/O */ |
451 | struct dio_cfg gw51xx_dio[] = { | |
452 | { | |
453 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
454 | IMX_GPIO_NR(1, 16), | |
455 | { 0, 0 }, | |
456 | 0 | |
457 | }, | |
458 | { | |
459 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
460 | IMX_GPIO_NR(1, 19), | |
461 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
462 | 2 | |
463 | }, | |
464 | { | |
465 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
466 | IMX_GPIO_NR(1, 17), | |
467 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
468 | 3 | |
469 | }, | |
470 | { | |
471 | { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, | |
472 | IMX_GPIO_NR(1, 18), | |
473 | { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, | |
474 | 4 | |
475 | }, | |
476 | }; | |
477 | ||
478 | struct dio_cfg gw52xx_dio[] = { | |
479 | { | |
480 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
481 | IMX_GPIO_NR(1, 16), | |
482 | { 0, 0 }, | |
483 | 0 | |
484 | }, | |
485 | { | |
486 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
487 | IMX_GPIO_NR(1, 19), | |
488 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
489 | 2 | |
490 | }, | |
491 | { | |
492 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
493 | IMX_GPIO_NR(1, 17), | |
494 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
495 | 3 | |
496 | }, | |
497 | { | |
498 | { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
499 | IMX_GPIO_NR(1, 20), | |
500 | { 0, 0 }, | |
501 | 0 | |
502 | }, | |
503 | }; | |
504 | ||
505 | struct dio_cfg gw53xx_dio[] = { | |
506 | { | |
507 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
508 | IMX_GPIO_NR(1, 16), | |
509 | { 0, 0 }, | |
510 | 0 | |
511 | }, | |
512 | { | |
513 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
514 | IMX_GPIO_NR(1, 19), | |
515 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
516 | 2 | |
517 | }, | |
518 | { | |
519 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
520 | IMX_GPIO_NR(1, 17), | |
521 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
522 | 3 | |
523 | }, | |
524 | { | |
525 | {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
526 | IMX_GPIO_NR(1, 20), | |
527 | { 0, 0 }, | |
528 | 0 | |
529 | }, | |
530 | }; | |
531 | ||
532 | struct dio_cfg gw54xx_dio[] = { | |
533 | { | |
534 | { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) }, | |
535 | IMX_GPIO_NR(1, 9), | |
536 | { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) }, | |
537 | 1 | |
538 | }, | |
539 | { | |
540 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
541 | IMX_GPIO_NR(1, 19), | |
542 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
543 | 2 | |
544 | }, | |
545 | { | |
546 | { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) }, | |
547 | IMX_GPIO_NR(2, 9), | |
548 | { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) }, | |
549 | 3 | |
550 | }, | |
551 | { | |
552 | { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) }, | |
553 | IMX_GPIO_NR(2, 10), | |
554 | { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) }, | |
555 | 4 | |
556 | }, | |
557 | }; | |
558 | ||
559 | struct dio_cfg gw551x_dio[] = { | |
560 | { | |
561 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
562 | IMX_GPIO_NR(1, 19), | |
563 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
564 | 2 | |
565 | }, | |
566 | { | |
567 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
568 | IMX_GPIO_NR(1, 17), | |
569 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
570 | 3 | |
571 | }, | |
572 | }; | |
573 | ||
574 | struct dio_cfg gw552x_dio[] = { | |
575 | { | |
576 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
577 | IMX_GPIO_NR(1, 16), | |
578 | { 0, 0 }, | |
579 | 0 | |
580 | }, | |
581 | { | |
582 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
583 | IMX_GPIO_NR(1, 19), | |
584 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
585 | 2 | |
586 | }, | |
587 | { | |
588 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
589 | IMX_GPIO_NR(1, 17), | |
590 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
591 | 3 | |
592 | }, | |
593 | { | |
594 | {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
595 | IMX_GPIO_NR(1, 20), | |
596 | { 0, 0 }, | |
597 | 0 | |
598 | }, | |
e86b7adf TH |
599 | { |
600 | {IOMUX_PADS(PAD_CSI0_PIXCLK__GPIO5_IO18) }, | |
601 | IMX_GPIO_NR(5, 18), | |
602 | { 0, 0 }, | |
603 | 0 | |
604 | }, | |
605 | { | |
606 | {IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20) }, | |
607 | IMX_GPIO_NR(5, 20), | |
608 | { 0, 0 }, | |
609 | 0 | |
610 | }, | |
611 | { | |
612 | {IOMUX_PADS(PAD_CSI0_VSYNC__GPIO5_IO21) }, | |
613 | IMX_GPIO_NR(5, 21), | |
614 | { 0, 0 }, | |
615 | 0 | |
616 | }, | |
617 | { | |
618 | {IOMUX_PADS(PAD_CSI0_DAT4__GPIO5_IO22) }, | |
619 | IMX_GPIO_NR(5, 22), | |
620 | { 0, 0 }, | |
621 | 0 | |
622 | }, | |
623 | { | |
624 | {IOMUX_PADS(PAD_CSI0_DAT5__GPIO5_IO23) }, | |
625 | IMX_GPIO_NR(5, 23), | |
626 | { 0, 0 }, | |
627 | 0 | |
628 | }, | |
629 | { | |
630 | {IOMUX_PADS(PAD_CSI0_DAT7__GPIO5_IO25) }, | |
631 | IMX_GPIO_NR(5, 25), | |
632 | { 0, 0 }, | |
633 | 0 | |
634 | }, | |
1800ffa8 TH |
635 | }; |
636 | ||
637 | struct dio_cfg gw553x_dio[] = { | |
638 | { | |
639 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
640 | IMX_GPIO_NR(1, 16), | |
641 | { 0, 0 }, | |
642 | 0 | |
643 | }, | |
644 | { | |
645 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
646 | IMX_GPIO_NR(1, 19), | |
647 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
648 | 2 | |
649 | }, | |
650 | { | |
651 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
652 | IMX_GPIO_NR(1, 17), | |
653 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
654 | 3 | |
655 | }, | |
656 | { | |
657 | { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) }, | |
658 | IMX_GPIO_NR(1, 18), | |
659 | { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) }, | |
660 | 4 | |
661 | }, | |
662 | }; | |
e56c5791 | 663 | |
94a1d6c6 TH |
664 | struct dio_cfg gw560x_dio[] = { |
665 | { | |
666 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
667 | IMX_GPIO_NR(1, 16), | |
668 | { 0, 0 }, | |
669 | 0 | |
670 | }, | |
671 | { | |
672 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
673 | IMX_GPIO_NR(1, 19), | |
674 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
675 | 2 | |
676 | }, | |
677 | { | |
678 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
679 | IMX_GPIO_NR(1, 17), | |
680 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
681 | 3 | |
682 | }, | |
683 | { | |
684 | {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
685 | IMX_GPIO_NR(1, 20), | |
686 | { 0, 0 }, | |
687 | 0 | |
688 | }, | |
689 | }; | |
690 | ||
8d1a6ff8 TH |
691 | struct dio_cfg gw5904_dio[] = { |
692 | { | |
693 | { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) }, | |
694 | IMX_GPIO_NR(1, 16), | |
695 | { 0, 0 }, | |
696 | 0 | |
697 | }, | |
698 | { | |
699 | { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) }, | |
700 | IMX_GPIO_NR(1, 19), | |
701 | { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) }, | |
702 | 2 | |
703 | }, | |
704 | { | |
705 | { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) }, | |
706 | IMX_GPIO_NR(1, 17), | |
707 | { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) }, | |
708 | 3 | |
709 | }, | |
710 | { | |
711 | {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) }, | |
712 | IMX_GPIO_NR(1, 20), | |
713 | { 0, 0 }, | |
714 | 0 | |
715 | }, | |
716 | { | |
717 | {IOMUX_PADS(PAD_NANDF_D0__GPIO2_IO00) }, | |
718 | IMX_GPIO_NR(2, 0), | |
719 | { 0, 0 }, | |
720 | 0 | |
721 | }, | |
722 | { | |
723 | {IOMUX_PADS(PAD_NANDF_D1__GPIO2_IO01) }, | |
724 | IMX_GPIO_NR(2, 1), | |
725 | { 0, 0 }, | |
726 | 0 | |
727 | }, | |
728 | { | |
729 | {IOMUX_PADS(PAD_NANDF_D2__GPIO2_IO02) }, | |
730 | IMX_GPIO_NR(2, 2), | |
731 | { 0, 0 }, | |
732 | 0 | |
733 | }, | |
734 | { | |
735 | {IOMUX_PADS(PAD_NANDF_D3__GPIO2_IO03) }, | |
736 | IMX_GPIO_NR(2, 3), | |
737 | { 0, 0 }, | |
738 | 0 | |
739 | }, | |
740 | { | |
741 | {IOMUX_PADS(PAD_NANDF_D4__GPIO2_IO04) }, | |
742 | IMX_GPIO_NR(2, 4), | |
743 | { 0, 0 }, | |
744 | 0 | |
745 | }, | |
746 | { | |
747 | {IOMUX_PADS(PAD_NANDF_D5__GPIO2_IO05) }, | |
748 | IMX_GPIO_NR(2, 5), | |
749 | { 0, 0 }, | |
750 | 0 | |
751 | }, | |
752 | { | |
753 | {IOMUX_PADS(PAD_NANDF_D6__GPIO2_IO06) }, | |
754 | IMX_GPIO_NR(2, 6), | |
755 | { 0, 0 }, | |
756 | 0 | |
757 | }, | |
758 | { | |
759 | {IOMUX_PADS(PAD_NANDF_D7__GPIO2_IO07) }, | |
760 | IMX_GPIO_NR(2, 7), | |
761 | { 0, 0 }, | |
762 | 0 | |
763 | }, | |
764 | }; | |
765 | ||
e56c5791 TH |
766 | /* |
767 | * Board Specific GPIO | |
768 | */ | |
769 | struct ventana gpio_cfg[GW_UNKNOWN] = { | |
770 | /* GW5400proto */ | |
771 | { | |
772 | .gpio_pads = gw54xx_gpio_pads, | |
773 | .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, | |
1800ffa8 TH |
774 | .dio_cfg = gw54xx_dio, |
775 | .dio_num = ARRAY_SIZE(gw54xx_dio), | |
e56c5791 TH |
776 | .leds = { |
777 | IMX_GPIO_NR(4, 6), | |
778 | IMX_GPIO_NR(4, 10), | |
779 | IMX_GPIO_NR(4, 15), | |
780 | }, | |
781 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
782 | .mezz_pwren = IMX_GPIO_NR(4, 7), | |
783 | .mezz_irq = IMX_GPIO_NR(4, 9), | |
784 | .rs485en = IMX_GPIO_NR(3, 24), | |
785 | .dioi2c_en = IMX_GPIO_NR(4, 5), | |
786 | .pcie_sson = IMX_GPIO_NR(1, 20), | |
f938500f | 787 | .otgpwr_en = IMX_GPIO_NR(3, 22), |
8d1a6ff8 | 788 | .mmc_cd = IMX_GPIO_NR(7, 0), |
e56c5791 TH |
789 | }, |
790 | ||
791 | /* GW51xx */ | |
792 | { | |
793 | .gpio_pads = gw51xx_gpio_pads, | |
794 | .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2, | |
1800ffa8 TH |
795 | .dio_cfg = gw51xx_dio, |
796 | .dio_num = ARRAY_SIZE(gw51xx_dio), | |
e56c5791 TH |
797 | .leds = { |
798 | IMX_GPIO_NR(4, 6), | |
799 | IMX_GPIO_NR(4, 10), | |
800 | }, | |
801 | .pcie_rst = IMX_GPIO_NR(1, 0), | |
802 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
803 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
804 | .gps_shdn = IMX_GPIO_NR(1, 2), | |
805 | .vidin_en = IMX_GPIO_NR(5, 20), | |
806 | .wdis = IMX_GPIO_NR(7, 12), | |
f938500f | 807 | .otgpwr_en = IMX_GPIO_NR(3, 22), |
e56c5791 TH |
808 | }, |
809 | ||
810 | /* GW52xx */ | |
811 | { | |
812 | .gpio_pads = gw52xx_gpio_pads, | |
813 | .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2, | |
1800ffa8 TH |
814 | .dio_cfg = gw52xx_dio, |
815 | .dio_num = ARRAY_SIZE(gw52xx_dio), | |
e56c5791 TH |
816 | .leds = { |
817 | IMX_GPIO_NR(4, 6), | |
818 | IMX_GPIO_NR(4, 7), | |
819 | IMX_GPIO_NR(4, 15), | |
820 | }, | |
821 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
822 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
823 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
824 | .gps_shdn = IMX_GPIO_NR(1, 27), | |
825 | .vidin_en = IMX_GPIO_NR(3, 31), | |
826 | .usb_sel = IMX_GPIO_NR(1, 2), | |
827 | .wdis = IMX_GPIO_NR(7, 12), | |
5c55572f | 828 | .msata_en = GP_MSATA_SEL, |
e49621b3 | 829 | .rs232_en = GP_RS232_EN, |
f938500f | 830 | .otgpwr_en = IMX_GPIO_NR(3, 22), |
f3a8546b | 831 | .vsel_pin = IMX_GPIO_NR(6, 14), |
8d1a6ff8 | 832 | .mmc_cd = IMX_GPIO_NR(7, 0), |
e56c5791 TH |
833 | }, |
834 | ||
835 | /* GW53xx */ | |
836 | { | |
837 | .gpio_pads = gw53xx_gpio_pads, | |
838 | .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2, | |
1800ffa8 TH |
839 | .dio_cfg = gw53xx_dio, |
840 | .dio_num = ARRAY_SIZE(gw53xx_dio), | |
e56c5791 TH |
841 | .leds = { |
842 | IMX_GPIO_NR(4, 6), | |
843 | IMX_GPIO_NR(4, 7), | |
844 | IMX_GPIO_NR(4, 15), | |
845 | }, | |
846 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
847 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
848 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
849 | .gps_shdn = IMX_GPIO_NR(1, 27), | |
850 | .vidin_en = IMX_GPIO_NR(3, 31), | |
851 | .wdis = IMX_GPIO_NR(7, 12), | |
5c55572f | 852 | .msata_en = GP_MSATA_SEL, |
e49621b3 | 853 | .rs232_en = GP_RS232_EN, |
f938500f | 854 | .otgpwr_en = IMX_GPIO_NR(3, 22), |
f3a8546b | 855 | .vsel_pin = IMX_GPIO_NR(6, 14), |
8d1a6ff8 | 856 | .mmc_cd = IMX_GPIO_NR(7, 0), |
e56c5791 TH |
857 | }, |
858 | ||
859 | /* GW54xx */ | |
860 | { | |
861 | .gpio_pads = gw54xx_gpio_pads, | |
862 | .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2, | |
1800ffa8 TH |
863 | .dio_cfg = gw54xx_dio, |
864 | .dio_num = ARRAY_SIZE(gw54xx_dio), | |
e56c5791 TH |
865 | .leds = { |
866 | IMX_GPIO_NR(4, 6), | |
867 | IMX_GPIO_NR(4, 7), | |
868 | IMX_GPIO_NR(4, 15), | |
869 | }, | |
870 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
871 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
872 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
873 | .rs485en = IMX_GPIO_NR(7, 1), | |
874 | .vidin_en = IMX_GPIO_NR(3, 31), | |
875 | .dioi2c_en = IMX_GPIO_NR(4, 5), | |
876 | .pcie_sson = IMX_GPIO_NR(1, 20), | |
877 | .wdis = IMX_GPIO_NR(5, 17), | |
5c55572f | 878 | .msata_en = GP_MSATA_SEL, |
e49621b3 | 879 | .rs232_en = GP_RS232_EN, |
f938500f | 880 | .otgpwr_en = IMX_GPIO_NR(3, 22), |
f3a8546b | 881 | .vsel_pin = IMX_GPIO_NR(6, 14), |
8d1a6ff8 | 882 | .mmc_cd = IMX_GPIO_NR(7, 0), |
e56c5791 TH |
883 | }, |
884 | ||
885 | /* GW551x */ | |
886 | { | |
887 | .gpio_pads = gw551x_gpio_pads, | |
888 | .num_pads = ARRAY_SIZE(gw551x_gpio_pads)/2, | |
1800ffa8 TH |
889 | .dio_cfg = gw551x_dio, |
890 | .dio_num = ARRAY_SIZE(gw551x_dio), | |
e56c5791 TH |
891 | .leds = { |
892 | IMX_GPIO_NR(4, 7), | |
893 | }, | |
894 | .pcie_rst = IMX_GPIO_NR(1, 0), | |
895 | .wdis = IMX_GPIO_NR(7, 12), | |
896 | }, | |
897 | ||
898 | /* GW552x */ | |
899 | { | |
900 | .gpio_pads = gw552x_gpio_pads, | |
901 | .num_pads = ARRAY_SIZE(gw552x_gpio_pads)/2, | |
1800ffa8 TH |
902 | .dio_cfg = gw552x_dio, |
903 | .dio_num = ARRAY_SIZE(gw552x_dio), | |
e56c5791 TH |
904 | .leds = { |
905 | IMX_GPIO_NR(4, 6), | |
906 | IMX_GPIO_NR(4, 7), | |
907 | IMX_GPIO_NR(4, 15), | |
908 | }, | |
909 | .pcie_rst = IMX_GPIO_NR(1, 29), | |
9a83a815 | 910 | .usb_sel = IMX_GPIO_NR(1, 7), |
e56c5791 | 911 | .wdis = IMX_GPIO_NR(7, 12), |
5c55572f | 912 | .msata_en = GP_MSATA_SEL, |
e56c5791 | 913 | }, |
385575bc TH |
914 | |
915 | /* GW553x */ | |
916 | { | |
917 | .gpio_pads = gw553x_gpio_pads, | |
918 | .num_pads = ARRAY_SIZE(gw553x_gpio_pads)/2, | |
1800ffa8 TH |
919 | .dio_cfg = gw553x_dio, |
920 | .dio_num = ARRAY_SIZE(gw553x_dio), | |
385575bc TH |
921 | .leds = { |
922 | IMX_GPIO_NR(4, 10), | |
923 | IMX_GPIO_NR(4, 11), | |
924 | }, | |
925 | .pcie_rst = IMX_GPIO_NR(1, 0), | |
926 | .vidin_en = IMX_GPIO_NR(5, 20), | |
927 | .wdis = IMX_GPIO_NR(7, 12), | |
f938500f | 928 | .otgpwr_en = IMX_GPIO_NR(3, 22), |
f3a8546b | 929 | .vsel_pin = IMX_GPIO_NR(6, 14), |
8d1a6ff8 TH |
930 | .mmc_cd = IMX_GPIO_NR(7, 0), |
931 | }, | |
932 | ||
94a1d6c6 TH |
933 | /* GW560x */ |
934 | { | |
935 | .gpio_pads = gw560x_gpio_pads, | |
936 | .num_pads = ARRAY_SIZE(gw560x_gpio_pads)/2, | |
937 | .dio_cfg = gw560x_dio, | |
938 | .dio_num = ARRAY_SIZE(gw560x_dio), | |
939 | .leds = { | |
940 | IMX_GPIO_NR(4, 6), | |
941 | IMX_GPIO_NR(4, 7), | |
942 | IMX_GPIO_NR(4, 15), | |
943 | }, | |
944 | .pcie_rst = IMX_GPIO_NR(4, 31), | |
945 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
946 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
947 | .rs232_en = GP_RS232_EN, | |
948 | .vidin_en = IMX_GPIO_NR(3, 31), | |
949 | .wdis = IMX_GPIO_NR(7, 12), | |
950 | .otgpwr_en = IMX_GPIO_NR(4, 15), | |
951 | .mmc_cd = IMX_GPIO_NR(7, 0), | |
952 | }, | |
953 | ||
8d1a6ff8 TH |
954 | /* GW5904 */ |
955 | { | |
956 | .gpio_pads = gw5904_gpio_pads, | |
957 | .num_pads = ARRAY_SIZE(gw5904_gpio_pads)/2, | |
958 | .dio_cfg = gw5904_dio, | |
959 | .dio_num = ARRAY_SIZE(gw5904_dio), | |
960 | .leds = { | |
961 | IMX_GPIO_NR(4, 6), | |
962 | IMX_GPIO_NR(4, 7), | |
963 | IMX_GPIO_NR(4, 15), | |
964 | }, | |
965 | .pcie_rst = IMX_GPIO_NR(1, 0), | |
966 | .mezz_pwren = IMX_GPIO_NR(2, 19), | |
967 | .mezz_irq = IMX_GPIO_NR(2, 18), | |
968 | .otgpwr_en = IMX_GPIO_NR(3, 22), | |
385575bc | 969 | }, |
e56c5791 TH |
970 | }; |
971 | ||
972 | void setup_iomux_gpio(int board, struct ventana_board_info *info) | |
973 | { | |
974 | int i; | |
975 | ||
e56c5791 TH |
976 | if (board >= GW_UNKNOWN) |
977 | return; | |
978 | ||
979 | /* board specific iomux */ | |
980 | imx_iomux_v3_setup_multiple_pads(gpio_cfg[board].gpio_pads, | |
981 | gpio_cfg[board].num_pads); | |
982 | ||
e49621b3 TH |
983 | /* RS232_EN# */ |
984 | if (gpio_cfg[board].rs232_en) { | |
095968f1 | 985 | gpio_request(gpio_cfg[board].rs232_en, "rs232_en#"); |
e49621b3 TH |
986 | gpio_direction_output(gpio_cfg[board].rs232_en, 0); |
987 | } | |
988 | ||
e56c5791 TH |
989 | /* GW522x Uses GPIO3_IO23 for PCIE_RST# */ |
990 | if (board == GW52xx && info->model[4] == '2') | |
991 | gpio_cfg[board].pcie_rst = IMX_GPIO_NR(3, 23); | |
992 | ||
993 | /* assert PCI_RST# */ | |
994 | gpio_request(gpio_cfg[board].pcie_rst, "pci_rst#"); | |
995 | gpio_direction_output(gpio_cfg[board].pcie_rst, 0); | |
996 | ||
997 | /* turn off (active-high) user LED's */ | |
998 | for (i = 0; i < ARRAY_SIZE(gpio_cfg[board].leds); i++) { | |
999 | char name[16]; | |
1000 | if (gpio_cfg[board].leds[i]) { | |
1001 | sprintf(name, "led_user%d", i); | |
1002 | gpio_request(gpio_cfg[board].leds[i], name); | |
1003 | gpio_direction_output(gpio_cfg[board].leds[i], 1); | |
1004 | } | |
1005 | } | |
1006 | ||
5c55572f TH |
1007 | /* MSATA Enable - default to PCI */ |
1008 | if (gpio_cfg[board].msata_en) { | |
1009 | gpio_request(gpio_cfg[board].msata_en, "msata_en"); | |
1010 | gpio_direction_output(gpio_cfg[board].msata_en, 0); | |
1011 | } | |
1012 | ||
e56c5791 TH |
1013 | /* Expansion Mezzanine IO */ |
1014 | if (gpio_cfg[board].mezz_pwren) { | |
1015 | gpio_request(gpio_cfg[board].mezz_pwren, "mezz_pwr"); | |
1016 | gpio_direction_output(gpio_cfg[board].mezz_pwren, 0); | |
1017 | } | |
1018 | if (gpio_cfg[board].mezz_irq) { | |
1019 | gpio_request(gpio_cfg[board].mezz_irq, "mezz_irq#"); | |
1020 | gpio_direction_input(gpio_cfg[board].mezz_irq); | |
1021 | } | |
1022 | ||
1023 | /* RS485 Transmit Enable */ | |
1024 | if (gpio_cfg[board].rs485en) { | |
1025 | gpio_request(gpio_cfg[board].rs485en, "rs485_en"); | |
1026 | gpio_direction_output(gpio_cfg[board].rs485en, 0); | |
1027 | } | |
1028 | ||
1029 | /* GPS_SHDN */ | |
1030 | if (gpio_cfg[board].gps_shdn) { | |
1031 | gpio_request(gpio_cfg[board].gps_shdn, "gps_shdn"); | |
1032 | gpio_direction_output(gpio_cfg[board].gps_shdn, 1); | |
1033 | } | |
1034 | ||
1035 | /* Analog video codec power enable */ | |
1036 | if (gpio_cfg[board].vidin_en) { | |
1037 | gpio_request(gpio_cfg[board].vidin_en, "anavidin_en"); | |
1038 | gpio_direction_output(gpio_cfg[board].vidin_en, 1); | |
1039 | } | |
1040 | ||
1041 | /* DIOI2C_DIS# */ | |
1042 | if (gpio_cfg[board].dioi2c_en) { | |
1043 | gpio_request(gpio_cfg[board].dioi2c_en, "dioi2c_dis#"); | |
1044 | gpio_direction_output(gpio_cfg[board].dioi2c_en, 0); | |
1045 | } | |
1046 | ||
1047 | /* PCICK_SSON: disable spread-spectrum clock */ | |
1048 | if (gpio_cfg[board].pcie_sson) { | |
1049 | gpio_request(gpio_cfg[board].pcie_sson, "pci_sson"); | |
1050 | gpio_direction_output(gpio_cfg[board].pcie_sson, 0); | |
1051 | } | |
1052 | ||
1053 | /* USBOTG mux routing */ | |
1054 | if (gpio_cfg[board].usb_sel) { | |
1055 | gpio_request(gpio_cfg[board].usb_sel, "usb_pcisel"); | |
1056 | gpio_direction_output(gpio_cfg[board].usb_sel, 0); | |
1057 | } | |
1058 | ||
1059 | /* PCISKT_WDIS# (Wireless disable GPIO to miniPCIe sockets) */ | |
1060 | if (gpio_cfg[board].wdis) { | |
1061 | gpio_request(gpio_cfg[board].wdis, "wlan_dis"); | |
1062 | gpio_direction_output(gpio_cfg[board].wdis, 1); | |
1063 | } | |
34b080b7 | 1064 | |
f938500f TH |
1065 | /* OTG power off */ |
1066 | if (gpio_cfg[board].otgpwr_en) { | |
1067 | gpio_request(gpio_cfg[board].otgpwr_en, "usbotg_pwr"); | |
1068 | gpio_direction_output(gpio_cfg[board].otgpwr_en, 0); | |
1069 | } | |
1070 | ||
34b080b7 | 1071 | /* sense vselect pin to see if we support uhs-i */ |
f3a8546b TH |
1072 | if (gpio_cfg[board].vsel_pin) { |
1073 | gpio_request(gpio_cfg[board].vsel_pin, "sd3_vselect"); | |
1074 | gpio_direction_input(gpio_cfg[board].vsel_pin); | |
1075 | gpio_cfg[board].usd_vsel = !gpio_get_value(gpio_cfg[board].vsel_pin); | |
1076 | } | |
8d1a6ff8 TH |
1077 | |
1078 | /* microSD CD */ | |
1079 | if (gpio_cfg[board].mmc_cd) { | |
1080 | gpio_request(gpio_cfg[board].mmc_cd, "sd_cd"); | |
1081 | gpio_direction_input(gpio_cfg[board].mmc_cd); | |
1082 | } | |
1083 | ||
1084 | /* Anything else board specific */ | |
1085 | switch(board) { | |
94a1d6c6 TH |
1086 | case GW560x: |
1087 | gpio_request(IMX_GPIO_NR(4, 26), "12p0_en"); | |
1088 | gpio_direction_output(IMX_GPIO_NR(4, 26), 1); | |
1089 | break; | |
8d1a6ff8 TH |
1090 | case GW5904: |
1091 | gpio_request(IMX_GPIO_NR(5, 11), "skt1_wdis#"); | |
1092 | gpio_direction_output(IMX_GPIO_NR(5, 11), 1); | |
1093 | gpio_request(IMX_GPIO_NR(5, 12), "skt1_rst#"); | |
1094 | gpio_direction_output(IMX_GPIO_NR(5, 12), 1); | |
1095 | gpio_request(IMX_GPIO_NR(5, 13), "skt2_wdis#"); | |
1096 | gpio_direction_output(IMX_GPIO_NR(5, 13), 1); | |
1097 | gpio_request(IMX_GPIO_NR(1, 15), "m2_off#"); | |
1098 | gpio_direction_output(IMX_GPIO_NR(1, 15), 1); | |
1099 | gpio_request(IMX_GPIO_NR(1, 14), "m2_wdis#"); | |
1100 | gpio_direction_output(IMX_GPIO_NR(1, 14), 1); | |
1101 | gpio_request(IMX_GPIO_NR(1, 13), "m2_rst#"); | |
1102 | gpio_direction_output(IMX_GPIO_NR(1, 13), 1); | |
1103 | break; | |
1104 | } | |
e56c5791 TH |
1105 | } |
1106 | ||
1107 | /* setup GPIO pinmux and default configuration per baseboard and env */ | |
1108 | void setup_board_gpio(int board, struct ventana_board_info *info) | |
1109 | { | |
1110 | const char *s; | |
1111 | char arg[10]; | |
1112 | size_t len; | |
1113 | int i; | |
1114 | int quiet = simple_strtol(getenv("quiet"), NULL, 10); | |
1115 | ||
1116 | if (board >= GW_UNKNOWN) | |
1117 | return; | |
1118 | ||
1119 | /* RS232_EN# */ | |
e49621b3 TH |
1120 | if (gpio_cfg[board].rs232_en) { |
1121 | gpio_direction_output(gpio_cfg[board].rs232_en, | |
1122 | (hwconfig("rs232")) ? 0 : 1); | |
1123 | } | |
e56c5791 TH |
1124 | |
1125 | /* MSATA Enable */ | |
5c55572f | 1126 | if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) { |
e56c5791 | 1127 | gpio_direction_output(GP_MSATA_SEL, |
5c55572f | 1128 | (hwconfig("msata")) ? 1 : 0); |
e56c5791 TH |
1129 | } |
1130 | ||
1131 | /* USBOTG Select (PCISKT or FrontPanel) */ | |
1132 | if (gpio_cfg[board].usb_sel) { | |
1133 | gpio_direction_output(gpio_cfg[board].usb_sel, | |
1134 | (hwconfig("usb_pcisel")) ? 1 : 0); | |
1135 | } | |
1136 | ||
1137 | /* | |
1138 | * Configure DIO pinmux/padctl registers | |
1139 | * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions | |
1140 | */ | |
1800ffa8 | 1141 | for (i = 0; i < gpio_cfg[board].dio_num; i++) { |
e56c5791 TH |
1142 | struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i]; |
1143 | iomux_v3_cfg_t ctrl = DIO_PAD_CFG; | |
1144 | unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1; | |
1145 | ||
1146 | if (!cfg->gpio_padmux[0] && !cfg->gpio_padmux[1]) | |
1147 | continue; | |
1148 | sprintf(arg, "dio%d", i); | |
1149 | if (!hwconfig(arg)) | |
1150 | continue; | |
1151 | s = hwconfig_subarg(arg, "padctrl", &len); | |
1152 | if (s) { | |
1153 | ctrl = MUX_PAD_CTRL(simple_strtoul(s, NULL, 16) | |
1154 | & 0x1ffff) | MUX_MODE_SION; | |
1155 | } | |
1156 | if (hwconfig_subarg_cmp(arg, "mode", "gpio")) { | |
1157 | if (!quiet) { | |
1158 | printf("DIO%d: GPIO%d_IO%02d (gpio-%d)\n", i, | |
1159 | (cfg->gpio_param/32)+1, | |
1160 | cfg->gpio_param%32, | |
1161 | cfg->gpio_param); | |
1162 | } | |
1163 | imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] | | |
1164 | ctrl); | |
1165 | gpio_requestf(cfg->gpio_param, "dio%d", i); | |
1166 | gpio_direction_input(cfg->gpio_param); | |
83e00f19 | 1167 | } else if (hwconfig_subarg_cmp(arg, "mode", "pwm") && |
e56c5791 | 1168 | cfg->pwm_padmux) { |
f17a9af8 TH |
1169 | if (!cfg->pwm_param) { |
1170 | printf("DIO%d: Error: pwm config invalid\n", | |
1171 | i); | |
1172 | continue; | |
1173 | } | |
e56c5791 TH |
1174 | if (!quiet) |
1175 | printf("DIO%d: pwm%d\n", i, cfg->pwm_param); | |
1176 | imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] | | |
1177 | MUX_PAD_CTRL(ctrl)); | |
1178 | } | |
1179 | } | |
1180 | ||
1181 | if (!quiet) { | |
5c55572f | 1182 | if (gpio_cfg[board].msata_en && is_cpu_type(MXC_CPU_MX6Q)) { |
e56c5791 TH |
1183 | printf("MSATA: %s\n", (hwconfig("msata") ? |
1184 | "enabled" : "disabled")); | |
1185 | } | |
e49621b3 TH |
1186 | if (gpio_cfg[board].rs232_en) { |
1187 | printf("RS232: %s\n", (hwconfig("rs232")) ? | |
1188 | "enabled" : "disabled"); | |
1189 | } | |
e56c5791 TH |
1190 | } |
1191 | } | |
1192 | ||
1193 | /* setup board specific PMIC */ | |
6d38f3a8 | 1194 | void setup_pmic(void) |
e56c5791 TH |
1195 | { |
1196 | struct pmic *p; | |
94a1d6c6 TH |
1197 | struct ventana_board_info ventana_info; |
1198 | int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info); | |
e56c5791 TH |
1199 | u32 reg; |
1200 | ||
6d38f3a8 TH |
1201 | i2c_set_bus_num(CONFIG_I2C_PMIC); |
1202 | ||
e56c5791 | 1203 | /* configure PFUZE100 PMIC */ |
6d38f3a8 TH |
1204 | if (!i2c_probe(CONFIG_POWER_PFUZE100_I2C_ADDR)) { |
1205 | debug("probed PFUZE100@0x%x\n", CONFIG_POWER_PFUZE100_I2C_ADDR); | |
e56c5791 TH |
1206 | power_pfuze100_init(CONFIG_I2C_PMIC); |
1207 | p = pmic_get("PFUZE100"); | |
1208 | if (p && !pmic_probe(p)) { | |
1209 | pmic_reg_read(p, PFUZE100_DEVICEID, ®); | |
1210 | printf("PMIC: PFUZE100 ID=0x%02x\n", reg); | |
1211 | ||
1212 | /* Set VGEN1 to 1.5V and enable */ | |
1213 | pmic_reg_read(p, PFUZE100_VGEN1VOL, ®); | |
1214 | reg &= ~(LDO_VOL_MASK); | |
1215 | reg |= (LDOA_1_50V | LDO_EN); | |
1216 | pmic_reg_write(p, PFUZE100_VGEN1VOL, reg); | |
1217 | ||
1218 | /* Set SWBST to 5.0V and enable */ | |
1219 | pmic_reg_read(p, PFUZE100_SWBSTCON1, ®); | |
1220 | reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK); | |
18e02ffe | 1221 | reg |= (SWBST_5_00V | (SWBST_MODE_AUTO << SWBST_MODE_SHIFT)); |
e56c5791 TH |
1222 | pmic_reg_write(p, PFUZE100_SWBSTCON1, reg); |
1223 | } | |
1224 | } | |
1225 | ||
1226 | /* configure LTC3676 PMIC */ | |
6d38f3a8 TH |
1227 | else if (!i2c_probe(CONFIG_POWER_LTC3676_I2C_ADDR)) { |
1228 | debug("probed LTC3676@0x%x\n", CONFIG_POWER_LTC3676_I2C_ADDR); | |
e56c5791 TH |
1229 | power_ltc3676_init(CONFIG_I2C_PMIC); |
1230 | p = pmic_get("LTC3676_PMIC"); | |
94a1d6c6 TH |
1231 | if (!p || pmic_probe(p)) |
1232 | return; | |
1233 | puts("PMIC: LTC3676\n"); | |
1234 | /* | |
1235 | * set board-specific scalar for max CPU frequency | |
1236 | * per CPU based on the LDO enabled Operating Ranges | |
1237 | * defined in the respective IMX6DQ and IMX6SDL | |
1238 | * datasheets. The voltage resulting from the R1/R2 | |
1239 | * feedback inputs on Ventana is 1308mV. Note that this | |
1240 | * is a bit shy of the Vmin of 1350mV in the datasheet | |
1241 | * for LDO enabled mode but is as high as we can go. | |
1242 | */ | |
1243 | switch (board) { | |
1244 | case GW560x: | |
1245 | /* mask PGOOD during SW3 transition */ | |
1246 | pmic_reg_write(p, LTC3676_DVB3B, | |
1247 | 0x1f | LTC3676_PGOOD_MASK); | |
1248 | /* set SW3 (VDD_ARM) */ | |
1249 | pmic_reg_write(p, LTC3676_DVB3A, 0x1f); | |
1250 | break; | |
1251 | default: | |
e56c5791 TH |
1252 | /* mask PGOOD during SW1 transition */ |
1253 | pmic_reg_write(p, LTC3676_DVB1B, | |
1254 | 0x1f | LTC3676_PGOOD_MASK); | |
1255 | /* set SW1 (VDD_SOC) */ | |
1256 | pmic_reg_write(p, LTC3676_DVB1A, 0x1f); | |
1257 | ||
1258 | /* mask PGOOD during SW3 transition */ | |
1259 | pmic_reg_write(p, LTC3676_DVB3B, | |
1260 | 0x1f | LTC3676_PGOOD_MASK); | |
1261 | /* set SW3 (VDD_ARM) */ | |
1262 | pmic_reg_write(p, LTC3676_DVB3A, 0x1f); | |
1263 | } | |
1264 | } | |
1265 | } | |
65da5c3b TH |
1266 | |
1267 | #ifdef CONFIG_FSL_ESDHC | |
94a1d6c6 | 1268 | static struct fsl_esdhc_cfg usdhc_cfg[2]; |
65da5c3b TH |
1269 | |
1270 | int board_mmc_init(bd_t *bis) | |
1271 | { | |
8d1a6ff8 TH |
1272 | struct ventana_board_info ventana_info; |
1273 | int board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info); | |
1274 | int ret; | |
1275 | ||
1276 | switch (board_type) { | |
1277 | case GW52xx: | |
1278 | case GW53xx: | |
1279 | case GW54xx: | |
1280 | case GW553x: | |
1281 | /* usdhc3: 4bit microSD */ | |
1282 | SETUP_IOMUX_PADS(usdhc3_pads); | |
94a1d6c6 TH |
1283 | usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; |
1284 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | |
1285 | usdhc_cfg[0].max_bus_width = 4; | |
1286 | return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); | |
1287 | case GW560x: | |
1288 | /* usdhc2: 8-bit eMMC */ | |
1289 | SETUP_IOMUX_PADS(gw560x_emmc_sd2_pads); | |
1290 | usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; | |
1291 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); | |
1292 | usdhc_cfg[0].max_bus_width = 8; | |
1293 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[0]); | |
1294 | if (ret) | |
1295 | return ret; | |
1296 | /* usdhc3: 4-bit microSD */ | |
1297 | SETUP_IOMUX_PADS(usdhc3_pads); | |
1298 | usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; | |
1299 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | |
1300 | usdhc_cfg[1].max_bus_width = 4; | |
1301 | return fsl_esdhc_initialize(bis, &usdhc_cfg[1]); | |
8d1a6ff8 TH |
1302 | case GW5904: |
1303 | /* usdhc3: 8bit eMMC */ | |
1304 | SETUP_IOMUX_PADS(gw5904_emmc_pads); | |
94a1d6c6 TH |
1305 | usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; |
1306 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | |
1307 | usdhc_cfg[0].max_bus_width = 8; | |
1308 | return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); | |
8d1a6ff8 TH |
1309 | default: |
1310 | /* doesn't have MMC */ | |
1311 | return -1; | |
1312 | } | |
65da5c3b TH |
1313 | } |
1314 | ||
1315 | int board_mmc_getcd(struct mmc *mmc) | |
1316 | { | |
8d1a6ff8 TH |
1317 | struct ventana_board_info ventana_info; |
1318 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | |
1319 | int board = read_eeprom(CONFIG_I2C_GSC, &ventana_info); | |
1320 | int gpio = gpio_cfg[board].mmc_cd; | |
1321 | ||
65da5c3b | 1322 | /* Card Detect */ |
8d1a6ff8 | 1323 | switch (board) { |
94a1d6c6 TH |
1324 | case GW560x: |
1325 | /* emmc is always present */ | |
1326 | if (cfg->esdhc_base == USDHC2_BASE_ADDR) | |
1327 | return 1; | |
1328 | break; | |
8d1a6ff8 TH |
1329 | case GW5904: |
1330 | /* emmc is always present */ | |
1331 | if (cfg->esdhc_base == USDHC3_BASE_ADDR) | |
1332 | return 1; | |
1333 | break; | |
1334 | } | |
1335 | ||
1336 | if (gpio) { | |
1337 | debug("%s: gpio%d=%d\n", __func__, gpio, gpio_get_value(gpio)); | |
1338 | return !gpio_get_value(gpio); | |
1339 | } | |
1340 | ||
1341 | return -1; | |
65da5c3b | 1342 | } |
8d1a6ff8 | 1343 | |
65da5c3b | 1344 | #endif /* CONFIG_FSL_ESDHC */ |