[thirdparty/u-boot.git] / board / gdsys / common / osd.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2010
 * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
 */

#ifdef CONFIG_GDSYS_LEGACY_DRIVERS

#include <common.h>
#include <command.h>
#include <i2c.h>
#include <malloc.h>
#include <linux/stringify.h>

#include "ch7301.h"
#include "dp501.h"
#include <gdsys_fpga.h>

#define ICS8N3QV01_I2C_ADDR 0x6E
#define ICS8N3QV01_FREF 114285000
#define ICS8N3QV01_FREF_LL 114285000LL
#define ICS8N3QV01_F_DEFAULT_0 156250000LL
#define ICS8N3QV01_F_DEFAULT_1 125000000LL
#define ICS8N3QV01_F_DEFAULT_2 100000000LL
#define ICS8N3QV01_F_DEFAULT_3  25175000LL

#define SIL1178_MASTER_I2C_ADDRESS 0x38
#define SIL1178_SLAVE_I2C_ADDRESS 0x39

#define PIXCLK_640_480_60 25180000
#define MAX_X_CHARS 53
#define MAX_Y_CHARS 26

#ifdef CONFIG_SYS_OSD_DH
#define MAX_OSD_SCREEN 8
#define OSD_DH_BASE 4
#else
#define MAX_OSD_SCREEN 4
#endif

#ifdef CONFIG_SYS_OSD_DH
#define OSD_SET_REG(screen, fld, val) \
	do { \
		if (screen >= OSD_DH_BASE) \
			FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
		else \
			FPGA_SET_REG(screen, osd0.fld, val); \
	} while (0)
#else
#define OSD_SET_REG(screen, fld, val) \
		FPGA_SET_REG(screen, osd0.fld, val)
#endif

#ifdef CONFIG_SYS_OSD_DH
#define OSD_GET_REG(screen, fld, val) \
	do {					\
		if (screen >= OSD_DH_BASE) \
			FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
		else \
			FPGA_GET_REG(screen, osd0.fld, val); \
	} while (0)
#else
#define OSD_GET_REG(screen, fld, val) \
		FPGA_GET_REG(screen, osd0.fld, val)
#endif

unsigned int base_width;
unsigned int base_height;
size_t bufsize;
u16 *buf;

unsigned int osd_screen_mask = 0;

#ifdef CONFIG_SYS_ICS8N3QV01_I2C
int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
#endif

#ifdef CONFIG_SYS_SIL1178_I2C
int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
#endif

#ifdef CONFIG_SYS_MPC92469AC
static void mpc92469ac_calc_parameters(unsigned int fout,
	unsigned int *post_div, unsigned int *feedback_div)
{
	unsigned int n = *post_div;
	unsigned int m = *feedback_div;
	unsigned int a;
	unsigned int b = 14745600 / 16;

	if (fout < 50169600)
		n = 8;
	else if (fout < 100339199)
		n = 4;
	else if (fout < 200678399)
		n = 2;
	else
		n = 1;

	a = fout * n + (b / 2); /* add b/2 for proper rounding */

	m = a / b;

	*post_div = n;
	*feedback_div = m;
}

static void mpc92469ac_set(unsigned screen, unsigned int fout)
{
	unsigned int n;
	unsigned int m;
	unsigned int bitval = 0;
	mpc92469ac_calc_parameters(fout, &n, &m);

	switch (n) {
	case 1:
		bitval = 0x00;
		break;
	case 2:
		bitval = 0x01;
		break;
	case 4:
		bitval = 0x02;
		break;
	case 8:
		bitval = 0x03;
		break;
	}

	FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) | m);
}
#endif

#ifdef CONFIG_SYS_ICS8N3QV01_I2C

static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
{
	unsigned long long n;
	unsigned long long mint;
	unsigned long long mfrac;
	u8 reg_a, reg_b, reg_c, reg_d, reg_f;
	unsigned long long fout_calc;

	if (index > 3)
		return 0;

	reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index);
	reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index);
	reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index);
	reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index);
	reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index);

	mint = ((reg_a >> 1) & 0x1f) | (reg_f & 0x20);
	mfrac = ((reg_a & 0x01) << 17) | (reg_b << 9) | (reg_c << 1)
		| (reg_d >> 7);
	n = reg_d & 0x7f;

	fout_calc = (mint * ICS8N3QV01_FREF_LL
		     + mfrac * ICS8N3QV01_FREF_LL / 262144LL
		     + ICS8N3QV01_FREF_LL / 524288LL
		     + n / 2)
		    / n
		    * 1000000
		    / (1000000 - 100);

	return fout_calc;
}


static void ics8n3qv01_calc_parameters(unsigned int fout,
	unsigned int *_mint, unsigned int *_mfrac,
	unsigned int *_n)
{
	unsigned int n;
	unsigned int foutiic;
	unsigned int fvcoiic;
	unsigned int mint;
	unsigned long long mfrac;

	n = (2215000000U + fout / 2) / fout;
	if ((n & 1) && (n > 5))
		n -= 1;

	foutiic = fout - (fout / 10000);
	fvcoiic = foutiic * n;

	mint = fvcoiic / 114285000;
	if ((mint < 17) || (mint > 63))
		printf("ics8n3qv01_calc_parameters: cannot determine mint\n");

	mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
		/ 114285000LL;

	*_mint = mint;
	*_mfrac = mfrac;
	*_n = n;
}

static void ics8n3qv01_set(unsigned int fout)
{
	unsigned int n;
	unsigned int mint;
	unsigned int mfrac;
	unsigned int fout_calc;
	unsigned long long fout_prog;
	long long off_ppm;
	u8 reg0, reg4, reg8, reg12, reg18, reg20;

	fout_calc = ics8n3qv01_get_fout_calc(1);
	off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
		  / ICS8N3QV01_F_DEFAULT_1;
	printf("       PLL is off by %lld ppm\n", off_ppm);
	fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
		    / ICS8N3QV01_F_DEFAULT_1;
	ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);

	reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
	reg0 |= (mint & 0x1f) << 1;
	reg0 |= (mfrac >> 17) & 0x01;
	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0);

	reg4 = mfrac >> 9;
	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4);

	reg8 = mfrac >> 1;
	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8);

	reg12 = mfrac << 7;
	reg12 |= n & 0x7f;
	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12);

	reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03;
	reg18 |= 0x20;
	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18);

	reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
	reg20 |= mint & (1 << 5);
	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20);
}
#endif

static int osd_write_videomem(unsigned screen, unsigned offset,
	u16 *data, size_t charcount)
{
	unsigned int k;

	for (k = 0; k < charcount; ++k) {
		if (offset + k >= bufsize)
			return -1;
#ifdef CONFIG_SYS_OSD_DH
		if (screen >= OSD_DH_BASE)
			FPGA_SET_REG(screen - OSD_DH_BASE,
				     videomem1[offset + k], data[k]);
		else
			FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
#else
		FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
#endif
	}

	return charcount;
}

static int osd_print(struct cmd_tbl *cmdtp, int flag, int argc,
		     char *const argv[])
{
	unsigned screen;

	if (argc < 5) {
		cmd_usage(cmdtp);
		return 1;
	}

	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
		unsigned x;
		unsigned y;
		unsigned charcount;
		unsigned len;
		u8 color;
		unsigned int k;
		char *text;
		int res;

		if (!(osd_screen_mask & (1 << screen)))
			continue;

		x = hextoul(argv[1], NULL);
		y = hextoul(argv[2], NULL);
		color = hextoul(argv[3], NULL);
		text = argv[4];
		charcount = strlen(text);
		len = (charcount > bufsize) ? bufsize : charcount;

		for (k = 0; k < len; ++k)
			buf[k] = (text[k] << 8) | color;

		res = osd_write_videomem(screen, y * base_width + x, buf, len);
		if (res < 0)
			return res;

		OSD_SET_REG(screen, control, 0x0049);
	}

	return 0;
}

int osd_probe(unsigned screen)
{
	u16 version;
	u16 features;
	int old_bus = i2c_get_bus_num();
	bool pixclock_present = false;
	bool output_driver_present = false;

	OSD_GET_REG(0, version, &version);
	OSD_GET_REG(0, features, &features);

	base_width = ((features & 0x3f00) >> 8) + 1;
	base_height = (features & 0x001f) + 1;
	bufsize = base_width * base_height;
	buf = malloc(sizeof(u16) * bufsize);
	if (!buf)
		return -1;

#ifdef CONFIG_SYS_OSD_DH
	printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
	       (screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen,
	       (screen > 3) ? 1 : 0, version/100, version%100, base_width,
	       base_height);
#else
	printf("OSD%d:  Digital-OSD version %01d.%02d, %d" "x%d characters\n",
	       screen, version/100, version%100, base_width, base_height);
#endif
	/* setup pixclock */

#ifdef CONFIG_SYS_MPC92469AC
	pixclock_present = true;
	mpc92469ac_set(screen, PIXCLK_640_480_60);
#endif

#ifdef CONFIG_SYS_ICS8N3QV01_I2C
	i2c_set_bus_num(ics8n3qv01_i2c[screen]);
	if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
		ics8n3qv01_set(PIXCLK_640_480_60);
		pixclock_present = true;
	}
#endif

	if (!pixclock_present)
		printf("       no pixelclock found\n");

	/* setup output driver */

#ifdef CONFIG_SYS_CH7301_I2C
	if (!ch7301_probe(screen, true))
		output_driver_present = true;
#endif

#ifdef CONFIG_SYS_SIL1178_I2C
	i2c_set_bus_num(sil1178_i2c[screen]);
	if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
		if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) {
			/*
			 * magic initialization sequence,
			 * adapted from datasheet
			 */
			i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
			i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
			output_driver_present = true;
		}
	}
#endif

#ifdef CONFIG_SYS_DP501_I2C
	if (!dp501_probe(screen, true))
		output_driver_present = true;
#endif

	if (!output_driver_present)
		printf("       no output driver found\n");

	OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) | (16 - 1));
	OSD_SET_REG(screen, x_pos, 0x007f);
	OSD_SET_REG(screen, y_pos, 0x005f);

	if (pixclock_present && output_driver_present)
		osd_screen_mask |= 1 << screen;

	i2c_set_bus_num(old_bus);

	return 0;
}

int osd_write(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	unsigned screen;

	if ((argc < 4) || (strlen(argv[3]) % 4)) {
		cmd_usage(cmdtp);
		return 1;
	}

	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
		unsigned x;
		unsigned y;
		unsigned k;
		u16 buffer[base_width];
		char *rp;
		u16 *wp = buffer;
		unsigned count = (argc > 4) ?
			hextoul(argv[4], NULL) : 1;

		if (!(osd_screen_mask & (1 << screen)))
			continue;

		x = hextoul(argv[1], NULL);
		y = hextoul(argv[2], NULL);
		rp = argv[3];


		while (*rp) {
			char substr[5];

			memcpy(substr, rp, 4);
			substr[4] = 0;
			*wp = hextoul(substr, NULL);

			rp += 4;
			wp++;
			if (wp - buffer > base_width)
				break;
		}

		for (k = 0; k < count; ++k) {
			unsigned offset =
				y * base_width + x + k * (wp - buffer);
			osd_write_videomem(screen, offset, buffer,
				wp - buffer);
		}

		OSD_SET_REG(screen, control, 0x0049);
	}

	return 0;
}

int osd_size(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
	unsigned screen;
	unsigned x;
	unsigned y;

	if (argc < 3) {
		cmd_usage(cmdtp);
		return 1;
	}

	x = hextoul(argv[1], NULL);
	y = hextoul(argv[2], NULL);

	if (!x || (x > 64) || (x > MAX_X_CHARS) ||
	    !y || (y > 32) || (y > MAX_Y_CHARS)) {
		cmd_usage(cmdtp);
		return 1;
	}

	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
		if (!(osd_screen_mask & (1 << screen)))
			continue;

		OSD_SET_REG(screen, xy_size, ((x - 1) << 8) | (y - 1));
		OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535);
		OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535);
	}

	return 0;
}

U_BOOT_CMD(
	osdw, 5, 0, osd_write,
	"write 16-bit hex encoded buffer to osd memory",
	"pos_x pos_y buffer count\n"
);

U_BOOT_CMD(
	osdp, 5, 0, osd_print,
	"write ASCII buffer to osd memory",
	"pos_x pos_y color text\n"
);

U_BOOT_CMD(
	osdsize, 3, 0, osd_size,
	"set OSD XY size in characters",
	"size_x(max. " __stringify(MAX_X_CHARS)
	") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"
);

#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
a605ea7e DE	2	/*
a605ea7e DE	3	* (C) Copyright 2010
d38826a3	4	* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
a605ea7e DE	5	*/
a605ea7e DE	6
fe4a9675 MS	7	#ifdef CONFIG_GDSYS_LEGACY_DRIVERS
fe4a9675 MS	8
d678a59d	9	#include <common.h>
09140113	10	#include <command.h>
aba27acf	11	#include <i2c.h>
e50e8968	12	#include <malloc.h>
1af3c7f4	13	#include <linux/stringify.h>
a605ea7e	14
a3f9d6c7	15	#include "ch7301.h"
3a990bfa	16	#include "dp501.h"
2da0fc0d	17	#include <gdsys_fpga.h>
a605ea7e	18
2da0fc0d	19	#define ICS8N3QV01_I2C_ADDR 0x6E
6853cc4b DE	20	#define ICS8N3QV01_FREF 114285000
	21	#define ICS8N3QV01_FREF_LL 114285000LL
	22	#define ICS8N3QV01_F_DEFAULT_0 156250000LL
	23	#define ICS8N3QV01_F_DEFAULT_1 125000000LL
	24	#define ICS8N3QV01_F_DEFAULT_2 100000000LL
	25	#define ICS8N3QV01_F_DEFAULT_3 25175000LL
2da0fc0d DE	26
	27	#define SIL1178_MASTER_I2C_ADDRESS 0x38
	28	#define SIL1178_SLAVE_I2C_ADDRESS 0x39
	29
a605ea7e	30	#define PIXCLK_640_480_60 25180000
da4833c7 DE	31	#define MAX_X_CHARS 53
da4833c7 DE	32	#define MAX_Y_CHARS 26
a605ea7e	33
7ed45d3d DE	34	#ifdef CONFIG_SYS_OSD_DH
	35	#define MAX_OSD_SCREEN 8
	36	#define OSD_DH_BASE 4
	37	#else
	38	#define MAX_OSD_SCREEN 4
	39	#endif
	40
	41	#ifdef CONFIG_SYS_OSD_DH
	42	#define OSD_SET_REG(screen, fld, val) \
	43	do { \
	44	if (screen >= OSD_DH_BASE) \
	45	FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
	46	else \
	47	FPGA_SET_REG(screen, osd0.fld, val); \
	48	} while (0)
	49	#else
	50	#define OSD_SET_REG(screen, fld, val) \
	51	FPGA_SET_REG(screen, osd0.fld, val)
	52	#endif
	53
	54	#ifdef CONFIG_SYS_OSD_DH
	55	#define OSD_GET_REG(screen, fld, val) \
	56	do { \
	57	if (screen >= OSD_DH_BASE) \
	58	FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
	59	else \
	60	FPGA_GET_REG(screen, osd0.fld, val); \
	61	} while (0)
	62	#else
	63	#define OSD_GET_REG(screen, fld, val) \
	64	FPGA_GET_REG(screen, osd0.fld, val)
	65	#endif
	66
0f0c1021 DE	67	unsigned int base_width;
	68	unsigned int base_height;
	69	size_t bufsize;
	70	u16 *buf;
	71
7ed45d3d	72	unsigned int osd_screen_mask = 0;
e50e8968	73
3a990bfa DE	74	#ifdef CONFIG_SYS_ICS8N3QV01_I2C
3a990bfa DE	75	int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
e50e8968 DE	76	#endif
e50e8968 DE	77
3a990bfa	78	#ifdef CONFIG_SYS_SIL1178_I2C
edfe9fea	79	int sil1178_i2c[] = CONFIG_SYS_SIL1178_I2C;
2da0fc0d DE	80	#endif
	81
	82	#ifdef CONFIG_SYS_MPC92469AC
a605ea7e DE	83	static void mpc92469ac_calc_parameters(unsigned int fout,
	84	unsigned int post_div, unsigned int feedback_div)
	85	{
	86	unsigned int n = *post_div;
	87	unsigned int m = *feedback_div;
	88	unsigned int a;
	89	unsigned int b = 14745600 / 16;
	90
	91	if (fout < 50169600)
	92	n = 8;
	93	else if (fout < 100339199)
	94	n = 4;
	95	else if (fout < 200678399)
	96	n = 2;
	97	else
	98	n = 1;
	99
	100	a = fout * n + (b / 2); /* add b/2 for proper rounding */
	101
	102	m = a / b;
	103
	104	*post_div = n;
	105	*feedback_div = m;
	106	}
	107
2da0fc0d	108	static void mpc92469ac_set(unsigned screen, unsigned int fout)
a605ea7e DE	109	{
	110	unsigned int n;
	111	unsigned int m;
	112	unsigned int bitval = 0;
	113	mpc92469ac_calc_parameters(fout, &n, &m);
	114
	115	switch (n) {
	116	case 1:
	117	bitval = 0x00;
	118	break;
	119	case 2:
	120	bitval = 0x01;
	121	break;
	122	case 4:
	123	bitval = 0x02;
	124	break;
	125	case 8:
	126	bitval = 0x03;
	127	break;
	128	}
	129
aba27acf	130	FPGA_SET_REG(screen, mpc3w_control, (bitval << 9) \| m);
a605ea7e	131	}
2da0fc0d	132	#endif
a605ea7e	133
3a990bfa	134	#ifdef CONFIG_SYS_ICS8N3QV01_I2C
6853cc4b	135
edfe9fea	136	static unsigned int ics8n3qv01_get_fout_calc(unsigned index)
6853cc4b DE	137	{
	138	unsigned long long n;
	139	unsigned long long mint;
	140	unsigned long long mfrac;
	141	u8 reg_a, reg_b, reg_c, reg_d, reg_f;
	142	unsigned long long fout_calc;
	143
	144	if (index > 3)
	145	return 0;
	146
edfe9fea DE	147	reg_a = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0 + index);
	148	reg_b = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 4 + index);
	149	reg_c = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 8 + index);
	150	reg_d = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 12 + index);
	151	reg_f = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20 + index);
6853cc4b DE	152
	153	mint = ((reg_a >> 1) & 0x1f) \| (reg_f & 0x20);
	154	mfrac = ((reg_a & 0x01) << 17) \| (reg_b << 9) \| (reg_c << 1)
	155	\| (reg_d >> 7);
	156	n = reg_d & 0x7f;
	157
	158	fout_calc = (mint * ICS8N3QV01_FREF_LL
	159	+ mfrac * ICS8N3QV01_FREF_LL / 262144LL
	160	+ ICS8N3QV01_FREF_LL / 524288LL
	161	+ n / 2)
	162	/ n
	163	* 1000000
	164	/ (1000000 - 100);
	165
	166	return fout_calc;
	167	}
	168
	169
2da0fc0d DE	170	static void ics8n3qv01_calc_parameters(unsigned int fout,
	171	unsigned int _mint, unsigned int _mfrac,
	172	unsigned int *_n)
a605ea7e	173	{
2da0fc0d DE	174	unsigned int n;
	175	unsigned int foutiic;
	176	unsigned int fvcoiic;
	177	unsigned int mint;
	178	unsigned long long mfrac;
	179
6853cc4b	180	n = (2215000000U + fout / 2) / fout;
2da0fc0d DE	181	if ((n & 1) && (n > 5))
	182	n -= 1;
	183
	184	foutiic = fout - (fout / 10000);
	185	fvcoiic = foutiic * n;
	186
	187	mint = fvcoiic / 114285000;
	188	if ((mint < 17) \|\| (mint > 63))
	189	printf("ics8n3qv01_calc_parameters: cannot determine mint\n");
	190
	191	mfrac = ((unsigned long long)fvcoiic % 114285000LL) * 262144LL
	192	/ 114285000LL;
	193
	194	*_mint = mint;
	195	*_mfrac = mfrac;
	196	*_n = n;
	197	}
	198
edfe9fea	199	static void ics8n3qv01_set(unsigned int fout)
2da0fc0d DE	200	{
	201	unsigned int n;
	202	unsigned int mint;
	203	unsigned int mfrac;
6853cc4b DE	204	unsigned int fout_calc;
	205	unsigned long long fout_prog;
	206	long long off_ppm;
2da0fc0d DE	207	u8 reg0, reg4, reg8, reg12, reg18, reg20;
2da0fc0d DE	208
edfe9fea	209	fout_calc = ics8n3qv01_get_fout_calc(1);
6853cc4b DE	210	off_ppm = (fout_calc - ICS8N3QV01_F_DEFAULT_1) * 1000000
	211	/ ICS8N3QV01_F_DEFAULT_1;
	212	printf(" PLL is off by %lld ppm\n", off_ppm);
	213	fout_prog = (unsigned long long)fout * (unsigned long long)fout_calc
	214	/ ICS8N3QV01_F_DEFAULT_1;
	215	ics8n3qv01_calc_parameters(fout_prog, &mint, &mfrac, &n);
2da0fc0d	216
edfe9fea	217	reg0 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 0) & 0xc0;
2da0fc0d DE	218	reg0 \|= (mint & 0x1f) << 1;
2da0fc0d DE	219	reg0 \|= (mfrac >> 17) & 0x01;
edfe9fea	220	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 0, reg0);
2da0fc0d DE	221
2da0fc0d DE	222	reg4 = mfrac >> 9;
edfe9fea	223	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 4, reg4);
2da0fc0d DE	224
2da0fc0d DE	225	reg8 = mfrac >> 1;
edfe9fea	226	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 8, reg8);
2da0fc0d DE	227
	228	reg12 = mfrac << 7;
	229	reg12 \|= n & 0x7f;
edfe9fea	230	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 12, reg12);
2da0fc0d	231
edfe9fea	232	reg18 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 18) & 0x03;
2da0fc0d	233	reg18 \|= 0x20;
edfe9fea	234	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 18, reg18);
2da0fc0d	235
edfe9fea	236	reg20 = i2c_reg_read(ICS8N3QV01_I2C_ADDR, 20) & 0x1f;
2da0fc0d	237	reg20 \|= mint & (1 << 5);
edfe9fea	238	i2c_reg_write(ICS8N3QV01_I2C_ADDR, 20, reg20);
2da0fc0d DE	239	}
	240	#endif
	241
	242	static int osd_write_videomem(unsigned screen, unsigned offset,
	243	u16 *data, size_t charcount)
	244	{
a605ea7e DE	245	unsigned int k;
	246
	247	for (k = 0; k < charcount; ++k) {
0f0c1021	248	if (offset + k >= bufsize)
a605ea7e	249	return -1;
7ed45d3d DE	250	#ifdef CONFIG_SYS_OSD_DH
	251	if (screen >= OSD_DH_BASE)
	252	FPGA_SET_REG(screen - OSD_DH_BASE,
	253	videomem1[offset + k], data[k]);
	254	else
	255	FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
	256	#else
	257	FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
	258	#endif
a605ea7e DE	259	}
	260
	261	return charcount;
	262	}
	263
09140113 SG	264	static int osd_print(struct cmd_tbl *cmdtp, int flag, int argc,
09140113 SG	265	char *const argv[])
a605ea7e	266	{
2da0fc0d DE	267	unsigned screen;
2da0fc0d DE	268
7ed45d3d DE	269	if (argc < 5) {
	270	cmd_usage(cmdtp);
	271	return 1;
	272	}
	273
	274	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
2da0fc0d DE	275	unsigned x;
	276	unsigned y;
	277	unsigned charcount;
	278	unsigned len;
	279	u8 color;
	280	unsigned int k;
2da0fc0d DE	281	char *text;
	282	int res;
	283
7ed45d3d DE	284	if (!(osd_screen_mask & (1 << screen)))
7ed45d3d DE	285	continue;
2da0fc0d	286
7e5f460e SG	287	x = hextoul(argv[1], NULL);
	288	y = hextoul(argv[2], NULL);
	289	color = hextoul(argv[3], NULL);
2da0fc0d DE	290	text = argv[4];
2da0fc0d DE	291	charcount = strlen(text);
0f0c1021	292	len = (charcount > bufsize) ? bufsize : charcount;
2da0fc0d DE	293
	294	for (k = 0; k < len; ++k)
	295	buf[k] = (text[k] << 8) \| color;
	296
0f0c1021	297	res = osd_write_videomem(screen, y * base_width + x, buf, len);
2da0fc0d DE	298	if (res < 0)
2da0fc0d DE	299	return res;
acff73fd DE	300
acff73fd DE	301	OSD_SET_REG(screen, control, 0x0049);
a605ea7e DE	302	}
a605ea7e DE	303
2da0fc0d	304	return 0;
a605ea7e DE	305	}
a605ea7e DE	306
2da0fc0d	307	int osd_probe(unsigned screen)
a605ea7e	308	{
aba27acf DE	309	u16 version;
aba27acf DE	310	u16 features;
e50e8968	311	int old_bus = i2c_get_bus_num();
3a990bfa DE	312	bool pixclock_present = false;
3a990bfa DE	313	bool output_driver_present = false;
a605ea7e	314
7ed45d3d DE	315	OSD_GET_REG(0, version, &version);
7ed45d3d DE	316	OSD_GET_REG(0, features, &features);
aba27acf	317
0f0c1021 DE	318	base_width = ((features & 0x3f00) >> 8) + 1;
	319	base_height = (features & 0x001f) + 1;
	320	bufsize = base_width * base_height;
	321	buf = malloc(sizeof(u16) * bufsize);
	322	if (!buf)
	323	return -1;
a605ea7e	324
7ed45d3d DE	325	#ifdef CONFIG_SYS_OSD_DH
	326	printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
	327	(screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen,
	328	(screen > 3) ? 1 : 0, version/100, version%100, base_width,
	329	base_height);
	330	#else
2da0fc0d	331	printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
7ed45d3d DE	332	screen, version/100, version%100, base_width, base_height);
7ed45d3d DE	333	#endif
3a990bfa	334	/* setup pixclock */
2da0fc0d DE	335
2da0fc0d DE	336	#ifdef CONFIG_SYS_MPC92469AC
3a990bfa	337	pixclock_present = true;
2da0fc0d DE	338	mpc92469ac_set(screen, PIXCLK_640_480_60);
2da0fc0d DE	339	#endif
a605ea7e	340
3a990bfa	341	#ifdef CONFIG_SYS_ICS8N3QV01_I2C
edfe9fea	342	i2c_set_bus_num(ics8n3qv01_i2c[screen]);
3a990bfa DE	343	if (!i2c_probe(ICS8N3QV01_I2C_ADDR)) {
	344	ics8n3qv01_set(PIXCLK_640_480_60);
	345	pixclock_present = true;
	346	}
2da0fc0d	347	#endif
a605ea7e	348
3a990bfa DE	349	if (!pixclock_present)
	350	printf(" no pixelclock found\n");
	351
	352	/* setup output driver */
	353
	354	#ifdef CONFIG_SYS_CH7301_I2C
a3f9d6c7 DE	355	if (!ch7301_probe(screen, true))
a3f9d6c7 DE	356	output_driver_present = true;
3a990bfa DE	357	#endif
	358
	359	#ifdef CONFIG_SYS_SIL1178_I2C
edfe9fea	360	i2c_set_bus_num(sil1178_i2c[screen]);
3a990bfa	361	if (!i2c_probe(SIL1178_SLAVE_I2C_ADDRESS)) {
a61762d2	362	if (i2c_reg_read(SIL1178_SLAVE_I2C_ADDRESS, 0x02) == 0x06) {
3a990bfa DE	363	/*
	364	* magic initialization sequence,
	365	* adapted from datasheet
	366	*/
	367	i2c_reg_write(SIL1178_SLAVE_I2C_ADDRESS, 0x08, 0x36);
	368	i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x44);
	369	i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0f, 0x4c);
	370	i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0e, 0x10);
	371	i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0a, 0x80);
	372	i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x09, 0x30);
	373	i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0c, 0x89);
	374	i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x0d, 0x60);
	375	i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x36);
	376	i2c_reg_write(SIL1178_MASTER_I2C_ADDRESS, 0x08, 0x37);
	377	output_driver_present = true;
	378	}
	379	}
	380	#endif
	381
	382	#ifdef CONFIG_SYS_DP501_I2C
e9cb21d0	383	if (!dp501_probe(screen, true))
3a990bfa	384	output_driver_present = true;
2da0fc0d DE	385	#endif
2da0fc0d DE	386
3a990bfa DE	387	if (!output_driver_present)
	388	printf(" no output driver found\n");
	389
7ed45d3d DE	390	OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) \| (16 - 1));
	391	OSD_SET_REG(screen, x_pos, 0x007f);
	392	OSD_SET_REG(screen, y_pos, 0x005f);
2da0fc0d	393
7ed45d3d DE	394	if (pixclock_present && output_driver_present)
7ed45d3d DE	395	osd_screen_mask \|= 1 << screen;
a605ea7e	396
edfe9fea DE	397	i2c_set_bus_num(old_bus);
edfe9fea DE	398
a605ea7e DE	399	return 0;
	400	}
	401
09140113	402	int osd_write(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
a605ea7e	403	{
2da0fc0d DE	404	unsigned screen;
2da0fc0d DE	405
7ed45d3d DE	406	if ((argc < 4) \|\| (strlen(argv[3]) % 4)) {
	407	cmd_usage(cmdtp);
	408	return 1;
	409	}
	410
	411	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
2da0fc0d DE	412	unsigned x;
	413	unsigned y;
	414	unsigned k;
0f0c1021	415	u16 buffer[base_width];
2da0fc0d DE	416	char *rp;
	417	u16 *wp = buffer;
	418	unsigned count = (argc > 4) ?
7e5f460e	419	hextoul(argv[4], NULL) : 1;
2da0fc0d	420
7ed45d3d DE	421	if (!(osd_screen_mask & (1 << screen)))
7ed45d3d DE	422	continue;
2da0fc0d	423
7e5f460e SG	424	x = hextoul(argv[1], NULL);
7e5f460e SG	425	y = hextoul(argv[2], NULL);
2da0fc0d DE	426	rp = argv[3];
	427
	428
	429	while (*rp) {
	430	char substr[5];
	431
	432	memcpy(substr, rp, 4);
	433	substr[4] = 0;
7e5f460e	434	*wp = hextoul(substr, NULL);
2da0fc0d DE	435
	436	rp += 4;
	437	wp++;
0f0c1021	438	if (wp - buffer > base_width)
2da0fc0d DE	439	break;
	440	}
	441
	442	for (k = 0; k < count; ++k) {
	443	unsigned offset =
0f0c1021	444	y * base_width + x + k * (wp - buffer);
2da0fc0d DE	445	osd_write_videomem(screen, offset, buffer,
	446	wp - buffer);
	447	}
acff73fd DE	448
acff73fd DE	449	OSD_SET_REG(screen, control, 0x0049);
a605ea7e DE	450	}
	451
	452	return 0;
	453	}
	454
09140113	455	int osd_size(struct cmd_tbl cmdtp, int flag, int argc, char const argv[])
da4833c7 DE	456	{
	457	unsigned screen;
	458	unsigned x;
	459	unsigned y;
	460
	461	if (argc < 3) {
	462	cmd_usage(cmdtp);
	463	return 1;
	464	}
	465
7e5f460e SG	466	x = hextoul(argv[1], NULL);
7e5f460e SG	467	y = hextoul(argv[2], NULL);
da4833c7 DE	468
	469	if (!x \|\| (x > 64) \|\| (x > MAX_X_CHARS) \|\|
	470	!y \|\| (y > 32) \|\| (y > MAX_Y_CHARS)) {
	471	cmd_usage(cmdtp);
	472	return 1;
	473	}
	474
	475	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
df3223f9 DE	476	if (!(osd_screen_mask & (1 << screen)))
	477	continue;
	478
da4833c7 DE	479	OSD_SET_REG(screen, xy_size, ((x - 1) << 8) \| (y - 1));
	480	OSD_SET_REG(screen, x_pos, 32767 * (640 - 12 * x) / 65535);
	481	OSD_SET_REG(screen, y_pos, 32767 * (480 - 18 * y) / 65535);
	482	}
	483
	484	return 0;
	485	}
	486
a605ea7e DE	487	U_BOOT_CMD(
	488	osdw, 5, 0, osd_write,
	489	"write 16-bit hex encoded buffer to osd memory",
	490	"pos_x pos_y buffer count\n"
	491	);
	492
	493	U_BOOT_CMD(
	494	osdp, 5, 0, osd_print,
	495	"write ASCII buffer to osd memory",
	496	"pos_x pos_y color text\n"
	497	);
da4833c7 DE	498
	499	U_BOOT_CMD(
	500	osdsize, 3, 0, osd_size,
	501	"set OSD XY size in characters",
	502	"size_x(max. " __stringify(MAX_X_CHARS)
	503	") size_y(max. " __stringify(MAX_Y_CHARS) ")\n"
	504	);
fe4a9675	505
09140113	506	#endif /* CONFIG_GDSYS_LEGACY_DRIVERS */