[people/ms/u-boot.git] / board / ge / bx50v3 / bx50v3.c

/*
 * Copyright 2015 Timesys Corporation
 * Copyright 2015 General Electric Company
 * Copyright 2012 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/video.h>
#include <mmc.h>
#include <fsl_esdhc.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
#include <i2c.h>
#include <pwm.h>
DECLARE_GLOBAL_DATA_PTR;

#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP |	\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |	\
	PAD_CTL_HYS)

#define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

#define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE |	\
	PAD_CTL_SPEED_HIGH | PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)

#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED | \
	PAD_CTL_DSE_120ohm | PAD_CTL_SRE_FAST)

#define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
	PAD_CTL_SPEED_HIGH   | PAD_CTL_SRE_FAST)

#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)

#define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
	PAD_CTL_ODE | PAD_CTL_SRE_FAST)

#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)

int dram_init(void)
{
	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);

	return 0;
}

static iomux_v3_cfg_t const uart3_pads[] = {
	MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static iomux_v3_cfg_t const uart4_pads[] = {
	MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
	MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};

static iomux_v3_cfg_t const enet_pads[] = {
	MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_MDC__ENET_MDC   | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK  | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
	MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	/* AR8033 PHY Reset */
	MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void setup_iomux_enet(void)
{
	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));

	/* Reset AR8033 PHY */
	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
	udelay(500);
	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
}

static iomux_v3_cfg_t const usdhc2_pads[] = {
	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const usdhc3_pads[] = {
	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};

static iomux_v3_cfg_t const usdhc4_pads[] = {
	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
	MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const ecspi1_pads[] = {
	MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
	MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static struct i2c_pads_info i2c_pad_info1 = {
	.scl = {
		.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | I2C_PAD,
		.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | I2C_PAD,
		.gp = IMX_GPIO_NR(5, 27)
	},
	.sda = {
		.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | I2C_PAD,
		.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | I2C_PAD,
		.gp = IMX_GPIO_NR(5, 26)
	}
};

static struct i2c_pads_info i2c_pad_info2 = {
	.scl = {
		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
		.gp = IMX_GPIO_NR(4, 12)
	},
	.sda = {
		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
		.gp = IMX_GPIO_NR(4, 13)
	}
};

static struct i2c_pads_info i2c_pad_info3 = {
	.scl = {
		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | I2C_PAD,
		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | I2C_PAD,
		.gp = IMX_GPIO_NR(1, 3)
	},
	.sda = {
		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | I2C_PAD,
		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | I2C_PAD,
		.gp = IMX_GPIO_NR(1, 6)
	}
};

#ifdef CONFIG_MXC_SPI
int board_spi_cs_gpio(unsigned bus, unsigned cs)
{
	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
}

static void setup_spi(void)
{
	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
}
#endif

static iomux_v3_cfg_t const pcie_pads[] = {
	MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
	MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void setup_pcie(void)
{
	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
}

static void setup_iomux_uart(void)
{
	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
}

#ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg usdhc_cfg[3] = {
	{USDHC2_BASE_ADDR},
	{USDHC3_BASE_ADDR},
	{USDHC4_BASE_ADDR},
};

#define USDHC2_CD_GPIO	IMX_GPIO_NR(1, 4)
#define USDHC4_CD_GPIO	IMX_GPIO_NR(6, 11)

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC2_BASE_ADDR:
		ret = !gpio_get_value(USDHC2_CD_GPIO);
		break;
	case USDHC3_BASE_ADDR:
		ret = 1; /* eMMC is always present */
		break;
	case USDHC4_BASE_ADDR:
		ret = !gpio_get_value(USDHC4_CD_GPIO);
		break;
	}

	return ret;
}

int board_mmc_init(bd_t *bis)
{
	int ret;
	int i;

	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
		switch (i) {
		case 0:
			imx_iomux_v3_setup_multiple_pads(
				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
			gpio_direction_input(USDHC2_CD_GPIO);
			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
			break;
		case 1:
			imx_iomux_v3_setup_multiple_pads(
				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
			break;
		case 2:
			imx_iomux_v3_setup_multiple_pads(
				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
			gpio_direction_input(USDHC4_CD_GPIO);
			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
			break;
		default:
			printf("Warning: you configured more USDHC controllers\n"
			       "(%d) then supported by the board (%d)\n",
			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
			return -EINVAL;
		}

		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		if (ret)
			return ret;
	}

	return 0;
}
#endif

static int mx6_rgmii_rework(struct phy_device *phydev)
{
	/* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
	/* set device address 0x7 */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
	/* offset 0x8016: CLK_25M Clock Select */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
	/* enable register write, no post increment, address 0x7 */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
	/* set to 125 MHz from local PLL source */
	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);

	/* rgmii tx clock delay enable */
	/* set debug port address: SerDes Test and System Mode Control */
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
	/* enable rgmii tx clock delay */
	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);

	return 0;
}

int board_phy_config(struct phy_device *phydev)
{
	mx6_rgmii_rework(phydev);

	if (phydev->drv->config)
		phydev->drv->config(phydev);

	return 0;
}

#if defined(CONFIG_VIDEO_IPUV3)
static iomux_v3_cfg_t const backlight_pads[] = {
	/* Power for LVDS Display */
	MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
	/* Backlight enable for LVDS display */
	MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
	/* backlight PWM brightness control */
	MX6_PAD_SD1_DAT3__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static void do_enable_hdmi(struct display_info_t const *dev)
{
	imx_enable_hdmi_phy();
}

int board_cfb_skip(void)
{
	gpio_direction_output(LVDS_POWER_GP, 1);

	return 0;
}

static int detect_baseboard(struct display_info_t const *dev)
{
	if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) ||
	    IS_ENABLED(CONFIG_TARGET_GE_B650V3))
		return 1;

	return 0;
}

struct display_info_t const displays[] = {{
	.bus	= -1,
	.addr	= -1,
	.pixfmt	= IPU_PIX_FMT_RGB24,
	.detect	= detect_baseboard,
	.enable	= NULL,
	.mode	= {
		.name           = "G121X1-L03",
		.refresh        = 60,
		.xres           = 1024,
		.yres           = 768,
		.pixclock       = 15385,
		.left_margin    = 20,
		.right_margin   = 300,
		.upper_margin   = 30,
		.lower_margin   = 8,
		.hsync_len      = 1,
		.vsync_len      = 1,
		.sync           = FB_SYNC_EXT,
		.vmode          = FB_VMODE_NONINTERLACED
} }, {
	.bus	= -1,
	.addr	= 3,
	.pixfmt	= IPU_PIX_FMT_RGB24,
	.detect	= detect_hdmi,
	.enable	= do_enable_hdmi,
	.mode	= {
		.name           = "HDMI",
		.refresh        = 60,
		.xres           = 1024,
		.yres           = 768,
		.pixclock       = 15385,
		.left_margin    = 220,
		.right_margin   = 40,
		.upper_margin   = 21,
		.lower_margin   = 7,
		.hsync_len      = 60,
		.vsync_len      = 10,
		.sync           = FB_SYNC_EXT,
		.vmode          = FB_VMODE_NONINTERLACED
} } };
size_t display_count = ARRAY_SIZE(displays);

static void enable_videopll(void)
{
	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	s32 timeout = 100000;

	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);

	/* set video pll to 910MHz (24MHz * (37+11/12))
	* video pll post div to 910/4 = 227.5MHz
	*/
	clrsetbits_le32(&ccm->analog_pll_video,
			BM_ANADIG_PLL_VIDEO_DIV_SELECT |
			BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
			BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) |
			BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));

	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);

	clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);

	while (timeout--)
		if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
			break;

	if (timeout < 0)
		printf("Warning: video pll lock timeout!\n");

	clrsetbits_le32(&ccm->analog_pll_video,
			BM_ANADIG_PLL_VIDEO_BYPASS,
			BM_ANADIG_PLL_VIDEO_ENABLE);
}

static void setup_display_b850v3(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	enable_videopll();

	/* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
	clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);

	imx_setup_hdmi();

	/* Set LDB_DI0 as clock source for IPU_DI0 */
	clrsetbits_le32(&mxc_ccm->chsccdr,
			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
			(CHSCCDR_CLK_SEL_LDB_DI0 <<
			 MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));

	/* Turn on IPU LDB DI0 clocks */
	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);

	enable_ipu_clock();

	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
	       IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
	       IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
	       IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
	       IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT |
	       IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
	       IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
	       IOMUXC_GPR2_SPLIT_MODE_EN_MASK |
	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
	       IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
	       &iomux->gpr[2]);

	clrbits_le32(&iomux->gpr[3],
		     IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
		     IOMUXC_GPR3_LVDS1_MUX_CTL_MASK |
		     IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
}

static void setup_display_bx50v3(void)
{
	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

	/* When a reset/reboot is performed the display power needs to be turned
	 * off for atleast 500ms. The boot time is ~300ms, we need to wait for
	 * an additional 200ms here. Unfortunately we use external PMIC for
	 * doing the reset, so can not differentiate between POR vs soft reset
	 */
	mdelay(200);

	/* IPU1 DI0 clock is 480/7 = 68.5 MHz */
	setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);

	/* Set LDB_DI0 as clock source for IPU_DI0 */
	clrsetbits_le32(&mxc_ccm->chsccdr,
			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
			(CHSCCDR_CLK_SEL_LDB_DI0 <<
			MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));

	/* Turn on IPU LDB DI0 clocks */
	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);

	enable_ipu_clock();

	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
	       IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
	       IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
	       IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
	       IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
	       &iomux->gpr[2]);

	clrsetbits_le32(&iomux->gpr[3],
			IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
		       (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
			IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));

	/* backlights off until needed */
	imx_iomux_v3_setup_multiple_pads(backlight_pads,
					 ARRAY_SIZE(backlight_pads));
	gpio_direction_input(LVDS_POWER_GP);
	gpio_direction_input(LVDS_BACKLIGHT_GP);
}
#endif /* CONFIG_VIDEO_IPUV3 */

/*
 * Do not overwrite the console
 * Use always serial for U-Boot console
 */
int overwrite_console(void)
{
	return 1;
}

int board_eth_init(bd_t *bis)
{
	setup_iomux_enet();
	setup_pcie();

	return cpu_eth_init(bis);
}

static iomux_v3_cfg_t const misc_pads[] = {
	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(NO_PAD_CTRL),
	MX6_PAD_EIM_A25__GPIO5_IO02	| MUX_PAD_CTRL(NC_PAD_CTRL),
	MX6_PAD_EIM_CS0__GPIO2_IO23	| MUX_PAD_CTRL(NC_PAD_CTRL),
	MX6_PAD_EIM_CS1__GPIO2_IO24	| MUX_PAD_CTRL(NC_PAD_CTRL),
	MX6_PAD_EIM_OE__GPIO2_IO25	| MUX_PAD_CTRL(NC_PAD_CTRL),
	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(NC_PAD_CTRL),
	MX6_PAD_GPIO_1__GPIO1_IO01	| MUX_PAD_CTRL(NC_PAD_CTRL),
};
#define SUS_S3_OUT	IMX_GPIO_NR(4, 11)
#define WIFI_EN	IMX_GPIO_NR(6, 14)

int board_early_init_f(void)
{
	imx_iomux_v3_setup_multiple_pads(misc_pads,
					 ARRAY_SIZE(misc_pads));

	setup_iomux_uart();

#if defined(CONFIG_VIDEO_IPUV3)
	if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
		/* Set LDB clock to Video PLL */
		select_ldb_di_clock_source(MXC_PLL5_CLK);
	else
		/* Set LDB clock to USB PLL */
		select_ldb_di_clock_source(MXC_PLL3_SW_CLK);
#endif
	return 0;
}

int board_init(void)
{
	gpio_direction_output(SUS_S3_OUT, 1);
	gpio_direction_output(WIFI_EN, 1);
#if defined(CONFIG_VIDEO_IPUV3)
	if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
		setup_display_b850v3();
	else
		setup_display_bx50v3();
#endif
	/* address of boot parameters */
	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

#ifdef CONFIG_MXC_SPI
	setup_spi();
#endif
	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);

	return 0;
}

#ifdef CONFIG_CMD_BMODE
static const struct boot_mode board_boot_modes[] = {
	/* 4 bit bus width */
	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	{NULL,	 0},
};
#endif

int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(board_boot_modes);
#endif

#ifdef CONFIG_VIDEO_IPUV3
	/* We need at least 200ms between power on and backlight on
	 * as per specifications from CHI MEI */
	mdelay(250);

	/* enable backlight PWM 1 */
	pwm_init(0, 0, 0);

	/* duty cycle 5000000ns, period: 5000000ns */
	pwm_config(0, 5000000, 5000000);

	/* Backlight Power */
	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);

	pwm_enable(0);
#endif

	return 0;
}

int checkboard(void)
{
	printf("BOARD: %s\n", CONFIG_BOARD_NAME);
	return 0;
}
Commit	Line	Data
f9162b15 AB	1	/*
	2	* Copyright 2015 Timesys Corporation
	3	* Copyright 2015 General Electric Company
	4	* Copyright 2012 Freescale Semiconductor, Inc.
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <asm/arch/clock.h>
	10	#include <asm/arch/imx-regs.h>
	11	#include <asm/arch/iomux.h>
	12	#include <asm/arch/mx6-pins.h>
	13	#include <asm/errno.h>
	14	#include <asm/gpio.h>
	15	#include <asm/imx-common/mxc_i2c.h>
	16	#include <asm/imx-common/iomux-v3.h>
	17	#include <asm/imx-common/boot_mode.h>
	18	#include <asm/imx-common/video.h>
	19	#include <mmc.h>
	20	#include <fsl_esdhc.h>
	21	#include <miiphy.h>
	22	#include <netdev.h>
	23	#include <asm/arch/mxc_hdmi.h>
	24	#include <asm/arch/crm_regs.h>
	25	#include <asm/io.h>
	26	#include <asm/arch/sys_proto.h>
	27	#include <i2c.h>
54971ac6	28	#include <pwm.h>
f9162b15 AB	29	DECLARE_GLOBAL_DATA_PTR;
f9162b15 AB	30
7d0b8cfe JW	31	#define NC_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	32	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	33	PAD_CTL_HYS)
	34
f9162b15 AB	35	#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	36	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| \
	37	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	38
	39	#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP \| \
	40	PAD_CTL_SPEED_LOW \| PAD_CTL_DSE_80ohm \| \
	41	PAD_CTL_SRE_FAST \| PAD_CTL_HYS)
	42
	43	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| PAD_CTL_PUE \| \
	44	PAD_CTL_SPEED_HIGH \| PAD_CTL_DSE_48ohm \| PAD_CTL_SRE_FAST)
	45
	46	#define ENET_CLK_PAD_CTRL (PAD_CTL_SPEED_MED \| \
	47	PAD_CTL_DSE_120ohm \| PAD_CTL_SRE_FAST)
	48
	49	#define ENET_RX_PAD_CTRL (PAD_CTL_PKE \| PAD_CTL_PUE \| \
	50	PAD_CTL_SPEED_HIGH \| PAD_CTL_SRE_FAST)
	51
	52	#define SPI_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_SPEED_MED \| \
	53	PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
	54
	55	#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
	56	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS \| \
	57	PAD_CTL_ODE \| PAD_CTL_SRE_FAST)
	58
	59	#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
	60
	61	int dram_init(void)
	62	{
	63	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
	64
	65	return 0;
	66	}
	67
	68	static iomux_v3_cfg_t const uart3_pads[] = {
	69	MX6_PAD_EIM_D31__UART3_RTS_B \| MUX_PAD_CTRL(UART_PAD_CTRL),
	70	MX6_PAD_EIM_D23__UART3_CTS_B \| MUX_PAD_CTRL(UART_PAD_CTRL),
	71	MX6_PAD_EIM_D24__UART3_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL),
	72	MX6_PAD_EIM_D25__UART3_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL),
	73	};
	74
	75	static iomux_v3_cfg_t const uart4_pads[] = {
	76	MX6_PAD_KEY_COL0__UART4_TX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL),
	77	MX6_PAD_KEY_ROW0__UART4_RX_DATA \| MUX_PAD_CTRL(UART_PAD_CTRL),
	78	};
	79
	80	static iomux_v3_cfg_t const enet_pads[] = {
	81	MX6_PAD_ENET_MDIO__ENET_MDIO \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	82	MX6_PAD_ENET_MDC__ENET_MDC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	83	MX6_PAD_RGMII_TXC__RGMII_TXC \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	84	MX6_PAD_RGMII_TD0__RGMII_TD0 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	85	MX6_PAD_RGMII_TD1__RGMII_TD1 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	86	MX6_PAD_RGMII_TD2__RGMII_TD2 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	87	MX6_PAD_RGMII_TD3__RGMII_TD3 \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	88	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL \| MUX_PAD_CTRL(ENET_PAD_CTRL),
	89	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK \| MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
	90	MX6_PAD_RGMII_RXC__RGMII_RXC \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	91	MX6_PAD_RGMII_RD0__RGMII_RD0 \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	92	MX6_PAD_RGMII_RD1__RGMII_RD1 \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	93	MX6_PAD_RGMII_RD2__RGMII_RD2 \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	94	MX6_PAD_RGMII_RD3__RGMII_RD3 \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	95	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL \| MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
	96	/* AR8033 PHY Reset */
	97	MX6_PAD_ENET_TX_EN__GPIO1_IO28 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	98	};
99
100	static void setup_iomux_enet(void)
101	{
102	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
103
104	/* Reset AR8033 PHY */
105	gpio_direction_output(IMX_GPIO_NR(1, 28), 0);
106	udelay(500);
107	gpio_set_value(IMX_GPIO_NR(1, 28), 1);
108	}
109
110	static iomux_v3_cfg_t const usdhc2_pads[] = {
111	MX6_PAD_SD2_CLK__SD2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
112	MX6_PAD_SD2_CMD__SD2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
113	MX6_PAD_SD2_DAT0__SD2_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
114	MX6_PAD_SD2_DAT1__SD2_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
115	MX6_PAD_SD2_DAT2__SD2_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
116	MX6_PAD_SD2_DAT3__SD2_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
117	MX6_PAD_GPIO_4__GPIO1_IO04 \| MUX_PAD_CTRL(NO_PAD_CTRL),
118	};
119
120	static iomux_v3_cfg_t const usdhc3_pads[] = {
121	MX6_PAD_SD3_CLK__SD3_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
122	MX6_PAD_SD3_CMD__SD3_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
123	MX6_PAD_SD3_RST__SD3_RESET \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
124	MX6_PAD_SD3_DAT0__SD3_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
125	MX6_PAD_SD3_DAT1__SD3_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
126	MX6_PAD_SD3_DAT2__SD3_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
127	MX6_PAD_SD3_DAT3__SD3_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
128	MX6_PAD_SD3_DAT4__SD3_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
129	MX6_PAD_SD3_DAT5__SD3_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
130	MX6_PAD_SD3_DAT6__SD3_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
131	MX6_PAD_SD3_DAT7__SD3_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
132	};
133
134	static iomux_v3_cfg_t const usdhc4_pads[] = {
135	MX6_PAD_SD4_CLK__SD4_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
136	MX6_PAD_SD4_CMD__SD4_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
137	MX6_PAD_SD4_DAT0__SD4_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
138	MX6_PAD_SD4_DAT1__SD4_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
139	MX6_PAD_SD4_DAT2__SD4_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
140	MX6_PAD_SD4_DAT3__SD4_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
141	MX6_PAD_SD4_DAT4__SD4_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
142	MX6_PAD_SD4_DAT5__SD4_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
143	MX6_PAD_SD4_DAT6__SD4_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
144	MX6_PAD_SD4_DAT7__SD4_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
145	MX6_PAD_NANDF_CS0__GPIO6_IO11 \| MUX_PAD_CTRL(NO_PAD_CTRL),
146	MX6_PAD_NANDF_CS1__GPIO6_IO14 \| MUX_PAD_CTRL(NO_PAD_CTRL),
147	};
148
149	static iomux_v3_cfg_t const ecspi1_pads[] = {
150	MX6_PAD_EIM_D16__ECSPI1_SCLK \| MUX_PAD_CTRL(SPI_PAD_CTRL),
151	MX6_PAD_EIM_D17__ECSPI1_MISO \| MUX_PAD_CTRL(SPI_PAD_CTRL),
152	MX6_PAD_EIM_D18__ECSPI1_MOSI \| MUX_PAD_CTRL(SPI_PAD_CTRL),
153	MX6_PAD_EIM_EB2__GPIO2_IO30 \| MUX_PAD_CTRL(NO_PAD_CTRL),
154	};
155
156	static struct i2c_pads_info i2c_pad_info1 = {
157	.scl = {
158	.i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL \| I2C_PAD,
159	.gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 \| I2C_PAD,
160	.gp = IMX_GPIO_NR(5, 27)
161	},
162	.sda = {
163	.i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA \| I2C_PAD,
164	.gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 \| I2C_PAD,
165	.gp = IMX_GPIO_NR(5, 26)
166	}
167	};
168
169	static struct i2c_pads_info i2c_pad_info2 = {
170	.scl = {
171	.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL \| I2C_PAD,
172	.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 \| I2C_PAD,
173	.gp = IMX_GPIO_NR(4, 12)
174	},
175	.sda = {
176	.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA \| I2C_PAD,
177	.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 \| I2C_PAD,
178	.gp = IMX_GPIO_NR(4, 13)
179	}
180	};
181
182	static struct i2c_pads_info i2c_pad_info3 = {
183	.scl = {
184	.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL \| I2C_PAD,
185	.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 \| I2C_PAD,
186	.gp = IMX_GPIO_NR(1, 3)
187	},
188	.sda = {
189	.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA \| I2C_PAD,
190	.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 \| I2C_PAD,
191	.gp = IMX_GPIO_NR(1, 6)
192	}
193	};
194
195	#ifdef CONFIG_MXC_SPI
196	int board_spi_cs_gpio(unsigned bus, unsigned cs)
197	{
198	return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(2, 30)) : -1;
199	}
200
201	static void setup_spi(void)
202	{
203	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
204	}
205	#endif
206
207	static iomux_v3_cfg_t const pcie_pads[] = {
208	MX6_PAD_GPIO_5__GPIO1_IO05 \| MUX_PAD_CTRL(NO_PAD_CTRL),
209	MX6_PAD_GPIO_17__GPIO7_IO12 \| MUX_PAD_CTRL(NO_PAD_CTRL),
210	};
211
212	static void setup_pcie(void)
213	{
214	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
215	}
216
217	static void setup_iomux_uart(void)
218	{
219	imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
220	imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
221	}
222
223	#ifdef CONFIG_FSL_ESDHC
224	struct fsl_esdhc_cfg usdhc_cfg[3] = {
225	{USDHC2_BASE_ADDR},
226	{USDHC3_BASE_ADDR},
227	{USDHC4_BASE_ADDR},
228	};
229
230	#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
231	#define USDHC4_CD_GPIO IMX_GPIO_NR(6, 11)
232
233	int board_mmc_getcd(struct mmc *mmc)
234	{
235	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
236	int ret = 0;
237
238	switch (cfg->esdhc_base) {
239	case USDHC2_BASE_ADDR:
240	ret = !gpio_get_value(USDHC2_CD_GPIO);
241	break;
242	case USDHC3_BASE_ADDR:
243	ret = 1; /* eMMC is always present */
244	break;
245	case USDHC4_BASE_ADDR:
246	ret = !gpio_get_value(USDHC4_CD_GPIO);
247	break;
248	}
249
250	return ret;
251	}
252
253	int board_mmc_init(bd_t *bis)
254	{
255	int ret;
256	int i;
257
258	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
259	switch (i) {
260	case 0:
261	imx_iomux_v3_setup_multiple_pads(
262	usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
263	gpio_direction_input(USDHC2_CD_GPIO);
264	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
265	break;
266	case 1:
267	imx_iomux_v3_setup_multiple_pads(
268	usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
269	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
270	break;
271	case 2:
272	imx_iomux_v3_setup_multiple_pads(
273	usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
274	gpio_direction_input(USDHC4_CD_GPIO);
275	usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
276	break;
277	default:
278	printf("Warning: you configured more USDHC controllers\n"
279	"(%d) then supported by the board (%d)\n",
280	i + 1, CONFIG_SYS_FSL_USDHC_NUM);
281	return -EINVAL;
282	}
283
284	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
285	if (ret)
286	return ret;
287	}
288
289	return 0;
290	}
291	#endif
292
293	static int mx6_rgmii_rework(struct phy_device *phydev)
294	{
295	/* Configure AR8033 to ouput a 125MHz clk from CLK_25M */
296	/* set device address 0x7 */
297	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
298	/* offset 0x8016: CLK_25M Clock Select */
299	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
300	/* enable register write, no post increment, address 0x7 */
301	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
302	/* set to 125 MHz from local PLL source */
303	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x18);
304
305	/* rgmii tx clock delay enable */
306	/* set debug port address: SerDes Test and System Mode Control */
307	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
308	/* enable rgmii tx clock delay */
309	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
310
311	return 0;
312	}
313
314	int board_phy_config(struct phy_device *phydev)
315	{
316	mx6_rgmii_rework(phydev);
317
318	if (phydev->drv->config)
319	phydev->drv->config(phydev);
320
321	return 0;
322	}
323
324	#if defined(CONFIG_VIDEO_IPUV3)
325	static iomux_v3_cfg_t const backlight_pads[] = {
326	/* Power for LVDS Display */
327	MX6_PAD_EIM_D22__GPIO3_IO22 \| MUX_PAD_CTRL(NO_PAD_CTRL),
328	#define LVDS_POWER_GP IMX_GPIO_NR(3, 22)
329	/* Backlight enable for LVDS display */
330	MX6_PAD_GPIO_0__GPIO1_IO00 \| MUX_PAD_CTRL(NO_PAD_CTRL),
331	#define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 0)
54971ac6 AB	332	/* backlight PWM brightness control */
54971ac6 AB	333	MX6_PAD_SD1_DAT3__PWM1_OUT \| MUX_PAD_CTRL(NO_PAD_CTRL),
f9162b15 AB	334	};
	335
	336	static void do_enable_hdmi(struct display_info_t const *dev)
	337	{
	338	imx_enable_hdmi_phy();
	339	}
	340
	341	int board_cfb_skip(void)
	342	{
	343	gpio_direction_output(LVDS_POWER_GP, 1);
	344
	345	return 0;
	346	}
	347
	348	static int detect_baseboard(struct display_info_t const *dev)
	349	{
	350	if (IS_ENABLED(CONFIG_TARGET_GE_B450V3) \|\|
	351	IS_ENABLED(CONFIG_TARGET_GE_B650V3))
	352	return 1;
	353
	354	return 0;
	355	}
	356
	357	struct display_info_t const displays[] = {{
	358	.bus = -1,
	359	.addr = -1,
	360	.pixfmt = IPU_PIX_FMT_RGB24,
	361	.detect = detect_baseboard,
	362	.enable = NULL,
	363	.mode = {
	364	.name = "G121X1-L03",
	365	.refresh = 60,
	366	.xres = 1024,
	367	.yres = 768,
	368	.pixclock = 15385,
	369	.left_margin = 20,
	370	.right_margin = 300,
	371	.upper_margin = 30,
	372	.lower_margin = 8,
	373	.hsync_len = 1,
	374	.vsync_len = 1,
	375	.sync = FB_SYNC_EXT,
	376	.vmode = FB_VMODE_NONINTERLACED
	377	} }, {
	378	.bus = -1,
	379	.addr = 3,
	380	.pixfmt = IPU_PIX_FMT_RGB24,
	381	.detect = detect_hdmi,
	382	.enable = do_enable_hdmi,
	383	.mode = {
	384	.name = "HDMI",
	385	.refresh = 60,
	386	.xres = 1024,
	387	.yres = 768,
	388	.pixclock = 15385,
	389	.left_margin = 220,
	390	.right_margin = 40,
	391	.upper_margin = 21,
	392	.lower_margin = 7,
	393	.hsync_len = 60,
	394	.vsync_len = 10,
	395	.sync = FB_SYNC_EXT,
	396	.vmode = FB_VMODE_NONINTERLACED
	397	} } };
398	size_t display_count = ARRAY_SIZE(displays);
399
494d43ec AB	400	static void enable_videopll(void)
	401	{
	402	struct mxc_ccm_reg ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	403	s32 timeout = 100000;
	404
	405	setbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
	406
	407	/* set video pll to 910MHz (24MHz * (37+11/12))
	408	* video pll post div to 910/4 = 227.5MHz
	409	*/
	410	clrsetbits_le32(&ccm->analog_pll_video,
	411	BM_ANADIG_PLL_VIDEO_DIV_SELECT \|
	412	BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
	413	BF_ANADIG_PLL_VIDEO_DIV_SELECT(37) \|
	414	BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0));
	415
	416	writel(BF_ANADIG_PLL_VIDEO_NUM_A(11), &ccm->analog_pll_video_num);
	417	writel(BF_ANADIG_PLL_VIDEO_DENOM_B(12), &ccm->analog_pll_video_denom);
	418
	419	clrbits_le32(&ccm->analog_pll_video, BM_ANADIG_PLL_VIDEO_POWERDOWN);
	420
	421	while (timeout--)
	422	if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
	423	break;
	424
	425	if (timeout < 0)
	426	printf("Warning: video pll lock timeout!\n");
	427
	428	clrsetbits_le32(&ccm->analog_pll_video,
	429	BM_ANADIG_PLL_VIDEO_BYPASS,
	430	BM_ANADIG_PLL_VIDEO_ENABLE);
	431	}
	432
de708da0	433	static void setup_display_b850v3(void)
f9162b15 AB	434	{
	435	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	436	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
f9162b15	437
494d43ec AB	438	enable_videopll();
494d43ec AB	439
de708da0 AB	440	/* IPU1 D0 clock is 227.5 / 3.5 = 65MHz */
	441	clrbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
	442
f9162b15 AB	443	imx_setup_hdmi();
f9162b15 AB	444
de708da0 AB	445	/* Set LDB_DI0 as clock source for IPU_DI0 */
	446	clrsetbits_le32(&mxc_ccm->chsccdr,
	447	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
	448	(CHSCCDR_CLK_SEL_LDB_DI0 <<
	449	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
	450
	451	/* Turn on IPU LDB DI0 clocks */
	452	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
	453
	454	enable_ipu_clock();
	455
	456	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES \|
	457	IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW \|
	458	IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW \|
	459	IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG \|
	460	IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT \|
	461	IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG \|
	462	IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT \|
	463	IOMUXC_GPR2_SPLIT_MODE_EN_MASK \|
	464	IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 \|
	465	IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0,
	466	&iomux->gpr[2]);
	467
	468	clrbits_le32(&iomux->gpr[3],
	469	IOMUXC_GPR3_LVDS0_MUX_CTL_MASK \|
	470	IOMUXC_GPR3_LVDS1_MUX_CTL_MASK \|
	471	IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
	472	}
	473
	474	static void setup_display_bx50v3(void)
	475	{
	476	struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )CCM_BASE_ADDR;
	477	struct iomuxc iomux = (struct iomuxc )IOMUXC_BASE_ADDR;
	478
8d293f49 AB	479	/* When a reset/reboot is performed the display power needs to be turned
	480	* off for atleast 500ms. The boot time is ~300ms, we need to wait for
	481	* an additional 200ms here. Unfortunately we use external PMIC for
	482	* doing the reset, so can not differentiate between POR vs soft reset
	483	*/
	484	mdelay(200);
	485
de708da0 AB	486	/* IPU1 DI0 clock is 480/7 = 68.5 MHz */
	487	setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
	488
	489	/* Set LDB_DI0 as clock source for IPU_DI0 */
	490	clrsetbits_le32(&mxc_ccm->chsccdr,
	491	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK,
	492	(CHSCCDR_CLK_SEL_LDB_DI0 <<
	493	MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET));
	494
	495	/* Turn on IPU LDB DI0 clocks */
	496	setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
	497
	498	enable_ipu_clock();
	499
	500	writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES \|
	501	IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW \|
	502	IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG \|
	503	IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT \|
	504	IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
	505	&iomux->gpr[2]);
	506
	507	clrsetbits_le32(&iomux->gpr[3],
	508	IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
	509	(IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
	510	IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET));
f9162b15 AB	511
	512	/* backlights off until needed */
	513	imx_iomux_v3_setup_multiple_pads(backlight_pads,
	514	ARRAY_SIZE(backlight_pads));
	515	gpio_direction_input(LVDS_POWER_GP);
	516	gpio_direction_input(LVDS_BACKLIGHT_GP);
	517	}
	518	#endif /* CONFIG_VIDEO_IPUV3 */
	519
	520	/*
	521	* Do not overwrite the console
	522	* Use always serial for U-Boot console
	523	*/
	524	int overwrite_console(void)
	525	{
	526	return 1;
	527	}
	528
	529	int board_eth_init(bd_t *bis)
	530	{
	531	setup_iomux_enet();
	532	setup_pcie();
	533
	534	return cpu_eth_init(bis);
	535	}
	536
	537	static iomux_v3_cfg_t const misc_pads[] = {
	538	MX6_PAD_KEY_ROW2__GPIO4_IO11 \| MUX_PAD_CTRL(NO_PAD_CTRL),
7d0b8cfe JW	539	MX6_PAD_EIM_A25__GPIO5_IO02 \| MUX_PAD_CTRL(NC_PAD_CTRL),
	540	MX6_PAD_EIM_CS0__GPIO2_IO23 \| MUX_PAD_CTRL(NC_PAD_CTRL),
	541	MX6_PAD_EIM_CS1__GPIO2_IO24 \| MUX_PAD_CTRL(NC_PAD_CTRL),
	542	MX6_PAD_EIM_OE__GPIO2_IO25 \| MUX_PAD_CTRL(NC_PAD_CTRL),
	543	MX6_PAD_EIM_BCLK__GPIO6_IO31 \| MUX_PAD_CTRL(NC_PAD_CTRL),
	544	MX6_PAD_GPIO_1__GPIO1_IO01 \| MUX_PAD_CTRL(NC_PAD_CTRL),
f9162b15 AB	545	};
	546	#define SUS_S3_OUT IMX_GPIO_NR(4, 11)
	547	#define WIFI_EN IMX_GPIO_NR(6, 14)
	548
	549	int board_early_init_f(void)
	550	{
	551	imx_iomux_v3_setup_multiple_pads(misc_pads,
	552	ARRAY_SIZE(misc_pads));
	553
	554	setup_iomux_uart();
	555
494d43ec AB	556	#if defined(CONFIG_VIDEO_IPUV3)
	557	if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
	558	/* Set LDB clock to Video PLL */
	559	select_ldb_di_clock_source(MXC_PLL5_CLK);
	560	else
	561	/* Set LDB clock to USB PLL */
	562	select_ldb_di_clock_source(MXC_PLL3_SW_CLK);
	563	#endif
f9162b15 AB	564	return 0;
	565	}
	566
	567	int board_init(void)
	568	{
	569	gpio_direction_output(SUS_S3_OUT, 1);
	570	gpio_direction_output(WIFI_EN, 1);
	571	#if defined(CONFIG_VIDEO_IPUV3)
de708da0 AB	572	if (IS_ENABLED(CONFIG_TARGET_GE_B850V3))
	573	setup_display_b850v3();
	574	else
	575	setup_display_bx50v3();
f9162b15 AB	576	#endif
	577	/* address of boot parameters */
	578	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	579
	580	#ifdef CONFIG_MXC_SPI
	581	setup_spi();
	582	#endif
	583	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
	584	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
	585	setup_i2c(3, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info3);
	586
	587	return 0;
	588	}
	589
	590	#ifdef CONFIG_CMD_BMODE
	591	static const struct boot_mode board_boot_modes[] = {
	592	/* 4 bit bus width */
	593	{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
	594	{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
	595	{NULL, 0},
	596	};
	597	#endif
	598
	599	int board_late_init(void)
	600	{
	601	#ifdef CONFIG_CMD_BMODE
	602	add_board_boot_modes(board_boot_modes);
	603	#endif
0c344e6e AS	604
0c344e6e AS	605	#ifdef CONFIG_VIDEO_IPUV3
f9162b15 AB	606	/* We need at least 200ms between power on and backlight on
	607	* as per specifications from CHI MEI */
	608	mdelay(250);
	609
54971ac6 AB	610	/* enable backlight PWM 1 */
	611	pwm_init(0, 0, 0);
	612
	613	/* duty cycle 5000000ns, period: 5000000ns */
	614	pwm_config(0, 5000000, 5000000);
	615
f9162b15 AB	616	/* Backlight Power */
	617	gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
	618
54971ac6	619	pwm_enable(0);
0c344e6e	620	#endif
54971ac6	621
f9162b15 AB	622	return 0;
	623	}
	624
	625	int checkboard(void)
	626	{
	627	printf("BOARD: %s\n", CONFIG_BOARD_NAME);
	628	return 0;
	629	}