[people/ms/u-boot.git] / board / gen860t / gen860t.c

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 * Keith Outwater, keith_outwater@mvis.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <virtex2.h>
#include <common.h>
#include <mpc8xx.h>
#include <asm/8xx_immap.h>
#include "beeper.h"
#include "fpga.h"
#include "ioport.h"

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_STATUS_LED
#include <status_led.h>
#endif

#if defined(CONFIG_CMD_MII) && defined(CONFIG_MII)
#include <net.h>
#endif

#if 0
#define GEN860T_DEBUG
#endif

#ifdef GEN860T_DEBUG
#define	PRINTF(fmt,args...)	printf (fmt ,##args)
#else
#define	PRINTF(fmt,args...)
#endif

/*
 * The following UPM init tables were generated automatically by
 * Motorola's MCUINIT program. See the README file for UPM to
 * SDRAM pin assignments if you want to type this data into
 * MCUINIT in order to reverse engineer the waveforms.
 */

/*
 * UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices
 * (UPMA) and Virtex FPGA SelectMap interface (UPMB).
 * NOTE that unused areas of the table are used to hold NOP, precharge
 * and mode register set sequences.
 *
 */
#define	UPMA_NOP_ADDR			0x5
#define	UPMA_PRECHARGE_ADDR		0x6
#define UPMA_MRS_ADDR			0x12

#define UPM_SINGLE_READ_ADDR	0x00
#define UPM_BURST_READ_ADDR		0x08
#define UPM_SINGLE_WRITE_ADDR	0x18
#define UPM_BURST_WRITE_ADDR	0x20
#define	UPM_REFRESH_ADDR		0x30

const uint sdram_upm_table[] = {
	/* single read   (offset 0x00 in upm ram) */
	0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05,
	0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff,
	/* burst read    (offset 0x08 in upm ram) */
	0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00,
	0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff,
	0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4,
	0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff,
	/* single write  (offset 0x18 in upm ram) */
	0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* burst write   (offset 0x20 in upm ram) */
	0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00,
	0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* refresh       (offset 0x30 in upm ram) */
	0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84,
	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* exception     (offset 0x3C in upm ram) */
};

const uint selectmap_upm_table[] = {
	/* single read   (offset 0x00 in upm ram) */
	0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00,
	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
	/* burst read    (offset 0x08 in upm ram) */
	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* single write  (offset 0x18 in upm ram) */
	0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* burst write   (offset 0x20 in upm ram) */
	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* refresh       (offset 0x30 in upm ram) */
	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	/* exception     (offset 0x3C in upm ram) */
	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff
};

/*
 * Check board identity.  Always successful (gives information only)
 */
int checkboard (void)
{
	char *s;
	char buf[64];
	int i;

	i = getenv_r ("board_id", buf, sizeof (buf));
	s = (i > 0) ? buf : NULL;

	if (s) {
		printf ("%s ", s);
	} else {
		printf ("<unknown> ");
	}

	i = getenv_r ("serial#", buf, sizeof (buf));
	s = (i > 0) ? buf : NULL;

	if (s) {
		printf ("S/N %s\n", s);
	} else {
		printf ("S/N <unknown>\n");
	}

	printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
	printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
	return (0);
}

/*
 * Initialize SDRAM
 */
phys_size_t initdram (int board_type)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;

	upmconfig (UPMA,
		   (uint *) sdram_upm_table,
		   sizeof (sdram_upm_table) / sizeof (uint)
		);

	/*
	 * Setup MAMR register
	 */
	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */

	/*
	 * Map CS1* to SDRAM bank
	 */
	memctl->memc_or1 = CONFIG_SYS_OR1;
	memctl->memc_br1 = CONFIG_SYS_BR1;

	/*
	 * Perform SDRAM initialization sequence:
	 * 1. Apply at least one NOP command
	 * 2. 100 uS delay (JEDEC standard says 200 uS)
	 * 3. Issue 4 precharge commands
	 * 4. Perform two refresh cycles
	 * 5. Program mode register
	 *
	 * Program SDRAM for standard operation, sequential burst, burst length
	 * of 4, CAS latency of 2.
	 */
	memctl->memc_mar = 0x00000000;
	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
		MCR_MLCF (0) | UPMA_NOP_ADDR;
	udelay (200);
	memctl->memc_mar = 0x00000000;
	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
		MCR_MLCF (4) | UPMA_PRECHARGE_ADDR;

	memctl->memc_mar = 0x00000000;
	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
		MCR_MLCF (2) | UPM_REFRESH_ADDR;

	memctl->memc_mar = 0x00000088;
	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
		MCR_MLCF (1) | UPMA_MRS_ADDR;

	memctl->memc_mar = 0x00000000;
	memctl->memc_mcr = MCR_UPM_A | MCR_OP_RUN | MCR_MB_CS1 |
		MCR_MLCF (0) | UPMA_NOP_ADDR;
	/*
	 * Enable refresh
	 */
	memctl->memc_mamr |= MAMR_PTAE;

	return (SDRAM_SIZE);
}

/*
 * Disk On Chip (DOC) Millenium initialization.
 * The DOC lives in the CS2* space
 */
#if defined(CONFIG_CMD_DOC)
void doc_init (void)
{
	printf ("Probing at 0x%.8x: ", DOC_BASE);
	doc_probe (DOC_BASE);
}
#endif

/*
 * Miscellaneous intialization
 */
int misc_init_r (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;

	/*
	 * Set up UPMB to handle the Virtex FPGA SelectMap interface
	 */
	upmconfig (UPMB, (uint *) selectmap_upm_table,
		   sizeof (selectmap_upm_table) / sizeof (uint));

	memctl->memc_mbmr = 0x0;

	config_mpc8xx_ioports (immr);

#if defined(CONFIG_CMD_MII)
	mii_init ();
#endif

#if defined(CONFIG_FPGA)
	gen860t_init_fpga ();
#endif
	return 0;
}

/*
 * Final init hook before entering command loop.
 */
int last_stage_init (void)
{
#if !defined(CONFIG_SC)
	char buf[256];
	int i;

	/*
	 * Turn the beeper volume all the way down in case this is a warm boot.
	 */
	set_beeper_volume (-64);
	init_beeper ();

	/*
	 * Read the environment to see what to do with the beeper
	 */
	i = getenv_r ("beeper", buf, sizeof (buf));
	if (i > 0) {
		do_beeper (buf);
	}
#endif
	return 0;
}

/*
 * Stub to make POST code happy.  Can't self-poweroff, so just hang.
 */
void board_poweroff (void)
{
	puts ("### Please power off the board ###\n");
	while (1);
}

#ifdef CONFIG_POST
/*
 * Returns 1 if keys pressed to start the power-on long-running tests
 * Called from board_init_f().
 */
int post_hotkeys_pressed (void)
{
	return 0;		/* No hotkeys supported */
}
#endif
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	* Keith Outwater, keith_outwater@mvis.com
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#include <virtex2.h>
	26	#include <common.h>
	27	#include <mpc8xx.h>
	28	#include <asm/8xx_immap.h>
	29	#include "beeper.h"
	30	#include "fpga.h"
	31	#include "ioport.h"
	32
d87080b7 WD	33	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	34
c609719b WD	35	#ifdef CONFIG_STATUS_LED
	36	#include <status_led.h>
	37	#endif
	38
77a31854	39	#if defined(CONFIG_CMD_MII) && defined(CONFIG_MII)
c609719b WD	40	#include <net.h>
	41	#endif
	42
	43	#if 0
	44	#define GEN860T_DEBUG
	45	#endif
	46
	47	#ifdef GEN860T_DEBUG
	48	#define PRINTF(fmt,args...) printf (fmt ,##args)
	49	#else
	50	#define PRINTF(fmt,args...)
	51	#endif
	52
	53	/*
	54	* The following UPM init tables were generated automatically by
	55	* Motorola's MCUINIT program. See the README file for UPM to
	56	* SDRAM pin assignments if you want to type this data into
	57	* MCUINIT in order to reverse engineer the waveforms.
	58	*/
	59
	60	/*
	61	* UPM initialization tables for MICRON MT48LC16M16A2TG SDRAM devices
	62	* (UPMA) and Virtex FPGA SelectMap interface (UPMB).
	63	* NOTE that unused areas of the table are used to hold NOP, precharge
	64	* and mode register set sequences.
	65	*
	66	*/
	67	#define UPMA_NOP_ADDR 0x5
	68	#define UPMA_PRECHARGE_ADDR 0x6
	69	#define UPMA_MRS_ADDR 0x12
	70
	71	#define UPM_SINGLE_READ_ADDR 0x00
	72	#define UPM_BURST_READ_ADDR 0x08
	73	#define UPM_SINGLE_WRITE_ADDR 0x18
	74	#define UPM_BURST_WRITE_ADDR 0x20
	75	#define UPM_REFRESH_ADDR 0x30
	76
	77	const uint sdram_upm_table[] = {
	78	/* single read (offset 0x00 in upm ram) */
	79	0x0e0fdc04, 0x01adfc04, 0x0fbffc00, 0x1fff5c05,
	80	0xffffffff, 0x0fffffcd, 0x0fff0fce, 0xefcfffff,
	81	/* burst read (offset 0x08 in upm ram) */
	82	0x0f0fdc04, 0x00fdfc04, 0xf0fffc00, 0xf0fffc00,
	83	0xf1fffc00, 0xfffffc00, 0xfffffc05, 0xffffffff,
	84	0xffffffff, 0xffffffff, 0x0ffffff4, 0x1f3d5ff4,
	85	0xfffffff4, 0xfffffff5, 0xffffffff, 0xffffffff,
	86	/* single write (offset 0x18 in upm ram) */
	87	0x0f0fdc04, 0x00ad3c00, 0x1fff5c05, 0xffffffff,
	88	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	89	/* burst write (offset 0x20 in upm ram) */
	90	0x0f0fdc00, 0x10fd7c00, 0xf0fffc00, 0xf0fffc00,
	91	0xf1fffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	92	0xffffffff, 0xffffffff, 0xffffffff, 0xfffff7ff,
	93	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	94	/* refresh (offset 0x30 in upm ram) */
	95	0x1ffddc84, 0xfffffc04, 0xfffffc04, 0xfffffc84,
	96	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
	97	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	98	/* exception (offset 0x3C in upm ram) */
bf9e3b38	99	};
c609719b WD	100
	101	const uint selectmap_upm_table[] = {
	102	/* single read (offset 0x00 in upm ram) */
	103	0x88fffc06, 0x00fff404, 0x00fffc04, 0x33fffc00,
	104	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff,
	105	/* burst read (offset 0x08 in upm ram) */
	106	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	107	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	108	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	109	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	110	/* single write (offset 0x18 in upm ram) */
	111	0x88fffc04, 0x00fff400, 0x77fffc05, 0xffffffff,
	112	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	113	/* burst write (offset 0x20 in upm ram) */
	114	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	115	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	116	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	117	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	118	/* refresh (offset 0x30 in upm ram) */
	119	0xfffffc04, 0xfffffc05, 0xffffffff, 0xffffffff,
	120	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	121	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	122	/* exception (offset 0x3C in upm ram) */
	123	0xfffffc05, 0xffffffff, 0xffffffff, 0xffffffff
	124	};
	125
	126	/*
	127	* Check board identity. Always successful (gives information only)
	128	*/
bf9e3b38	129	int checkboard (void)
c609719b	130	{
77ddac94 WD	131	char *s;
77ddac94 WD	132	char buf[64];
bf9e3b38	133	int i;
c609719b	134
bf9e3b38 WD	135	i = getenv_r ("board_id", buf, sizeof (buf));
bf9e3b38 WD	136	s = (i > 0) ? buf : NULL;
c609719b WD	137
c609719b WD	138	if (s) {
bf9e3b38	139	printf ("%s ", s);
c609719b	140	} else {
bf9e3b38	141	printf ("<unknown> ");
c609719b WD	142	}
c609719b WD	143
bf9e3b38 WD	144	i = getenv_r ("serial#", buf, sizeof (buf));
bf9e3b38 WD	145	s = (i > 0) ? buf : NULL;
c609719b WD	146
c609719b WD	147	if (s) {
bf9e3b38	148	printf ("S/N %s\n", s);
c609719b	149	} else {
bf9e3b38	150	printf ("S/N <unknown>\n");
c609719b WD	151	}
c609719b WD	152
bf9e3b38 WD	153	printf ("CPU at %s MHz, ", strmhz (buf, gd->cpu_clk));
	154	printf ("local bus at %s MHz\n", strmhz (buf, gd->bus_clk));
	155	return (0);
c609719b WD	156	}
	157
	158	/*
	159	* Initialize SDRAM
	160	*/
9973e3c6	161	phys_size_t initdram (int board_type)
c609719b	162	{
6d0f6bcf	163	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
bf9e3b38 WD	164	volatile memctl8xx_t *memctl = &immr->im_memctl;
	165
	166	upmconfig (UPMA,
	167	(uint *) sdram_upm_table,
	168	sizeof (sdram_upm_table) / sizeof (uint)
	169	);
	170
	171	/*
	172	* Setup MAMR register
	173	*/
6d0f6bcf JCPV	174	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
6d0f6bcf JCPV	175	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
bf9e3b38 WD	176
	177	/*
	178	* Map CS1* to SDRAM bank
	179	*/
6d0f6bcf JCPV	180	memctl->memc_or1 = CONFIG_SYS_OR1;
6d0f6bcf JCPV	181	memctl->memc_br1 = CONFIG_SYS_BR1;
c609719b WD	182
	183	/*
	184	* Perform SDRAM initialization sequence:
	185	* 1. Apply at least one NOP command
	186	* 2. 100 uS delay (JEDEC standard says 200 uS)
	187	* 3. Issue 4 precharge commands
	188	* 4. Perform two refresh cycles
	189	* 5. Program mode register
	190	*
	191	* Program SDRAM for standard operation, sequential burst, burst length
	192	* of 4, CAS latency of 2.
	193	*/
bf9e3b38	194	memctl->memc_mar = 0x00000000;
c609719b	195	memctl->memc_mcr = MCR_UPM_A \| MCR_OP_RUN \| MCR_MB_CS1 \|
bf9e3b38 WD	196	MCR_MLCF (0) \| UPMA_NOP_ADDR;
	197	udelay (200);
	198	memctl->memc_mar = 0x00000000;
c609719b	199	memctl->memc_mcr = MCR_UPM_A \| MCR_OP_RUN \| MCR_MB_CS1 \|
bf9e3b38	200	MCR_MLCF (4) \| UPMA_PRECHARGE_ADDR;
c609719b	201
bf9e3b38	202	memctl->memc_mar = 0x00000000;
c609719b	203	memctl->memc_mcr = MCR_UPM_A \| MCR_OP_RUN \| MCR_MB_CS1 \|
bf9e3b38	204	MCR_MLCF (2) \| UPM_REFRESH_ADDR;
c609719b	205
bf9e3b38	206	memctl->memc_mar = 0x00000088;
c609719b	207	memctl->memc_mcr = MCR_UPM_A \| MCR_OP_RUN \| MCR_MB_CS1 \|
bf9e3b38	208	MCR_MLCF (1) \| UPMA_MRS_ADDR;
c609719b	209
bf9e3b38	210	memctl->memc_mar = 0x00000000;
c609719b	211	memctl->memc_mcr = MCR_UPM_A \| MCR_OP_RUN \| MCR_MB_CS1 \|
bf9e3b38	212	MCR_MLCF (0) \| UPMA_NOP_ADDR;
c609719b WD	213	/*
	214	* Enable refresh
	215	*/
bf9e3b38	216	memctl->memc_mamr \|= MAMR_PTAE;
c609719b	217
bf9e3b38	218	return (SDRAM_SIZE);
c609719b WD	219	}
	220
	221	/*
	222	* Disk On Chip (DOC) Millenium initialization.
	223	* The DOC lives in the CS2* space
	224	*/
c508a4ce	225	#if defined(CONFIG_CMD_DOC)
bf9e3b38	226	void doc_init (void)
c609719b	227	{
bf9e3b38 WD	228	printf ("Probing at 0x%.8x: ", DOC_BASE);
bf9e3b38 WD	229	doc_probe (DOC_BASE);
c609719b WD	230	}
	231	#endif
	232
	233	/*
	234	* Miscellaneous intialization
	235	*/
bf9e3b38	236	int misc_init_r (void)
c609719b	237	{
6d0f6bcf	238	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
bf9e3b38	239	volatile memctl8xx_t *memctl = &immr->im_memctl;
c609719b WD	240
	241	/*
	242	* Set up UPMB to handle the Virtex FPGA SelectMap interface
	243	*/
bf9e3b38 WD	244	upmconfig (UPMB, (uint *) selectmap_upm_table,
bf9e3b38 WD	245	sizeof (selectmap_upm_table) / sizeof (uint));
c609719b	246
bf9e3b38	247	memctl->memc_mbmr = 0x0;
c609719b	248
bf9e3b38	249	config_mpc8xx_ioports (immr);
c609719b	250
c508a4ce	251	#if defined(CONFIG_CMD_MII)
bf9e3b38	252	mii_init ();
c609719b WD	253	#endif
c609719b WD	254
0133502e	255	#if defined(CONFIG_FPGA)
bf9e3b38	256	gen860t_init_fpga ();
c609719b WD	257	#endif
	258	return 0;
	259	}
	260
	261	/*
	262	* Final init hook before entering command loop.
	263	*/
bf9e3b38	264	int last_stage_init (void)
c609719b	265	{
7aa78614	266	#if !defined(CONFIG_SC)
77ddac94	267	char buf[256];
c609719b WD	268	int i;
	269
	270	/*
7aa78614	271	* Turn the beeper volume all the way down in case this is a warm boot.
c609719b	272	*/
bf9e3b38 WD	273	set_beeper_volume (-64);
bf9e3b38 WD	274	init_beeper ();
c609719b WD	275
	276	/*
	277	* Read the environment to see what to do with the beeper
	278	*/
bf9e3b38	279	i = getenv_r ("beeper", buf, sizeof (buf));
c609719b	280	if (i > 0) {
bf9e3b38	281	do_beeper (buf);
c609719b	282	}
7aa78614	283	#endif
c609719b WD	284	return 0;
c609719b WD	285	}
7aa78614 WD	286
	287	/*
	288	* Stub to make POST code happy. Can't self-poweroff, so just hang.
	289	*/
bf9e3b38	290	void board_poweroff (void)
7aa78614	291	{
bf9e3b38 WD	292	puts ("### Please power off the board ###\n");
bf9e3b38 WD	293	while (1);
7aa78614 WD	294	}
7aa78614 WD	295
8564acf9	296	#ifdef CONFIG_POST
945af8d7	297	/*
8564acf9 WD	298	* Returns 1 if keys pressed to start the power-on long-running tests
	299	* Called from board_init_f().
	300	*/
bf9e3b38	301	int post_hotkeys_pressed (void)
8564acf9	302	{
bf9e3b38	303	return 0; /* No hotkeys supported */
8564acf9 WD	304	}
8564acf9 WD	305	#endif