[people/ms/u-boot.git] / board / genesi / mx51_efikamx / imximage_sb.cfg

/*
 * Copyright (C) 2009 Pegatron Corporation
 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
 * Copyright (C) 2009-2012 Genesi USA, Inc.
 *
 * BASED ON: imx51evk
 *
 * (C) Copyright 2009
 * Stefano Babic DENX Software Engineering sbabic@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Boot Device : one of
 * spi, sd (the board has no nand neither onenand)
 */
BOOT_FROM	spi

/*
 * Device Configuration Data (DCD)
 *
 * Each entry must have the format:
 * Addr-type           Address        Value
 *
 * where:
 *	Addr-type register length (1,2 or 4 bytes)
 *	Address	  absolute address of the register
 *	value	  value to be stored in the register
*/
/* DDR bus IOMUX PAD settings */
DATA 4 0x73fa88a0 0x200		# GRP_INMODE1
DATA 4 0x73fa850c 0x20c5	# SDODT1
DATA 4 0x73fa8510 0x20c5	# SDODT0
DATA 4 0x73fa8848 0x4		# DDR_A1
DATA 4 0x73fa84b8 0xe7		# DRAM_SDCLK
DATA 4 0x73fa84bc 0x45		# DRAM_SDQS0
DATA 4 0x73fa84c0 0x45		# DRAM_SDQS1
DATA 4 0x73fa84c4 0x45		# DRAM_SDQS2
DATA 4 0x73fa84c8 0x45		# DRAM_SDQS3
DATA 4 0x73fa8820 0x0		# DDRPKS
DATA 4 0x73fa84ac 0xe5		# SDWE
DATA 4 0x73fa84b0 0xe5		# SDCKE0
DATA 4 0x73fa84b4 0xe5		# SDCKE1
DATA 4 0x73fa84cc 0xe5		# DRAM_CS0
DATA 4 0x73fa84d0 0xe4		# DRAM_CS1

/*
 * Setting DDR for micron
 * 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
 * CAS=3 BL=4
 */
/* ESDCTL_ESDCTL0 */
DATA 4 0x83fd9000 0x82a20000
/* ESDCTL_ESDCTL1 */
DATA 4 0x83fd9008 0x82a20000
/* ESDCTL_ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
/* ESDCTL_ESDCFG0 */
DATA 4 0x83fd9004 0x333574aa
/* ESDCTL_ESDCFG1 */
DATA 4 0x83fd900c 0x333574aa

/* Init DRAM on CS0 */
/* ESDCTL_ESDSCR */
DATA 4 0x83fd9014 0x04008008
DATA 4 0x83fd9014 0x0000801a
DATA 4 0x83fd9014 0x0000801b
DATA 4 0x83fd9014 0x00448019
DATA 4 0x83fd9014 0x07328018
DATA 4 0x83fd9014 0x04008008
DATA 4 0x83fd9014 0x00008010
DATA 4 0x83fd9014 0x00008010
DATA 4 0x83fd9014 0x06328018
DATA 4 0x83fd9014 0x03808019
DATA 4 0x83fd9014 0x00408019
DATA 4 0x83fd9014 0x00008000

/* Init DRAM on CS1 */
DATA 4 0x83fd9014 0x0400800c
DATA 4 0x83fd9014 0x0000801e
DATA 4 0x83fd9014 0x0000801f
DATA 4 0x83fd9014 0x0000801d
DATA 4 0x83fd9014 0x0732801c
DATA 4 0x83fd9014 0x0400800c
DATA 4 0x83fd9014 0x00008014
DATA 4 0x83fd9014 0x00008014
DATA 4 0x83fd9014 0x0632801c
DATA 4 0x83fd9014 0x0380801d
DATA 4 0x83fd9014 0x0042801d
DATA 4 0x83fd9014 0x00008004

/* Write to CTL0 */
DATA 4 0x83fd9000 0xb2a20000
/* Write to CTL1 */
DATA 4 0x83fd9008 0xb2a20000
/* ESDMISC */
DATA 4 0x83fd9010 0xcaaaf6d0
/* ESDCTL_ESDCDLYGD */
DATA 4 0x83fd9034 0x90000000
DATA 4 0x83fd9014 0x00000000
Commit	Line	Data
71a988aa TK	1	/*
	2	* Copyright (C) 2009 Pegatron Corporation
	3	* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
	4	* Copyright (C) 2009-2012 Genesi USA, Inc.
	5	*
	6	* BASED ON: imx51evk
	7	*
	8	* (C) Copyright 2009
	9	* Stefano Babic DENX Software Engineering sbabic@denx.de.
	10	*
1a459660	11	* SPDX-License-Identifier: GPL-2.0+
71a988aa	12	*/
d5914017	13
71a988aa TK	14	/*
	15	* Boot Device : one of
	16	* spi, sd (the board has no nand neither onenand)
	17	*/
d5914017 MV	18	BOOT_FROM spi
d5914017 MV	19
71a988aa TK	20	/*
	21	* Device Configuration Data (DCD)
	22	*
	23	* Each entry must have the format:
	24	* Addr-type Address Value
	25	*
	26	* where:
	27	* Addr-type register length (1,2 or 4 bytes)
	28	* Address absolute address of the register
	29	* value value to be stored in the register
	30	*/
	31	/* DDR bus IOMUX PAD settings */
10e2178b MS	32	DATA 4 0x73fa88a0 0x200 # GRP_INMODE1
	33	DATA 4 0x73fa850c 0x20c5 # SDODT1
	34	DATA 4 0x73fa8510 0x20c5 # SDODT0
	35	DATA 4 0x73fa8848 0x4 # DDR_A1
	36	DATA 4 0x73fa84b8 0xe7 # DRAM_SDCLK
	37	DATA 4 0x73fa84bc 0x45 # DRAM_SDQS0
	38	DATA 4 0x73fa84c0 0x45 # DRAM_SDQS1
	39	DATA 4 0x73fa84c4 0x45 # DRAM_SDQS2
	40	DATA 4 0x73fa84c8 0x45 # DRAM_SDQS3
	41	DATA 4 0x73fa8820 0x0 # DDRPKS
	42	DATA 4 0x73fa84ac 0xe5 # SDWE
	43	DATA 4 0x73fa84b0 0xe5 # SDCKE0
	44	DATA 4 0x73fa84b4 0xe5 # SDCKE1
	45	DATA 4 0x73fa84cc 0xe5 # DRAM_CS0
	46	DATA 4 0x73fa84d0 0xe4 # DRAM_CS1
d5914017	47
71a988aa TK	48	/*
	49	* Setting DDR for micron
	50	* 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model
	51	* CAS=3 BL=4
	52	*/
	53	/* ESDCTL_ESDCTL0 */
d5914017	54	DATA 4 0x83fd9000 0x82a20000
71a988aa	55	/* ESDCTL_ESDCTL1 */
d5914017	56	DATA 4 0x83fd9008 0x82a20000
71a988aa	57	/* ESDCTL_ESDMISC */
d5914017	58	DATA 4 0x83fd9010 0xcaaaf6d0
71a988aa	59	/* ESDCTL_ESDCFG0 */
0ef4fc53	60	DATA 4 0x83fd9004 0x333574aa
71a988aa	61	/* ESDCTL_ESDCFG1 */
0ef4fc53	62	DATA 4 0x83fd900c 0x333574aa
d5914017	63
71a988aa TK	64	/* Init DRAM on CS0 */
71a988aa TK	65	/* ESDCTL_ESDSCR */
d5914017 MV	66	DATA 4 0x83fd9014 0x04008008
	67	DATA 4 0x83fd9014 0x0000801a
	68	DATA 4 0x83fd9014 0x0000801b
	69	DATA 4 0x83fd9014 0x00448019
	70	DATA 4 0x83fd9014 0x07328018
	71	DATA 4 0x83fd9014 0x04008008
	72	DATA 4 0x83fd9014 0x00008010
	73	DATA 4 0x83fd9014 0x00008010
	74	DATA 4 0x83fd9014 0x06328018
	75	DATA 4 0x83fd9014 0x03808019
	76	DATA 4 0x83fd9014 0x00408019
	77	DATA 4 0x83fd9014 0x00008000
	78
71a988aa	79	/* Init DRAM on CS1 */
d5914017 MV	80	DATA 4 0x83fd9014 0x0400800c
	81	DATA 4 0x83fd9014 0x0000801e
	82	DATA 4 0x83fd9014 0x0000801f
	83	DATA 4 0x83fd9014 0x0000801d
	84	DATA 4 0x83fd9014 0x0732801c
	85	DATA 4 0x83fd9014 0x0400800c
	86	DATA 4 0x83fd9014 0x00008014
	87	DATA 4 0x83fd9014 0x00008014
	88	DATA 4 0x83fd9014 0x0632801c
	89	DATA 4 0x83fd9014 0x0380801d
10e2178b	90	DATA 4 0x83fd9014 0x0042801d
d5914017 MV	91	DATA 4 0x83fd9014 0x00008004
d5914017 MV	92
71a988aa	93	/* Write to CTL0 */
d5914017	94	DATA 4 0x83fd9000 0xb2a20000
71a988aa	95	/* Write to CTL1 */
d5914017	96	DATA 4 0x83fd9008 0xb2a20000
71a988aa	97	/* ESDMISC */
0ef4fc53	98	DATA 4 0x83fd9010 0xcaaaf6d0
71a988aa	99	/* ESDCTL_ESDCDLYGD */
d5914017 MV	100	DATA 4 0x83fd9034 0x90000000
d5914017 MV	101	DATA 4 0x83fd9014 0x00000000