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16f21704 WD |
1 | /* |
2 | * (C) Copyright 2000 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * Adapted from FADS and other board config files to GTH by thomas@corelatus.com | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <common.h> | |
27 | #include <config.h> | |
28 | #include <watchdog.h> | |
29 | #include <mpc8xx.h> | |
30 | #include "ee_access.h" | |
31 | #include "ee_dev.h" | |
32 | ||
33 | #ifdef CONFIG_BDM | |
34 | #undef printf | |
35 | #define printf(a,...) /* nothing */ | |
36 | #endif | |
37 | ||
38 | ||
39 | int checkboard (void) | |
40 | { | |
6d0f6bcf | 41 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
16f21704 WD |
42 | int Id = 0; |
43 | int Rev = 0; | |
44 | u32 Pbdat; | |
45 | ||
46 | puts ("Board: "); | |
47 | ||
48 | /* Turn on leds and setup for reading rev and id */ | |
49 | ||
50 | #define PB_OUTS (PB_BLUE_LED|PB_ID_GND) | |
51 | #define PB_INS (PB_ID_0|PB_ID_1|PB_ID_2|PB_ID_3|PB_REV_1|PB_REV_0) | |
52 | ||
53 | immap->im_cpm.cp_pbpar &= ~(PB_OUTS | PB_INS); | |
54 | ||
55 | immap->im_cpm.cp_pbdir &= ~PB_INS; | |
56 | ||
57 | immap->im_cpm.cp_pbdir |= PB_OUTS; | |
58 | immap->im_cpm.cp_pbodr |= PB_OUTS; | |
59 | immap->im_cpm.cp_pbdat &= ~PB_OUTS; | |
60 | ||
61 | /* Hold 100 Mbit in reset until fpga is loaded */ | |
62 | immap->im_ioport.iop_pcpar &= ~PC_ENET100_RESET; | |
63 | immap->im_ioport.iop_pcdir |= PC_ENET100_RESET; | |
64 | immap->im_ioport.iop_pcso &= ~PC_ENET100_RESET; | |
65 | immap->im_ioport.iop_pcdat &= ~PC_ENET100_RESET; | |
66 | ||
67 | /* Turn on front led to show that we are alive */ | |
68 | immap->im_ioport.iop_papar &= ~PA_FRONT_LED; | |
69 | immap->im_ioport.iop_padir |= PA_FRONT_LED; | |
70 | immap->im_ioport.iop_paodr |= PA_FRONT_LED; | |
71 | immap->im_ioport.iop_padat &= ~PA_FRONT_LED; | |
72 | ||
73 | Pbdat = immap->im_cpm.cp_pbdat; | |
74 | ||
75 | if (!(Pbdat & PB_ID_0)) | |
76 | Id += 1; | |
77 | if (!(Pbdat & PB_ID_1)) | |
78 | Id += 2; | |
79 | if (!(Pbdat & PB_ID_2)) | |
80 | Id += 4; | |
81 | if (!(Pbdat & PB_ID_3)) | |
82 | Id += 8; | |
83 | ||
84 | if (Pbdat & PB_REV_0) | |
85 | Rev += 1; | |
86 | if (Pbdat & PB_REV_1) | |
87 | Rev += 2; | |
88 | ||
89 | /* Turn ID off since we dont need it anymore */ | |
90 | immap->im_cpm.cp_pbdat |= PB_ID_GND; | |
91 | ||
92 | printf ("GTH board, rev %d, id=0x%01x\n", Rev, Id); | |
93 | return 0; | |
94 | } | |
95 | ||
96 | #define _NOT_USED_ 0xffffffff | |
97 | const uint sdram_table[] = { | |
98 | /* Single read, offset 0 */ | |
99 | 0x0f3dfc04, 0x0eefbc04, 0x01bf7c04, 0x0feafc00, | |
100 | 0x1fb5fc45, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
101 | ||
102 | /* Burst read, Offset 0x8, 4 reads */ | |
103 | 0x0f3dfc04, 0x0eefbc04, 0x00bf7c04, 0x00ffec00, | |
104 | 0x00fffc00, 0x01eafc00, 0x1fb5fc00, 0xfffffc45, | |
105 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
106 | ||
107 | /* Not used part of burst read is used for MRS, Offset 0x14 */ | |
108 | 0xefeabc34, 0x1fb57c34, 0xfffffc05, _NOT_USED_, | |
109 | /* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */ | |
110 | ||
111 | /* Single write, Offset 0x18 */ | |
112 | 0x0f3dfc04, 0x0eebbc00, 0x01a27c04, 0x1fb5fc45, | |
113 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
114 | ||
115 | /* Burst write, Offset 0x20. 4 writes */ | |
116 | 0x0f3dfc04, 0x0eebbc00, 0x00b77c00, 0x00fffc00, | |
117 | 0x00fffc00, 0x01eafc04, 0x1fb5fc45, _NOT_USED_, | |
118 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
119 | ||
120 | /* Not used part of burst write is used for precharge, Offset 0x2C */ | |
121 | 0x0ff5fc04, 0xfffffc05, _NOT_USED_, _NOT_USED_, | |
122 | /* _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, */ | |
123 | ||
124 | /* Period timer service. Offset 0x30. Refresh. Wait at least 70 ns after refresh command */ | |
125 | 0x1ffd7c04, 0xfffffc04, 0xfffffc04, 0xfffffc05, | |
126 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
127 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
128 | ||
129 | /* Exception, Offset 0x3C */ | |
130 | 0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_ | |
131 | }; | |
132 | ||
133 | const uint fpga_table[] = { | |
134 | /* Single read, offset 0 */ | |
135 | 0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04, | |
136 | 0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05, | |
137 | ||
138 | /* Burst read, Offset 0x8 */ | |
139 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
140 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
141 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
142 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
143 | ||
144 | /* Single write, Offset 0x18 */ | |
145 | 0x0cffec04, 0x00ffec04, 0x00ffec04, 0x00ffec04, | |
146 | 0x00fffc04, 0x00fffc00, 0x00ffec04, 0xffffec05, | |
147 | ||
148 | /* Burst write, Offset 0x20. */ | |
149 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
150 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
151 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
152 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
153 | ||
154 | /* Period timer service. Offset 0x30. */ | |
155 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
156 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
157 | _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, | |
158 | ||
159 | /* Exception, Offset 0x3C */ | |
160 | 0xfffffc04, 0xfffffc05, _NOT_USED_, _NOT_USED_ | |
161 | }; | |
162 | ||
163 | int _initsdram (uint base, uint * noMbytes) | |
164 | { | |
6d0f6bcf | 165 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
16f21704 WD |
166 | volatile memctl8xx_t *mc = &immap->im_memctl; |
167 | volatile u32 *memptr; | |
168 | ||
169 | mc->memc_mptpr = MPTPR_PTP_DIV16; /* (16-17) */ | |
170 | ||
171 | /* SDRAM in UPMA | |
172 | ||
173 | GPL_0 is connected instead of A19 to SDRAM. | |
174 | According to table 16-17, AMx should be 001, i.e. type 1 | |
175 | and GPL_0 should hold address A10 when multiplexing */ | |
176 | ||
177 | mc->memc_mamr = (0x2E << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_AMA_TYPE_1 | MAMR_G0CLA_A10 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X; /* (16-13) */ | |
178 | ||
179 | upmconfig (UPMA, (uint *) sdram_table, | |
180 | sizeof (sdram_table) / sizeof (uint)); | |
181 | ||
182 | /* Perform init of sdram ( Datasheet Page 9 ) | |
183 | Precharge */ | |
184 | mc->memc_mcr = 0x8000212C; /* run upm a at 0x2C (16-15) */ | |
185 | ||
186 | /* Run 2 refresh cycles */ | |
187 | mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */ | |
188 | mc->memc_mcr = 0x80002130; /* run upm a at 0x30 (16-15) */ | |
189 | ||
190 | /* Set Mode register */ | |
191 | mc->memc_mar = 0x00000088; /* set mode register (address) to 0x022 (16-17) */ | |
192 | /* Lower 2 bits are not connected to chip */ | |
193 | mc->memc_mcr = 0x80002114; /* run upm a at 0x14 (16-15) */ | |
194 | ||
195 | /* CS1, base 0x0000000 - 64 Mbyte, use UPM A */ | |
196 | mc->memc_or1 = 0xfc000000 | OR_CSNT_SAM; | |
197 | mc->memc_br1 = BR_MS_UPMA | BR_V; /* SDRAM base always 0 */ | |
198 | ||
199 | /* Test if we really have 64 MB SDRAM */ | |
200 | memptr = (u32 *) 0; | |
201 | *memptr = 0; | |
202 | ||
203 | memptr = (u32 *) 0x2000000; /* First u32 in upper 32 MB */ | |
204 | *memptr = 0x12345678; | |
205 | ||
206 | memptr = (u32 *) 0; | |
207 | if (*memptr == 0x12345678) { | |
208 | /* Wrapped, only have 32 MB */ | |
209 | mc->memc_or1 = 0xfe000000 | OR_CSNT_SAM; | |
210 | *noMbytes = 32; | |
211 | } else { | |
212 | /* 64 MB */ | |
213 | *noMbytes = 64; | |
214 | } | |
215 | ||
216 | /* Setup FPGA in UPMB */ | |
217 | upmconfig (UPMB, (uint *) fpga_table, | |
218 | sizeof (fpga_table) / sizeof (uint)); | |
219 | ||
220 | /* Enable UPWAITB */ | |
2535d602 | 221 | mc->memc_mbmr = MBMR_GPL_B4DIS; /* (16-13) */ |
16f21704 WD |
222 | |
223 | /* CS2, base FPGA_2_BASE - 4 MByte, use UPM B 32 Bit */ | |
224 | mc->memc_or2 = 0xffc00000 | OR_BI; | |
225 | mc->memc_br2 = FPGA_2_BASE | BR_MS_UPMB | BR_V; | |
226 | ||
227 | /* CS3, base FPGA_3_BASE - 4 MByte, use UPM B 16 bit */ | |
228 | mc->memc_or3 = 0xffc00000 | OR_BI; | |
229 | mc->memc_br3 = FPGA_3_BASE | BR_MS_UPMB | BR_V | BR_PS_16; | |
230 | ||
231 | return 0; | |
232 | } | |
233 | ||
234 | /* ------------------------------------------------------------------------- */ | |
235 | ||
236 | void _sdramdisable (void) | |
237 | { | |
6d0f6bcf | 238 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
16f21704 WD |
239 | volatile memctl8xx_t *memctl = &immap->im_memctl; |
240 | ||
241 | memctl->memc_br1 = 0x00000000; | |
242 | ||
243 | /* maybe we should turn off upmb here or something */ | |
244 | } | |
245 | ||
246 | /* ------------------------------------------------------------------------- */ | |
247 | ||
248 | int initsdram (uint base, uint * noMbytes) | |
249 | { | |
250 | *noMbytes = 32; | |
251 | ||
252 | #ifdef CONFIG_START_IN_RAM | |
253 | /* SDRAM is already setup. Dont touch it */ | |
254 | return 0; | |
255 | #else | |
256 | ||
257 | if (!_initsdram (base, noMbytes)) { | |
258 | ||
259 | return 0; | |
260 | } else { | |
261 | _sdramdisable (); | |
262 | ||
263 | return -1; | |
264 | } | |
265 | #endif | |
266 | } | |
267 | ||
9973e3c6 | 268 | phys_size_t initdram (int board_type) |
16f21704 WD |
269 | { |
270 | u32 *i; | |
271 | u32 j; | |
272 | u32 k; | |
273 | ||
274 | /* GTH only have SDRAM */ | |
275 | uint sdramsz; | |
276 | ||
277 | if (!initsdram (0x00000000, &sdramsz)) { | |
278 | printf ("(%u MB SDRAM) ", sdramsz); | |
279 | } else { | |
280 | /******************************** | |
281 | *SDRAM ERROR, HALT PROCESSOR | |
282 | *********************************/ | |
283 | printf ("SDRAM ERROR\n"); | |
284 | while (1); | |
285 | } | |
286 | ||
287 | #ifndef CONFIG_START_IN_RAM | |
288 | ||
289 | #define U32_S ((sdramsz<<18)-1) | |
290 | ||
291 | #if 1 | |
292 | /* Do a simple memory test */ | |
293 | for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) { | |
294 | *i = j + (j << 17); | |
295 | *(i + 1) = ~(j + (j << 18)); | |
296 | } | |
297 | ||
298 | WATCHDOG_RESET (); | |
299 | ||
300 | printf ("."); | |
301 | ||
302 | for (i = (u32 *) 0, j = 0; (u32) i < U32_S; i += 2, j += 2) { | |
303 | k = *i; | |
304 | if (k != (j + (j << 17))) { | |
305 | printf ("Mem test error, i=0x%x, 0x%x\n, 0x%x", (u32) i, j, k); | |
306 | while (1); | |
307 | } | |
308 | k = *(i + 1); | |
309 | if (k != ~(j + (j << 18))) { | |
310 | printf ("Mem test error(+1), i=0x%x, 0x%x\n, 0x%x", | |
311 | (u32) i + 1, j, k); | |
312 | while (1); | |
313 | } | |
314 | } | |
315 | #endif | |
316 | ||
317 | WATCHDOG_RESET (); | |
318 | ||
319 | /* Clear memory */ | |
320 | for (i = (u32 *) 0; (u32) i < U32_S; i++) { | |
321 | *i = 0; | |
322 | } | |
323 | #endif /* !start in ram */ | |
324 | ||
325 | WATCHDOG_RESET (); | |
326 | ||
327 | return (sdramsz << 20); | |
328 | } | |
329 | ||
330 | #define POWER_OFFSET 0xF0000 | |
331 | #define SW_WATCHDOG_REASON 13 | |
332 | ||
333 | #define BOOTDATA_OFFSET 0xF8000 | |
334 | #define MAX_ATTEMPTS 5 | |
335 | ||
336 | #define FAILSAFE_BOOT 1 | |
337 | #define SYSTEM_BOOT 2 | |
338 | ||
339 | #define WRITE_FLASH16(a, d) \ | |
340 | do \ | |
341 | { \ | |
342 | *((volatile u16 *) (a)) = (d);\ | |
343 | } while(0) | |
344 | ||
345 | static void write_bootdata (volatile u16 * addr, u8 System, u8 Count) | |
346 | { | |
347 | u16 data; | |
6d0f6bcf | 348 | volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE); |
16f21704 WD |
349 | |
350 | if ((System != FAILSAFE_BOOT) & (System != SYSTEM_BOOT)) { | |
351 | printf ("Invalid system data %u, setting failsafe\n", System); | |
352 | System = FAILSAFE_BOOT; | |
353 | } | |
354 | ||
355 | if ((Count < 1) | (Count > MAX_ATTEMPTS)) { | |
356 | printf ("Invalid boot count %u, setting 1\n", Count); | |
357 | Count = 1; | |
358 | } | |
359 | ||
360 | if (System == FAILSAFE_BOOT) { | |
361 | printf ("Setting failsafe boot in flash\n"); | |
362 | } else { | |
363 | printf ("Setting system boot in flash\n"); | |
364 | } | |
365 | printf ("Boot attempt %d\n", Count); | |
366 | ||
367 | data = (System << 8) | Count; | |
368 | /* AMD 16 bit */ | |
369 | WRITE_FLASH16 (&flash[0x555], 0xAAAA); | |
370 | WRITE_FLASH16 (&flash[0x2AA], 0x5555); | |
371 | WRITE_FLASH16 (&flash[0x555], 0xA0A0); | |
372 | ||
373 | WRITE_FLASH16 (addr, data); | |
374 | } | |
375 | ||
376 | static void maybe_update_restart_reason (volatile u32 * addr32) | |
377 | { | |
378 | /* Update addr if sw wd restart */ | |
6d0f6bcf | 379 | volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE); |
16f21704 WD |
380 | volatile u16 *addr_16 = (u16 *) addr32; |
381 | u32 rsr; | |
382 | ||
383 | /* Dont reset register now */ | |
6d0f6bcf | 384 | rsr = ((volatile immap_t *) CONFIG_SYS_IMMR)->im_clkrst.car_rsr; |
16f21704 WD |
385 | |
386 | rsr >>= 24; | |
387 | ||
388 | if (rsr & 0x10) { | |
389 | /* Was really a sw wd restart, update reason */ | |
390 | ||
391 | printf ("Last restart by software watchdog\n"); | |
392 | ||
393 | /* AMD 16 bit */ | |
394 | WRITE_FLASH16 (&flash[0x555], 0xAAAA); | |
395 | WRITE_FLASH16 (&flash[0x2AA], 0x5555); | |
396 | WRITE_FLASH16 (&flash[0x555], 0xA0A0); | |
397 | ||
398 | WRITE_FLASH16 (addr_16, 0); | |
399 | ||
400 | udelay (1000); | |
401 | ||
402 | WATCHDOG_RESET (); | |
403 | ||
404 | /* AMD 16 bit */ | |
405 | WRITE_FLASH16 (&flash[0x555], 0xAAAA); | |
406 | WRITE_FLASH16 (&flash[0x2AA], 0x5555); | |
407 | WRITE_FLASH16 (&flash[0x555], 0xA0A0); | |
408 | ||
409 | WRITE_FLASH16 (addr_16 + 1, SW_WATCHDOG_REASON); | |
410 | ||
411 | } | |
412 | } | |
413 | ||
414 | static void check_restart_reason (void) | |
415 | { | |
416 | /* Update restart reason if sw watchdog was | |
417 | triggered */ | |
418 | ||
419 | int i; | |
420 | volatile u32 *raddr; | |
421 | ||
6d0f6bcf | 422 | raddr = (u32 *) (CONFIG_SYS_FLASH_BASE + POWER_OFFSET); |
16f21704 WD |
423 | |
424 | if (*raddr == 0xFFFFFFFF) { | |
425 | /* Nothing written */ | |
426 | maybe_update_restart_reason (raddr); | |
427 | } else { | |
428 | /* Search for latest written reason */ | |
429 | i = 0; | |
430 | while ((*(raddr + 2) != 0xFFFFFFFF) & (i < 2000)) { | |
431 | raddr += 2; | |
432 | i++; | |
433 | } | |
434 | if (i >= 2000) { | |
435 | /* Whoa, dont write any more */ | |
436 | printf ("*** No free restart reason found ***\n"); | |
437 | } else { | |
438 | /* Check if written */ | |
439 | if (*raddr == 0) { | |
440 | /* Erased by kernel, no new reason written */ | |
441 | maybe_update_restart_reason (raddr + 2); | |
442 | } | |
443 | } | |
444 | } | |
445 | } | |
446 | ||
447 | static void check_boot_tries (void) | |
448 | { | |
449 | /* Count the number of boot attemps | |
450 | switch system if too many */ | |
451 | ||
452 | int i; | |
453 | volatile u16 *addr; | |
454 | volatile u16 data; | |
455 | int failsafe = 1; | |
456 | u8 system; | |
457 | u8 count; | |
458 | ||
6d0f6bcf | 459 | addr = (u16 *) (CONFIG_SYS_FLASH_BASE + BOOTDATA_OFFSET); |
16f21704 WD |
460 | |
461 | if (*addr == 0xFFFF) { | |
462 | printf ("*** No bootdata exists. ***\n"); | |
463 | write_bootdata (addr, FAILSAFE_BOOT, 1); | |
464 | } else { | |
465 | /* Search for latest written bootdata */ | |
466 | i = 0; | |
467 | while ((*(addr + 1) != 0xFFFF) & (i < 8000)) { | |
468 | addr++; | |
469 | i++; | |
470 | } | |
471 | if (i >= 8000) { | |
472 | /* Whoa, dont write any more */ | |
473 | printf ("*** No bootdata found. Not updating flash***\n"); | |
474 | } else { | |
475 | /* See how many times we have tried to boot real system */ | |
476 | data = *addr; | |
477 | system = data >> 8; | |
478 | count = data & 0xFF; | |
479 | if ((system != SYSTEM_BOOT) & (system != FAILSAFE_BOOT)) { | |
480 | printf ("*** Wrong system %d\n", system); | |
481 | system = FAILSAFE_BOOT; | |
482 | count = 1; | |
483 | } else { | |
484 | switch (count) { | |
485 | case 0: | |
486 | case 1: | |
487 | case 2: | |
488 | case 3: | |
489 | case 4: | |
490 | /* Try same system again if needed */ | |
491 | count++; | |
492 | break; | |
493 | ||
494 | case 5: | |
495 | /* Switch system and reset tries */ | |
496 | count = 1; | |
497 | system = 3 - system; | |
498 | printf ("***Too many boot attempts, switching system***\n"); | |
499 | break; | |
500 | default: | |
501 | /* Switch system, start over and hope it works */ | |
502 | printf ("***Unexpected data on addr 0x%x, %u***\n", | |
503 | (u32) addr, data); | |
504 | count = 1; | |
505 | system = 3 - system; | |
506 | } | |
507 | } | |
508 | write_bootdata (addr + 1, system, count); | |
509 | if (system == SYSTEM_BOOT) { | |
510 | failsafe = 0; | |
511 | } | |
512 | } | |
513 | } | |
514 | if (failsafe) { | |
515 | printf ("Booting failsafe system\n"); | |
516 | setenv ("bootargs", "panic=1 root=/dev/hda7"); | |
517 | setenv ("bootcmd", "disk 100000 0:5;bootm 100000"); | |
518 | } else { | |
519 | printf ("Using normal system\n"); | |
520 | setenv ("bootargs", "panic=1 root=/dev/hda4"); | |
521 | setenv ("bootcmd", "disk 100000 0:2;bootm 100000"); | |
522 | } | |
523 | } | |
524 | ||
525 | int misc_init_r (void) | |
526 | { | |
527 | u8 Rx[80]; | |
528 | u8 Tx[5]; | |
529 | int page; | |
530 | int read = 0; | |
6d0f6bcf | 531 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
16f21704 WD |
532 | |
533 | /* Kill fpga */ | |
534 | immap->im_ioport.iop_papar &= ~(PA_FL_CONFIG | PA_FL_CE); | |
535 | immap->im_ioport.iop_padir |= (PA_FL_CONFIG | PA_FL_CE); | |
536 | immap->im_ioport.iop_paodr &= ~(PA_FL_CONFIG | PA_FL_CE); | |
537 | ||
538 | /* Enable fpga, active low */ | |
539 | immap->im_ioport.iop_padat &= ~PA_FL_CE; | |
540 | ||
541 | /* Start configuration */ | |
542 | immap->im_ioport.iop_padat &= ~PA_FL_CONFIG; | |
543 | udelay (2); | |
544 | ||
545 | immap->im_ioport.iop_padat |= (PA_FL_CONFIG | PA_FL_CE); | |
546 | ||
547 | /* Check if we need to boot failsafe system */ | |
548 | check_boot_tries (); | |
549 | ||
550 | /* Check if we need to update restart reason */ | |
551 | check_restart_reason (); | |
552 | ||
553 | if (ee_init_data ()) { | |
554 | printf ("EEPROM init failed\n"); | |
555 | return (0); | |
556 | } | |
557 | ||
558 | /* Read the pages where ethernet address is stored */ | |
559 | ||
560 | for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) { | |
561 | /* Copy from nvram to scratchpad */ | |
562 | Tx[0] = RECALL_MEMORY; | |
563 | Tx[1] = page; | |
564 | if (ee_do_command (Tx, 2, NULL, 0, TRUE)) { | |
565 | printf ("EE user page %d recall failed\n", page); | |
566 | return (0); | |
567 | } | |
568 | ||
569 | Tx[0] = READ_SCRATCHPAD; | |
570 | if (ee_do_command (Tx, 2, Rx + read, 9, TRUE)) { | |
571 | printf ("EE user page %d read failed\n", page); | |
572 | return (0); | |
573 | } | |
574 | /* Crc in 9:th byte */ | |
575 | if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) { | |
576 | printf ("EE read failed, page %d. CRC error\n", page); | |
577 | return (0); | |
578 | } | |
579 | read += 8; | |
580 | } | |
581 | ||
582 | /* Add eos after eth addr */ | |
583 | Rx[17] = 0; | |
584 | ||
585 | printf ("Ethernet addr read from eeprom: %s\n\n", Rx); | |
586 | ||
587 | if ((Rx[2] != ':') | | |
588 | (Rx[5] != ':') | | |
589 | (Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) { | |
590 | printf ("*** ethernet addr invalid, using default ***\n"); | |
591 | } else { | |
77ddac94 | 592 | setenv ("ethaddr", (char *)Rx); |
16f21704 WD |
593 | } |
594 | return (0); | |
595 | } |