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Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet""
[thirdparty/u-boot.git] / board / highbank / highbank.c
CommitLineData
83d290c5 1// SPDX-License-Identifier: GPL-2.0+
37fc0ed2
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2/*
3 * Copyright 2010-2011 Calxeda, Inc.
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4 */
5
d678a59d 6#include <common.h>
37fc0ed2 7#include <ahci.h>
9edefc27 8#include <cpu_func.h>
9fb625ce 9#include <env.h>
4d72caa5 10#include <fdt_support.h>
1238d014 11#include <fdtdec.h>
691d719d 12#include <init.h>
90526e9f 13#include <net.h>
37fc0ed2 14#include <scsi.h>
401d1c4f 15#include <asm/global_data.h>
37fc0ed2 16
1ace4022 17#include <linux/sizes.h>
877012df 18#include <asm/io.h>
37fc0ed2 19
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20#define HB_AHCI_BASE 0xffe08000
21
083ffd65 22#define HB_SCU_A9_PWR_STATUS 0xfff10008
0c34e69f 23#define HB_SREG_A9_PWR_REQ 0xfff3cf00
4a3ea216 24#define HB_SREG_A9_BOOT_SRC_STAT 0xfff3cf04
76c3999d 25#define HB_SREG_A9_PWRDOM_STAT 0xfff3cf20
f8973325 26#define HB_SREG_A15_PWR_CTRL 0xfff3c200
76c3999d 27
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28#define HB_PWR_SUSPEND 0
29#define HB_PWR_SOFT_RESET 1
30#define HB_PWR_HARD_RESET 2
31#define HB_PWR_SHUTDOWN 3
32
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33#define PWRDOM_STAT_SATA 0x80000000
34#define PWRDOM_STAT_PCI 0x40000000
35#define PWRDOM_STAT_EMMC 0x20000000
36
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37#define HB_SCU_A9_PWR_NORMAL 0
38#define HB_SCU_A9_PWR_DORMANT 2
39#define HB_SCU_A9_PWR_OFF 3
40
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41DECLARE_GLOBAL_DATA_PTR;
42
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43void cphy_disable_overrides(void);
44
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45/*
46 * Miscellaneous platform dependent initialisations
47 */
48int board_init(void)
49{
50 icache_enable();
51
52 return 0;
53}
54
b9463226
IC
55#ifdef CONFIG_MISC_INIT_R
56int misc_init_r(void)
57{
58 char envbuffer[16];
59 u32 boot_choice;
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60
61 boot_choice = readl(HB_SREG_A9_BOOT_SRC_STAT) & 0xff;
62 sprintf(envbuffer, "bootcmd%d", boot_choice);
00caae6d 63 if (env_get(envbuffer)) {
4a3ea216 64 sprintf(envbuffer, "run bootcmd%d", boot_choice);
382bee57 65 env_set("bootcmd", envbuffer);
4a3ea216 66 } else
382bee57 67 env_set("bootcmd", "");
4a3ea216 68
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69 return 0;
70}
95395023 71#endif
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72
73int dram_init(void)
74{
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75 return fdtdec_setup_mem_size_base();
76}
77
78int dram_init_banksize(void)
79{
80 return fdtdec_setup_memory_banksize();
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81}
82
76c3999d 83#if defined(CONFIG_OF_BOARD_SETUP)
b75d8dc5 84int ft_board_setup(void *fdt, struct bd_info *bd)
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85{
86 static const char disabled[] = "disabled";
87 u32 reg = readl(HB_SREG_A9_PWRDOM_STAT);
88
89 if (!(reg & PWRDOM_STAT_SATA))
90 do_fixup_by_compat(fdt, "calxeda,hb-ahci", "status",
91 disabled, sizeof(disabled), 1);
92
93 if (!(reg & PWRDOM_STAT_EMMC))
94 do_fixup_by_compat(fdt, "calxeda,hb-sdhci", "status",
95 disabled, sizeof(disabled), 1);
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96
97 return 0;
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98}
99#endif
100
e7fb7896 101void *board_fdt_blob_setup(int *err)
109552d7 102{
e7fb7896 103 *err = 0;
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104 /*
105 * The ECME management processor loads the DTB from NOR flash
106 * into DRAM (at 4KB), where it gets patched to contain the
107 * detected memory size.
108 */
109 return (void *)0x1000;
110}
111
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112static int is_highbank(void)
113{
114 uint32_t midr;
115
116 asm volatile ("mrc p15, 0, %0, c0, c0, 0\n" : "=r"(midr));
117
118 return (midr & 0xfff0) == 0xc090;
119}
120
35b65dd8 121void reset_cpu(void)
37fc0ed2 122{
0c34e69f 123 writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
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124 if (is_highbank())
125 writeb(HB_SCU_A9_PWR_OFF, HB_SCU_A9_PWR_STATUS);
126 else
127 writel(0x1, HB_SREG_A15_PWR_CTRL);
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128
129 wfi();
37fc0ed2 130}
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131
132/*
133 * turn off the override before transferring control to Linux, since Linux
134 * may not support spread spectrum.
135 */
136void arch_preboot_os(void)
137{
138 cphy_disable_overrides();
139}