]>
Commit | Line | Data |
---|---|---|
945af8d7 WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
e35745bb WD |
5 | * (C) Copyright 2004 |
6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. | |
7 | * | |
945af8d7 WD |
8 | * See file CREDITS for list of people who contributed to this |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include <mpc5xxx.h> | |
96e48cf6 | 29 | #include <pci.h> |
b66a9383 | 30 | #include <asm/processor.h> |
cf2817a8 | 31 | #include <libfdt.h> |
19403633 | 32 | #include <netdev.h> |
e59581c5 | 33 | |
09e4b0c5 WD |
34 | #if defined(CONFIG_LITE5200B) |
35 | #include "mt46v32m16.h" | |
e35745bb | 36 | #else |
09e4b0c5 WD |
37 | # if defined(CONFIG_MPC5200_DDR) |
38 | # include "mt46v16m16-75.h" | |
39 | # else | |
e35745bb | 40 | #include "mt48lc16m16a2-75.h" |
09e4b0c5 | 41 | # endif |
e35745bb | 42 | #endif |
d3832e8f DP |
43 | |
44 | #ifdef CONFIG_LITE5200B_PM | |
45 | /* u-boot part of low-power mode implementation */ | |
46 | #define SAVED_ADDR (*(void **)0x00000000) | |
47 | #define PSC2_4 0x02 | |
48 | ||
49 | void lite5200b_wakeup(void) | |
50 | { | |
51 | unsigned char wakeup_pin; | |
52 | void (*linux_wakeup)(void); | |
53 | ||
54 | /* check PSC2_4, if it's down "QT" is signaling we have a wakeup | |
55 | * from low power mode */ | |
56 | *(vu_char *)MPC5XXX_WU_GPIO_ENABLE = PSC2_4; | |
57 | __asm__ volatile ("sync"); | |
58 | ||
59 | wakeup_pin = *(vu_char *)MPC5XXX_WU_GPIO_DATA_I; | |
60 | if (wakeup_pin & PSC2_4) | |
61 | return; | |
62 | ||
63 | /* acknowledge to "QT" | |
64 | * by holding pin at 1 for 10 uS */ | |
65 | *(vu_char *)MPC5XXX_WU_GPIO_DIR = PSC2_4; | |
66 | __asm__ volatile ("sync"); | |
67 | *(vu_char *)MPC5XXX_WU_GPIO_DATA_O = PSC2_4; | |
68 | __asm__ volatile ("sync"); | |
69 | udelay(10); | |
70 | ||
71 | /* put ram out of self-refresh */ | |
72 | *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x80000000; /* mode_en */ | |
73 | __asm__ volatile ("sync"); | |
74 | *(vu_long *)MPC5XXX_SDRAM_CTRL |= 0x50000000; /* cke ref_en */ | |
75 | __asm__ volatile ("sync"); | |
76 | *(vu_long *)MPC5XXX_SDRAM_CTRL &= ~0x80000000; /* !mode_en */ | |
77 | __asm__ volatile ("sync"); | |
78 | udelay(10); /* wait a bit */ | |
79 | ||
80 | /* jump back to linux kernel code */ | |
81 | linux_wakeup = SAVED_ADDR; | |
82 | printf("\n\nLooks like we just woke, transferring control to 0x%08lx\n", | |
83 | linux_wakeup); | |
84 | linux_wakeup(); | |
85 | } | |
86 | #else | |
87 | #define lite5200b_wakeup() | |
88 | #endif | |
89 | ||
d94f92cb | 90 | #ifndef CFG_RAMBOOT |
e0ac62d7 WD |
91 | static void sdram_start (int hi_addr) |
92 | { | |
93 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; | |
945af8d7 | 94 | |
b2001f27 | 95 | /* unlock mode register */ |
e35745bb WD |
96 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit; |
97 | __asm__ volatile ("sync"); | |
5cf91d6b | 98 | |
b2001f27 | 99 | /* precharge all banks */ |
e35745bb WD |
100 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; |
101 | __asm__ volatile ("sync"); | |
102 | ||
103 | #if SDRAM_DDR | |
b2001f27 | 104 | /* set mode register: extended mode */ |
e35745bb WD |
105 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE; |
106 | __asm__ volatile ("sync"); | |
107 | ||
b2001f27 | 108 | /* set mode register: reset DLL */ |
e35745bb WD |
109 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000; |
110 | __asm__ volatile ("sync"); | |
e0ac62d7 | 111 | #endif |
e35745bb WD |
112 | |
113 | /* precharge all banks */ | |
114 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit; | |
115 | __asm__ volatile ("sync"); | |
116 | ||
f8d813e3 | 117 | /* auto refresh */ |
e35745bb WD |
118 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit; |
119 | __asm__ volatile ("sync"); | |
120 | ||
945af8d7 | 121 | /* set mode register */ |
e35745bb WD |
122 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
123 | __asm__ volatile ("sync"); | |
5cf91d6b | 124 | |
945af8d7 | 125 | /* normal operation */ |
e35745bb WD |
126 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
127 | __asm__ volatile ("sync"); | |
e0ac62d7 | 128 | } |
d94f92cb | 129 | #endif |
e0ac62d7 | 130 | |
e35745bb WD |
131 | /* |
132 | * ATTENTION: Although partially referenced initdram does NOT make real use | |
133 | * use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE | |
134 | * is something else than 0x00000000. | |
135 | */ | |
136 | ||
137 | #if defined(CONFIG_MPC5200) | |
9973e3c6 | 138 | phys_size_t initdram (int board_type) |
e0ac62d7 | 139 | { |
d94f92cb | 140 | ulong dramsize = 0; |
b2001f27 | 141 | ulong dramsize2 = 0; |
b66a9383 RJ |
142 | uint svr, pvr; |
143 | ||
e0ac62d7 | 144 | #ifndef CFG_RAMBOOT |
d94f92cb | 145 | ulong test1, test2; |
5cf91d6b | 146 | |
e35745bb | 147 | /* setup SDRAM chip selects */ |
e0ac62d7 WD |
148 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */ |
149 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */ | |
e35745bb | 150 | __asm__ volatile ("sync"); |
e0ac62d7 | 151 | |
b2001f27 | 152 | /* setup config registers */ |
e35745bb WD |
153 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
154 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; | |
155 | __asm__ volatile ("sync"); | |
d4ca31c4 | 156 | |
e35745bb WD |
157 | #if SDRAM_DDR |
158 | /* set tap delay */ | |
159 | *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY; | |
160 | __asm__ volatile ("sync"); | |
b2001f27 | 161 | #endif |
e0ac62d7 | 162 | |
e35745bb | 163 | /* find RAM size using SDRAM CS0 only */ |
e0ac62d7 | 164 | sdram_start(0); |
77ddac94 | 165 | test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); |
e0ac62d7 | 166 | sdram_start(1); |
77ddac94 | 167 | test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); |
e0ac62d7 WD |
168 | if (test1 > test2) { |
169 | sdram_start(0); | |
170 | dramsize = test1; | |
171 | } else { | |
172 | dramsize = test2; | |
173 | } | |
e35745bb WD |
174 | |
175 | /* memory smaller than 1MB is impossible */ | |
176 | if (dramsize < (1 << 20)) { | |
177 | dramsize = 0; | |
178 | } | |
5cf91d6b | 179 | |
e35745bb WD |
180 | /* set SDRAM CS0 size according to the amount of RAM found */ |
181 | if (dramsize > 0) { | |
182 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1; | |
183 | } else { | |
184 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ | |
185 | } | |
186 | ||
e35745bb | 187 | /* let SDRAM CS1 start right after CS0 */ |
b2001f27 | 188 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */ |
e35745bb WD |
189 | |
190 | /* find RAM size using SDRAM CS1 only */ | |
07cc0999 | 191 | if (!dramsize) |
a6310928 | 192 | sdram_start(0); |
77ddac94 | 193 | test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); |
a6310928 WD |
194 | if (!dramsize) { |
195 | sdram_start(1); | |
77ddac94 | 196 | test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000); |
a6310928 | 197 | } |
b2001f27 WD |
198 | if (test1 > test2) { |
199 | sdram_start(0); | |
200 | dramsize2 = test1; | |
201 | } else { | |
202 | dramsize2 = test2; | |
203 | } | |
5cf91d6b | 204 | |
e35745bb WD |
205 | /* memory smaller than 1MB is impossible */ |
206 | if (dramsize2 < (1 << 20)) { | |
207 | dramsize2 = 0; | |
208 | } | |
5cf91d6b | 209 | |
e35745bb WD |
210 | /* set SDRAM CS1 size according to the amount of RAM found */ |
211 | if (dramsize2 > 0) { | |
212 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize | |
213 | | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1); | |
214 | } else { | |
215 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */ | |
216 | } | |
217 | ||
218 | #else /* CFG_RAMBOOT */ | |
219 | ||
220 | /* retrieve size of memory connected to SDRAM CS0 */ | |
221 | dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; | |
222 | if (dramsize >= 0x13) { | |
223 | dramsize = (1 << (dramsize - 0x13)) << 20; | |
224 | } else { | |
225 | dramsize = 0; | |
226 | } | |
227 | ||
228 | /* retrieve size of memory connected to SDRAM CS1 */ | |
229 | dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF; | |
230 | if (dramsize2 >= 0x13) { | |
231 | dramsize2 = (1 << (dramsize2 - 0x13)) << 20; | |
232 | } else { | |
233 | dramsize2 = 0; | |
234 | } | |
235 | ||
236 | #endif /* CFG_RAMBOOT */ | |
237 | ||
b66a9383 | 238 | /* |
cf48eb9a WD |
239 | * On MPC5200B we need to set the special configuration delay in the |
240 | * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM | |
b66a9383 RJ |
241 | * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: |
242 | * | |
cf48eb9a WD |
243 | * "The SDelay should be written to a value of 0x00000004. It is |
244 | * required to account for changes caused by normal wafer processing | |
b66a9383 | 245 | * parameters." |
cf48eb9a | 246 | */ |
b66a9383 RJ |
247 | svr = get_svr(); |
248 | pvr = get_pvr(); | |
cf48eb9a | 249 | if ((SVR_MJREV(svr) >= 2) && |
b66a9383 RJ |
250 | (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { |
251 | ||
252 | *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; | |
253 | __asm__ volatile ("sync"); | |
254 | } | |
255 | ||
d3832e8f DP |
256 | lite5200b_wakeup(); |
257 | ||
e35745bb WD |
258 | return dramsize + dramsize2; |
259 | } | |
260 | ||
e0ac62d7 | 261 | #elif defined(CONFIG_MGT5100) |
e0ac62d7 | 262 | |
9973e3c6 | 263 | phys_size_t initdram (int board_type) |
e35745bb WD |
264 | { |
265 | ulong dramsize = 0; | |
266 | #ifndef CFG_RAMBOOT | |
267 | ulong test1, test2; | |
5cf91d6b | 268 | |
e35745bb WD |
269 | /* setup and enable SDRAM chip selects */ |
270 | *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; | |
271 | *(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */ | |
945af8d7 | 272 | *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ |
e35745bb WD |
273 | __asm__ volatile ("sync"); |
274 | ||
275 | /* setup config registers */ | |
276 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; | |
277 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; | |
278 | ||
279 | /* address select register */ | |
280 | *(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL; | |
281 | __asm__ volatile ("sync"); | |
282 | ||
283 | /* find RAM size */ | |
284 | sdram_start(0); | |
77ddac94 | 285 | test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); |
e35745bb | 286 | sdram_start(1); |
77ddac94 | 287 | test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); |
e35745bb WD |
288 | if (test1 > test2) { |
289 | sdram_start(0); | |
290 | dramsize = test1; | |
291 | } else { | |
292 | dramsize = test2; | |
293 | } | |
294 | ||
295 | /* set SDRAM end address according to size */ | |
296 | *(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15); | |
5cf91d6b | 297 | |
e35745bb WD |
298 | #else /* CFG_RAMBOOT */ |
299 | ||
300 | /* Retrieve amount of SDRAM available */ | |
d94f92cb | 301 | dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15); |
e35745bb | 302 | |
d94f92cb | 303 | #endif /* CFG_RAMBOOT */ |
b2001f27 | 304 | |
e0ac62d7 | 305 | return dramsize; |
945af8d7 WD |
306 | } |
307 | ||
e35745bb WD |
308 | #else |
309 | #error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined | |
310 | #endif | |
311 | ||
945af8d7 WD |
312 | int checkboard (void) |
313 | { | |
09e4b0c5 WD |
314 | #if defined (CONFIG_LITE5200B) |
315 | puts ("Board: Freescale Lite5200B\n"); | |
316 | #elif defined(CONFIG_MPC5200) | |
945af8d7 WD |
317 | puts ("Board: Motorola MPC5200 (IceCube)\n"); |
318 | #elif defined(CONFIG_MGT5100) | |
319 | puts ("Board: Motorola MGT5100 (IceCube)\n"); | |
320 | #endif | |
321 | return 0; | |
322 | } | |
323 | ||
324 | void flash_preinit(void) | |
325 | { | |
326 | /* | |
327 | * Now, when we are in RAM, enable flash write | |
328 | * access for detection process. | |
329 | * Note that CS_BOOT cannot be cleared when | |
330 | * executing in flash. | |
331 | */ | |
332 | #if defined(CONFIG_MGT5100) | |
333 | *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ | |
334 | *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ | |
335 | #endif | |
336 | *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ | |
337 | } | |
96e48cf6 | 338 | |
7152b1d0 WD |
339 | void flash_afterinit(ulong size) |
340 | { | |
341 | if (size == 0x800000) { /* adjust mapping */ | |
42d1f039 | 342 | *(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START = |
7152b1d0 | 343 | START_REG(CFG_BOOTCS_START | size); |
42d1f039 | 344 | *(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP = |
7152b1d0 WD |
345 | STOP_REG(CFG_BOOTCS_START | size, size); |
346 | } | |
347 | } | |
348 | ||
96e48cf6 WD |
349 | #ifdef CONFIG_PCI |
350 | static struct pci_controller hose; | |
351 | ||
352 | extern void pci_mpc5xxx_init(struct pci_controller *); | |
353 | ||
354 | void pci_init_board(void) | |
355 | { | |
356 | pci_mpc5xxx_init(&hose); | |
357 | } | |
358 | #endif | |
c3f9d493 | 359 | |
77a31854 | 360 | #if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) |
c3f9d493 | 361 | |
c3f9d493 WD |
362 | void init_ide_reset (void) |
363 | { | |
4d13cbad | 364 | debug ("init_ide_reset\n"); |
42dfe7a1 | 365 | |
dd520bf3 | 366 | /* Configure PSC1_4 as GPIO output for ATA reset */ |
c3f9d493 | 367 | *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4; |
4d13cbad | 368 | *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4; |
64f70bed | 369 | /* Deassert reset */ |
dae80f3c | 370 | *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; |
c3f9d493 WD |
371 | } |
372 | ||
373 | void ide_set_reset (int idereset) | |
374 | { | |
4d13cbad WD |
375 | debug ("ide_reset(%d)\n", idereset); |
376 | ||
c3f9d493 | 377 | if (idereset) { |
dae80f3c | 378 | *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4; |
64f70bed WD |
379 | /* Make a delay. MPC5200 spec says 25 usec min */ |
380 | udelay(500000); | |
c3f9d493 | 381 | } else { |
dae80f3c | 382 | *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4; |
c3f9d493 WD |
383 | } |
384 | } | |
77a31854 | 385 | #endif |
e59581c5 | 386 | |
cf2817a8 | 387 | #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) |
e59581c5 SR |
388 | void |
389 | ft_board_setup(void *blob, bd_t *bd) | |
390 | { | |
391 | ft_cpu_setup(blob, bd); | |
392 | } | |
393 | #endif | |
19403633 BW |
394 | |
395 | int board_eth_init(bd_t *bis) | |
396 | { | |
e1d7480b | 397 | cpu_eth_init(bis); /* Built in FEC comes first */ |
19403633 BW |
398 | return pci_eth_init(bis); |
399 | } |