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1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <mpc5xxx.h> | |
26 | ||
27 | long int initdram (int board_type) | |
28 | { | |
29 | #ifndef CFG_RAMBOOT | |
30 | /* configure SDRAM start/end */ | |
31 | #if defined(CONFIG_MPC5200) | |
32 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x00000018;/* 32M at 0x0 */ | |
33 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x02000000;/* disabled */ | |
34 | ||
35 | /* setup config registers */ | |
36 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2233a00; | |
37 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004; | |
38 | ||
39 | /* unlock mode register */ | |
40 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0000; | |
41 | /* precharge all banks */ | |
42 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002; | |
43 | /* set mode register */ | |
44 | *(vu_long *)MPC5XXX_SDRAM_MODE = 0x408d0000; | |
45 | /* precharge all banks */ | |
46 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0002; | |
47 | /* auto refresh */ | |
48 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd04f0004; | |
49 | /* set mode register */ | |
50 | *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000; | |
51 | /* normal operation */ | |
52 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x504f0000; | |
53 | #elif defined(CONFIG_MGT5100) | |
54 | *(vu_long *)MPC5XXX_SDRAM_START = 0x00000000; | |
55 | *(vu_long *)MPC5XXX_SDRAM_STOP = 0x000007ff;/* 64M */ | |
56 | *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ | |
57 | ||
58 | /* setup config registers */ | |
59 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0xc2222600; | |
60 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x88b70004; | |
61 | ||
62 | /* address select register */ | |
63 | *(vu_long *)MPC5XXX_SDRAM_XLBSEL = 0x03000000; | |
64 | ||
65 | /* unlock mode register */ | |
66 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0000; | |
67 | /* precharge all banks */ | |
68 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002; | |
69 | /* set mode register */ | |
70 | *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000; | |
71 | /* precharge all banks */ | |
72 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0002; | |
73 | /* auto refresh */ | |
74 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0xd14f0004; | |
75 | /* set mode register */ | |
76 | *(vu_long *)MPC5XXX_SDRAM_MODE = 0x008d0000; | |
77 | /* normal operation */ | |
78 | *(vu_long *)MPC5XXX_SDRAM_CTRL = 0x514f0000; | |
79 | #endif | |
80 | #else | |
81 | #ifdef CONFIG_MGT5100 | |
82 | *(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */ | |
83 | #endif | |
84 | #endif | |
85 | /* return total ram size */ | |
86 | #if defined(CONFIG_MGT5100) | |
87 | return (64 * 1024 * 1024); | |
88 | #elif defined(CONFIG_MPC5200) | |
89 | return (32 * 1024 * 1024); | |
90 | #endif | |
91 | } | |
92 | ||
93 | int checkboard (void) | |
94 | { | |
95 | #if defined(CONFIG_MPC5200) | |
96 | puts ("Board: Motorola MPC5200 (IceCube)\n"); | |
97 | #elif defined(CONFIG_MGT5100) | |
98 | puts ("Board: Motorola MGT5100 (IceCube)\n"); | |
99 | #endif | |
100 | return 0; | |
101 | } | |
102 | ||
103 | void flash_preinit(void) | |
104 | { | |
105 | /* | |
106 | * Now, when we are in RAM, enable flash write | |
107 | * access for detection process. | |
108 | * Note that CS_BOOT cannot be cleared when | |
109 | * executing in flash. | |
110 | */ | |
111 | #if defined(CONFIG_MGT5100) | |
112 | *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */ | |
113 | *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */ | |
114 | #endif | |
115 | *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */ | |
116 | } |