[people/ms/u-boot.git] / board / icecube / icecube.c

/*
 * (C) Copyright 2003
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2004
 * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc5xxx.h>
#include <pci.h>

#if defined(CONFIG_MPC5200_DDR)
#include "mt46v16m16-75.h"
#else
#include "mt48lc16m16a2-75.h"
#endif

#ifndef CFG_RAMBOOT
static void sdram_start (int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set mode register: extended mode */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	__asm__ volatile ("sync");

	/* set mode register: reset DLL */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
	__asm__ volatile ("sync");
#endif

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* auto refresh */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | hi_addr_bit;
	__asm__ volatile ("sync");

	/* set mode register */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	__asm__ volatile ("sync");

	/* normal operation */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
	__asm__ volatile ("sync");
}
#endif

/*
 * ATTENTION: Although partially referenced initdram does NOT make real use
 *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
 *            is something else than 0x00000000.
 */

#if defined(CONFIG_MPC5200)
long int initdram (int board_type)
{
	ulong dramsize = 0;
	ulong dramsize2 = 0;
#ifndef CFG_RAMBOOT
	ulong test1, test2;

	/* setup SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	__asm__ volatile ("sync");

#if SDRAM_DDR
	/* set tap delay */
	*(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	__asm__ volatile ("sync");
#endif

	/* find RAM size using SDRAM CS0 only */
	sdram_start(0);
	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20)) {
		dramsize = 0;
	}

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	}

	/* let SDRAM CS1 start right after CS0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */

	/* find RAM size using SDRAM CS1 only */
	if (!dramsize)
		sdram_start(0);
	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
	if (!dramsize) {
		sdram_start(1);
		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
	}
	if (test1 > test2) {
		sdram_start(0);
		dramsize2 = test1;
	} else {
		dramsize2 = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize2 < (1 << 20)) {
		dramsize2 = 0;
	}

	/* set SDRAM CS1 size according to the amount of RAM found */
	if (dramsize2 > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
			| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	}

#else /* CFG_RAMBOOT */

	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
	if (dramsize >= 0x13) {
		dramsize = (1 << (dramsize - 0x13)) << 20;
	} else {
		dramsize = 0;
	}

	/* retrieve size of memory connected to SDRAM CS1 */
	dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
	if (dramsize2 >= 0x13) {
		dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	} else {
		dramsize2 = 0;
	}

#endif /* CFG_RAMBOOT */

	return dramsize + dramsize2;
}

#elif defined(CONFIG_MGT5100)

long int initdram (int board_type)
{
	ulong dramsize = 0;
#ifndef CFG_RAMBOOT
	ulong test1, test2;

	/* setup and enable SDRAM chip selects */
	*(vu_long *)MPC5XXX_SDRAM_START = 0x00000000;
	*(vu_long *)MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
	*(vu_long *)MPC5XXX_ADDECR |= (1 << 22); /* Enable SDRAM */
	__asm__ volatile ("sync");

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;

	/* address select register */
	*(vu_long *)MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
	__asm__ volatile ("sync");

	/* find RAM size */
	sdram_start(0);
	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* set SDRAM end address according to size */
	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);

#else /* CFG_RAMBOOT */

	/* Retrieve amount of SDRAM available */
	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);

#endif /* CFG_RAMBOOT */

	return dramsize;
}

#else
#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
#endif

int checkboard (void)
{
#if defined(CONFIG_MPC5200)
	puts ("Board: Motorola MPC5200 (IceCube)\n");
#elif defined(CONFIG_MGT5100)
	puts ("Board: Motorola MGT5100 (IceCube)\n");
#endif
	return 0;
}

void flash_preinit(void)
{
	/*
	 * Now, when we are in RAM, enable flash write
	 * access for detection process.
	 * Note that CS_BOOT cannot be cleared when
	 * executing in flash.
	 */
#if defined(CONFIG_MGT5100)
	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16); /* enable CS0 */
#endif
	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
}

void flash_afterinit(ulong size)
{
	if (size == 0x800000) { /* adjust mapping */
		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
			START_REG(CFG_BOOTCS_START | size);
		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
			STOP_REG(CFG_BOOTCS_START | size, size);
	}
}

#ifdef	CONFIG_PCI
static struct pci_controller hose;

extern void pci_mpc5xxx_init(struct pci_controller *);

void pci_init_board(void)
{
	pci_mpc5xxx_init(&hose);
}
#endif

#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)

#define GPIO_PSC1_4	0x01000000UL

void init_ide_reset (void)
{
	debug ("init_ide_reset\n");

    	/* Configure PSC1_4 as GPIO output for ATA reset */
	*(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
	*(vu_long *) MPC5XXX_WU_GPIO_DIR    |= GPIO_PSC1_4;
	/* Deassert reset */
	*(vu_long *) MPC5XXX_WU_GPIO_DATA   |= GPIO_PSC1_4;
}

void ide_set_reset (int idereset)
{
	debug ("ide_reset(%d)\n", idereset);

	if (idereset) {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
		/* Make a delay. MPC5200 spec says 25 usec min */
		udelay(500000);
	} else {
		*(vu_long *) MPC5XXX_WU_GPIO_DATA |=  GPIO_PSC1_4;
	}
}
#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
Commit	Line	Data
945af8d7 WD	1	/*
	2	* (C) Copyright 2003
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
e35745bb WD	5	* (C) Copyright 2004
	6	* Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com.
	7	*
945af8d7 WD	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#include <common.h>
	28	#include <mpc5xxx.h>
96e48cf6	29	#include <pci.h>
945af8d7	30
e35745bb WD	31	#if defined(CONFIG_MPC5200_DDR)
	32	#include "mt46v16m16-75.h"
	33	#else
	34	#include "mt48lc16m16a2-75.h"
	35	#endif
	36
d94f92cb	37	#ifndef CFG_RAMBOOT
e0ac62d7 WD	38	static void sdram_start (int hi_addr)
	39	{
	40	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
945af8d7	41
b2001f27	42	/* unlock mode register */
e35745bb WD	43	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \| hi_addr_bit;
e35745bb WD	44	__asm__ volatile ("sync");
5cf91d6b	45
b2001f27	46	/* precharge all banks */
e35745bb WD	47	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	48	__asm__ volatile ("sync");
	49
	50	#if SDRAM_DDR
b2001f27	51	/* set mode register: extended mode */
e35745bb WD	52	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
	53	__asm__ volatile ("sync");
	54
b2001f27	55	/* set mode register: reset DLL */
e35745bb WD	56	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE \| 0x04000000;
e35745bb WD	57	__asm__ volatile ("sync");
e0ac62d7	58	#endif
e35745bb WD	59
	60	/* precharge all banks */
	61	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \| hi_addr_bit;
	62	__asm__ volatile ("sync");
	63
f8d813e3	64	/* auto refresh */
e35745bb WD	65	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \| hi_addr_bit;
	66	__asm__ volatile ("sync");
	67
945af8d7	68	/* set mode register */
e35745bb WD	69	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
e35745bb WD	70	__asm__ volatile ("sync");
5cf91d6b	71
945af8d7	72	/* normal operation */
e35745bb WD	73	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
e35745bb WD	74	__asm__ volatile ("sync");
e0ac62d7	75	}
d94f92cb	76	#endif
e0ac62d7	77
e35745bb WD	78	/*
	79	* ATTENTION: Although partially referenced initdram does NOT make real use
	80	* use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
	81	* is something else than 0x00000000.
	82	*/
	83
	84	#if defined(CONFIG_MPC5200)
e0ac62d7 WD	85	long int initdram (int board_type)
e0ac62d7 WD	86	{
d94f92cb	87	ulong dramsize = 0;
b2001f27	88	ulong dramsize2 = 0;
e0ac62d7	89	#ifndef CFG_RAMBOOT
d94f92cb	90	ulong test1, test2;
5cf91d6b	91
e35745bb	92	/* setup SDRAM chip selects */
e0ac62d7 WD	93	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001e;/* 2G at 0x0 */
e0ac62d7 WD	94	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x80000000;/* disabled */
e35745bb	95	__asm__ volatile ("sync");
e0ac62d7	96
b2001f27	97	/* setup config registers */
e35745bb WD	98	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	99	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	100	__asm__ volatile ("sync");
d4ca31c4	101
e35745bb WD	102	#if SDRAM_DDR
	103	/* set tap delay */
	104	(vu_long )MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
	105	__asm__ volatile ("sync");
b2001f27	106	#endif
e0ac62d7	107
e35745bb	108	/* find RAM size using SDRAM CS0 only */
e0ac62d7	109	sdram_start(0);
77ddac94	110	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
e0ac62d7	111	sdram_start(1);
77ddac94	112	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
e0ac62d7 WD	113	if (test1 > test2) {
	114	sdram_start(0);
	115	dramsize = test1;
	116	} else {
	117	dramsize = test2;
	118	}
e35745bb WD	119
	120	/* memory smaller than 1MB is impossible */
	121	if (dramsize < (1 << 20)) {
	122	dramsize = 0;
	123	}
5cf91d6b	124
e35745bb WD	125	/* set SDRAM CS0 size according to the amount of RAM found */
	126	if (dramsize > 0) {
	127	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 + __builtin_ffs(dramsize >> 20) - 1;
	128	} else {
	129	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	130	}
	131
e35745bb	132	/* let SDRAM CS1 start right after CS0 */
b2001f27	133	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001e;/* 2G */
e35745bb WD	134
e35745bb WD	135	/* find RAM size using SDRAM CS1 only */
07cc0999	136	if (!dramsize)
a6310928	137	sdram_start(0);
77ddac94	138	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
a6310928 WD	139	if (!dramsize) {
a6310928 WD	140	sdram_start(1);
77ddac94	141	test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
a6310928	142	}
b2001f27 WD	143	if (test1 > test2) {
	144	sdram_start(0);
	145	dramsize2 = test1;
	146	} else {
	147	dramsize2 = test2;
	148	}
5cf91d6b	149
e35745bb WD	150	/* memory smaller than 1MB is impossible */
	151	if (dramsize2 < (1 << 20)) {
	152	dramsize2 = 0;
	153	}
5cf91d6b	154
e35745bb WD	155	/* set SDRAM CS1 size according to the amount of RAM found */
	156	if (dramsize2 > 0) {
	157	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize
	158	\| (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
	159	} else {
	160	(vu_long )MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
	161	}
	162
	163	#else /* CFG_RAMBOOT */
	164
	165	/* retrieve size of memory connected to SDRAM CS0 */
	166	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
	167	if (dramsize >= 0x13) {
	168	dramsize = (1 << (dramsize - 0x13)) << 20;
	169	} else {
	170	dramsize = 0;
	171	}
	172
	173	/* retrieve size of memory connected to SDRAM CS1 */
	174	dramsize2 = (vu_long )MPC5XXX_SDRAM_CS1CFG & 0xFF;
	175	if (dramsize2 >= 0x13) {
	176	dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
	177	} else {
	178	dramsize2 = 0;
	179	}
	180
	181	#endif /* CFG_RAMBOOT */
	182
	183	return dramsize + dramsize2;
	184	}
	185
e0ac62d7	186	#elif defined(CONFIG_MGT5100)
e0ac62d7	187
e35745bb WD	188	long int initdram (int board_type)
	189	{
	190	ulong dramsize = 0;
	191	#ifndef CFG_RAMBOOT
	192	ulong test1, test2;
5cf91d6b	193
e35745bb WD	194	/* setup and enable SDRAM chip selects */
	195	(vu_long )MPC5XXX_SDRAM_START = 0x00000000;
	196	(vu_long )MPC5XXX_SDRAM_STOP = 0x0000ffff;/* 2G */
945af8d7	197	(vu_long )MPC5XXX_ADDECR \|= (1 << 22); /* Enable SDRAM */
e35745bb WD	198	__asm__ volatile ("sync");
	199
	200	/* setup config registers */
	201	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	202	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	203
	204	/* address select register */
	205	(vu_long )MPC5XXX_SDRAM_XLBSEL = SDRAM_ADDRSEL;
	206	__asm__ volatile ("sync");
	207
	208	/* find RAM size */
	209	sdram_start(0);
77ddac94	210	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
e35745bb	211	sdram_start(1);
77ddac94	212	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
e35745bb WD	213	if (test1 > test2) {
	214	sdram_start(0);
	215	dramsize = test1;
	216	} else {
	217	dramsize = test2;
	218	}
	219
	220	/* set SDRAM end address according to size */
	221	(vu_long )MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
5cf91d6b	222
e35745bb WD	223	#else /* CFG_RAMBOOT */
	224
	225	/* Retrieve amount of SDRAM available */
d94f92cb	226	dramsize = (((vu_long )MPC5XXX_SDRAM_STOP + 1) << 15);
e35745bb	227
d94f92cb	228	#endif /* CFG_RAMBOOT */
b2001f27	229
e0ac62d7	230	return dramsize;
945af8d7 WD	231	}
945af8d7 WD	232
e35745bb WD	233	#else
	234	#error Neither CONFIG_MPC5200 or CONFIG_MGT5100 defined
	235	#endif
	236
945af8d7 WD	237	int checkboard (void)
	238	{
	239	#if defined(CONFIG_MPC5200)
	240	puts ("Board: Motorola MPC5200 (IceCube)\n");
	241	#elif defined(CONFIG_MGT5100)
	242	puts ("Board: Motorola MGT5100 (IceCube)\n");
	243	#endif
	244	return 0;
	245	}
	246
	247	void flash_preinit(void)
	248	{
	249	/*
	250	* Now, when we are in RAM, enable flash write
	251	* access for detection process.
	252	* Note that CS_BOOT cannot be cleared when
	253	* executing in flash.
	254	*/
	255	#if defined(CONFIG_MGT5100)
	256	(vu_long )MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
	257	(vu_long )MPC5XXX_ADDECR \|= (1 << 16); /* enable CS0 */
	258	#endif
	259	(vu_long )MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
	260	}
96e48cf6	261
7152b1d0 WD	262	void flash_afterinit(ulong size)
	263	{
	264	if (size == 0x800000) { /* adjust mapping */
42d1f039	265	(vu_long )MPC5XXX_BOOTCS_START = (vu_long )MPC5XXX_CS0_START =
7152b1d0	266	START_REG(CFG_BOOTCS_START \| size);
42d1f039	267	(vu_long )MPC5XXX_BOOTCS_STOP = (vu_long )MPC5XXX_CS0_STOP =
7152b1d0 WD	268	STOP_REG(CFG_BOOTCS_START \| size, size);
	269	}
	270	}
	271
96e48cf6 WD	272	#ifdef CONFIG_PCI
	273	static struct pci_controller hose;
	274
	275	extern void pci_mpc5xxx_init(struct pci_controller *);
	276
	277	void pci_init_board(void)
	278	{
	279	pci_mpc5xxx_init(&hose);
	280	}
	281	#endif
c3f9d493 WD	282
	283	#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
	284
4d13cbad	285	#define GPIO_PSC1_4 0x01000000UL
c3f9d493 WD	286
	287	void init_ide_reset (void)
	288	{
4d13cbad	289	debug ("init_ide_reset\n");
42dfe7a1	290
c3f9d493	291	/* Configure PSC1_4 as GPIO output for ATA reset */
c3f9d493	292	(vu_long ) MPC5XXX_WU_GPIO_ENABLE \|= GPIO_PSC1_4;
4d13cbad	293	(vu_long ) MPC5XXX_WU_GPIO_DIR \|= GPIO_PSC1_4;
64f70bed WD	294	/* Deassert reset */
64f70bed WD	295	(vu_long ) MPC5XXX_WU_GPIO_DATA \|= GPIO_PSC1_4;
c3f9d493 WD	296	}
	297
	298	void ide_set_reset (int idereset)
	299	{
4d13cbad WD	300	debug ("ide_reset(%d)\n", idereset);
4d13cbad WD	301
c3f9d493 WD	302	if (idereset) {
c3f9d493 WD	303	(vu_long ) MPC5XXX_WU_GPIO_DATA &= ~GPIO_PSC1_4;
64f70bed WD	304	/* Make a delay. MPC5200 spec says 25 usec min */
64f70bed WD	305	udelay(500000);
c3f9d493	306	} else {
4d13cbad	307	(vu_long ) MPC5XXX_WU_GPIO_DATA \|= GPIO_PSC1_4;
c3f9d493 WD	308	}
	309	}
	310	#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */