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[people/ms/u-boot.git] / board / ifm / ac14xx / ac14xx.c
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AG		 1/*
2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009 Dave Srl www.dave.eu
4 * (C) Copyright 2010 ifm ecomatic GmbH
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15#include <common.h>
16#include <asm/bitops.h>
17#include <command.h>
18#include <asm/io.h>
19#include <asm/processor.h>
20#include <asm/mpc512x.h>
21#include <fdt_support.h>
22#ifdef CONFIG_MISC_INIT_R
23#include <i2c.h>
24#endif
25
26DECLARE_GLOBAL_DATA_PTR;
27
28static void gpio_configure(void)
29{
30 immap_t *im;
31 gpio512x_t *gpioregs;
32
33 im = (immap_t *) CONFIG_SYS_IMMR;
34 gpioregs = &im->gpio;
35 out_be32(&gpioregs->gpodr, 0x00290000); /* open drain */
36 out_be32(&gpioregs->gpdat, 0x80001040); /* data (when output) */
37
38 /*
39 * out_be32(&gpioregs->gpdir, 0xC2293020);
40 * workaround for a hardware affect: configure direction in pieces,
41 * setting all outputs at once drops the reset line too low and
42 * makes us lose the MII connection (breaks ethernet for us)
43 */
44 out_be32(&gpioregs->gpdir, 0x02003060); /* direction */
45 setbits_be32(&gpioregs->gpdir, 0x00200000); /* += reset asi */
46 udelay(10);
47 setbits_be32(&gpioregs->gpdir, 0x00080000); /* += reset safety */
48 udelay(10);
49 setbits_be32(&gpioregs->gpdir, 0x00010000); /* += reset comm */
50 udelay(10);
51 setbits_be32(&gpioregs->gpdir, 0xC0000000); /* += backlight, KB sel */
52
53 /* to turn from red to yellow when U-Boot runs */
54 setbits_be32(&gpioregs->gpdat, 0x00002020);
55 out_be32(&gpioregs->gpimr, 0x00000000); /* interrupt mask */
56 out_be32(&gpioregs->gpicr1, 0x00000004); /* interrupt sense part 1 */
57 out_be32(&gpioregs->gpicr2, 0x00A80000); /* interrupt sense part 2 */
58 out_be32(&gpioregs->gpier, 0xFFFFFFFF); /* interrupt events, clear */
59}
60
61/* the physical location of the pins */
62#define GPIOKEY_ROW_BITMASK 0x40000000
63#define GPIOKEY_ROW_UPPER 0
64#define GPIOKEY_ROW_LOWER 1
65
66#define GPIOKEY_COL0_BITMASK 0x20000000
67#define GPIOKEY_COL1_BITMASK 0x10000000
68#define GPIOKEY_COL2_BITMASK 0x08000000
69
70/* the logical presentation of pressed keys */
71#define GPIOKEY_BIT_FNLEFT (1 << 5)
72#define GPIOKEY_BIT_FNRIGHT (1 << 4)
73#define GPIOKEY_BIT_DIRUP (1 << 3)
74#define GPIOKEY_BIT_DIRLEFT (1 << 2)
75#define GPIOKEY_BIT_DIRRIGHT (1 << 1)
76#define GPIOKEY_BIT_DIRDOWN (1 << 0)
77
78/* the hotkey combination which starts recovery */
79#define GPIOKEY_BITS_RECOVERY (GPIOKEY_BIT_FNLEFT | GPIOKEY_BIT_DIRUP | \
80 GPIOKEY_BIT_DIRDOWN)
81
82static void gpio_selectrow(gpio512x_t *gpioregs, u32 row)
83{
84
85 if (row)
86 setbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
87 else
88 clrbits_be32(&gpioregs->gpdat, GPIOKEY_ROW_BITMASK);
89 udelay(10);
90}
91
92static u32 gpio_querykbd(void)
93{
94 immap_t *im;
95 gpio512x_t *gpioregs;
96 u32 keybits;
97 u32 input;
98
99 im = (immap_t *)CONFIG_SYS_IMMR;
100 gpioregs = &im->gpio;
101 keybits = 0;
102
103 /* query upper row */
104 gpio_selectrow(gpioregs, GPIOKEY_ROW_UPPER);
105 input = in_be32(&gpioregs->gpdat);
106 if ((input & GPIOKEY_COL0_BITMASK) == 0)
107 keybits |= GPIOKEY_BIT_FNLEFT;
108 if ((input & GPIOKEY_COL1_BITMASK) == 0)
109 keybits |= GPIOKEY_BIT_DIRUP;
110 if ((input & GPIOKEY_COL2_BITMASK) == 0)
111 keybits |= GPIOKEY_BIT_FNRIGHT;
112
113 /* query lower row */
114 gpio_selectrow(gpioregs, GPIOKEY_ROW_LOWER);
115 input = in_be32(&gpioregs->gpdat);
116 if ((input & GPIOKEY_COL0_BITMASK) == 0)
117 keybits |= GPIOKEY_BIT_DIRLEFT;
118 if ((input & GPIOKEY_COL1_BITMASK) == 0)
119 keybits |= GPIOKEY_BIT_DIRRIGHT;
120 if ((input & GPIOKEY_COL2_BITMASK) == 0)
121 keybits |= GPIOKEY_BIT_DIRDOWN;
122
123 /* return bit pattern for keys */
124 return keybits;
125}
126
127/* excerpt from the recovery's hw_info.h */
128
129static int eeprom_diag = 1;
130
131struct __attribute__ ((__packed__)) eeprom_layout {
132 char magic[3]; /** 'ifm' */
133 u8 len[2]; /** content length without magic/len fields */
134 u8 version[3]; /** structure version */
135 u8 type; /** type of PCB */
136 u8 reserved[0x37]; /** padding up to offset 0x40 */
137 u8 macaddress[6]; /** ethernet MAC (for the mainboard) @0x40 */
138};
139
140#define HW_COMP_MAINCPU 2
141
142static struct eeprom_layout eeprom_content;
143static int eeprom_was_read; /* has_been_read */
144static int eeprom_is_valid;
145static int eeprom_version;
146
147#define get_eeprom_field_int(name) ({ \
148 int value; \
149 int idx; \
150 value = 0; \
151 for (idx = 0; idx < sizeof(name); idx++) { \
152 value <<= 8; \
153 value |= name[idx]; \
154 } \
155 value; \
156})
157
158static int read_eeprom(void)
159{
160 int eeprom_datalen;
161 int ret;
162
163 if (eeprom_was_read)
164 return 0;
165
166 eeprom_is_valid = 0;
167 ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0,
168 CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
169 (uchar *)&eeprom_content, sizeof(eeprom_content));
170 if (eeprom_diag) {
171 printf("DIAG: %s() read rc[%d], size[%d]\n",
172 __func__, ret, sizeof(eeprom_content));
173 }
174
175 if (ret != 0)
176 return -1;
177
178 eeprom_was_read = 1;
179
180 /*
181 * check validity of EEPROM content
182 * (check version, length, optionally checksum)
183 */
184 eeprom_is_valid = 1;
185 eeprom_datalen = get_eeprom_field_int(eeprom_content.len);
186 eeprom_version = get_eeprom_field_int(eeprom_content.version);
187
188 if (eeprom_diag) {
189 printf("DIAG: %s() magic[%c%c%c] len[%d] ver[%d] type[%d]\n",
190 __func__, eeprom_content.magic[0],
191 eeprom_content.magic[1], eeprom_content.magic[2],
192 eeprom_datalen, eeprom_version, eeprom_content.type);
193 }
194 if (strncmp(eeprom_content.magic, "ifm", strlen("ifm")) != 0)
195 eeprom_is_valid = 0;
196 if (eeprom_datalen < sizeof(struct eeprom_layout) - 5)
197 eeprom_is_valid = 0;
198 if ((eeprom_version != 1) && (eeprom_version != 2))
199 eeprom_is_valid = 0;
200 if (eeprom_content.type != HW_COMP_MAINCPU)
201 eeprom_is_valid = 0;
202
203 if (eeprom_diag)
204 printf("DIAG: %s() valid[%d]\n", __func__, eeprom_is_valid);
205
206 return ret;
207}
208
209int mac_read_from_eeprom(void)
210{
211 const u8 *mac;
212
213 if (read_eeprom()) {
214 printf("I2C EEPROM read failed.\n");
215 return -1;
216 }
217
218 if (!eeprom_is_valid) {
219 printf("I2C EEPROM content not valid\n");
220 return -1;
221 }
222
223 mac = NULL;
224 switch (eeprom_version) {
225 case 1:
226 case 2:
227 mac = (const u8 *)&eeprom_content.macaddress;
228 break;
229 }
230
231 if (mac && is_valid_ether_addr(mac)) {
232 eth_setenv_enetaddr("ethaddr", mac);
233 printf("DIAG: %s() MAC value [%s]\n",
234 __func__, getenv("ethaddr"));
235 }
236
237 return 0;
238}
239
240/*
241 * BEWARE!
242 * this board uses DDR1(!) Micron SDRAM, *NOT* the DDR2
243 * which the ADS, Aria or PDM360NG boards are using
244 * (the steps outlined here refer to the Micron datasheet)
245 */
246u32 sdram_init_seq[] = {
247 /* item 6, at least one NOP after CKE went high */
248 CONFIG_SYS_DDRCMD_NOP,
249 CONFIG_SYS_DDRCMD_NOP,
250 CONFIG_SYS_DDRCMD_NOP,
251 CONFIG_SYS_DDRCMD_NOP,
252 CONFIG_SYS_DDRCMD_NOP,
253 CONFIG_SYS_DDRCMD_NOP,
254 CONFIG_SYS_DDRCMD_NOP,
255 CONFIG_SYS_DDRCMD_NOP,
256 CONFIG_SYS_DDRCMD_NOP,
257 CONFIG_SYS_DDRCMD_NOP,
258 /* item 7, precharge all; item 8, tRP (20ns) */
259 CONFIG_SYS_DDRCMD_PCHG_ALL,
260 CONFIG_SYS_DDRCMD_NOP,
261 /* item 9, extended mode register; item 10, tMRD 10ns) */
262 CONFIG_SYS_MICRON_EMODE | CONFIG_SYS_MICRON_EMODE_PARAM,
263 CONFIG_SYS_DDRCMD_NOP,
264 /*
265 * item 11, (base) mode register _with_ reset DLL;
266 * item 12, tMRD (10ns)
267 */
268 CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_RSTDLL |
269 CONFIG_SYS_MICRON_BMODE_PARAM,
270 CONFIG_SYS_DDRCMD_NOP,
271 /* item 13, precharge all; item 14, tRP (20ns) */
272 CONFIG_SYS_DDRCMD_PCHG_ALL,
273 CONFIG_SYS_DDRCMD_NOP,
274 /*
275 * item 15, auto refresh (i.e. refresh with CKE held high);
276 * item 16, tRFC (70ns)
277 */
278 CONFIG_SYS_DDRCMD_RFSH,
279 CONFIG_SYS_DDRCMD_NOP,
280 CONFIG_SYS_DDRCMD_NOP,
281 CONFIG_SYS_DDRCMD_NOP,
282 CONFIG_SYS_DDRCMD_NOP,
283 CONFIG_SYS_DDRCMD_NOP,
284 CONFIG_SYS_DDRCMD_NOP,
285 CONFIG_SYS_DDRCMD_NOP,
286 CONFIG_SYS_DDRCMD_NOP,
287 /*
288 * item 17, auto refresh (i.e. refresh with CKE held high);
289 * item 18, tRFC (70ns)
290 */
291 CONFIG_SYS_DDRCMD_RFSH,
292 CONFIG_SYS_DDRCMD_NOP,
293 CONFIG_SYS_DDRCMD_NOP,
294 CONFIG_SYS_DDRCMD_NOP,
295 CONFIG_SYS_DDRCMD_NOP,
296 CONFIG_SYS_DDRCMD_NOP,
297 CONFIG_SYS_DDRCMD_NOP,
298 CONFIG_SYS_DDRCMD_NOP,
299 CONFIG_SYS_DDRCMD_NOP,
300 /* item 19, optional, unassert DLL reset; item 20, tMRD (20ns) */
301 CONFIG_SYS_MICRON_BMODE | CONFIG_SYS_MICRON_BMODE_PARAM,
302 CONFIG_SYS_DDRCMD_NOP,
303 /*
304 * item 21, "actually done", but make sure 200 DRAM clock cycles
305 * have passed after DLL reset before READ requests are issued
306 * (200 cycles at 160MHz -> 1.25 usec)
307 */
308 /* EMPTY, optional, we don't do it */
309};
310
311phys_size_t initdram(int board_type)
312{
313 return fixed_sdram(NULL, sdram_init_seq, ARRAY_SIZE(sdram_init_seq));
314}
315
316int misc_init_r(void)
317{
318 u32 keys;
319 char *s;
320 int want_recovery;
321
322 /* we use bus I2C-0 for the on-board eeprom */
323 i2c_set_bus_num(0);
324
325 /* setup GPIO directions and initial values */
326 gpio_configure();
327
328 /*
329 * check the GPIO keyboard,
330 * enforced start of the recovery when
331 * - the appropriate keys were pressed
332 * - a previous installation was aborted or has failed
333 * - "some" external software told us to
334 */
335 want_recovery = 0;
336 keys = gpio_querykbd();
337 printf("GPIO keyboard status [0x%08X]\n", keys);
338 /* XXX insist in the _exact_ combination? */
339 if ((keys & GPIOKEY_BITS_RECOVERY) == GPIOKEY_BITS_RECOVERY) {
340 printf("GPIO keyboard requested RECOVERY\n");
341 /* XXX TODO
342 * refine the logic to detect the first keypress, and
343 * wait to recheck IF it was the recovery combination?
344 */
345 want_recovery = 1;
346 }
347 s = getenv("install_in_progress");
348 if ((s != NULL) && (*s != '\0')) {
349 printf("previous installation aborted, running RECOVERY\n");
350 want_recovery = 1;
351 }
352 s = getenv("install_failed");
353 if ((s != NULL) && (*s != '\0')) {
354 printf("previous installation FAILED, running RECOVERY\n");
355 want_recovery = 1;
356 }
357 s = getenv("want_recovery");
358 if ((s != NULL) && (*s != '\0')) {
359 printf("running RECOVERY according to the request\n");
360 want_recovery = 1;
361 }
362
363 if (want_recovery)
364 setenv("bootcmd", "run recovery");
365
366 /*
367 * boot the recovery system without waiting; boot the
368 * production system without waiting by default, only
369 * insert a pause (to provide a chance to get a prompt)
370 * when GPIO keys were pressed during power on
371 */
372 if (want_recovery)
373 setenv("bootdelay", "0");
374 else if (!keys)
375 setenv("bootdelay", "0");
376 else
377 setenv("bootdelay", "2");
378
379 /* get the ethernet MAC from I2C EEPROM */
380 mac_read_from_eeprom();
381
382 return 0;
383}
384
385/* setup specific IO pad configuration */
386static iopin_t ioregs_init[] = {
387 { /* LPC CS3 */
388 offsetof(struct ioctrl512x, io_control_nfc_ce0), 1,
389 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
390 IO_PIN_FMUX(1) | IO_PIN_DS(2),
391 },
392 { /* LPC CS1 */
393 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1,
394 IO_PIN_OVER_DRVSTR,
395 IO_PIN_DS(2),
396 },
397 { /* LPC CS2 */
398 offsetof(struct ioctrl512x, io_control_lpc_cs2), 1,
399 IO_PIN_OVER_DRVSTR,
400 IO_PIN_DS(2),
401 },
402 { /* LPC CS4, CS5 */
403 offsetof(struct ioctrl512x, io_control_pata_ce1), 2,
404 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
405 IO_PIN_FMUX(1) | IO_PIN_DS(2),
406 },
407 { /* SDHC CLK, CMD, D0, D1, D2, D3 */
408 offsetof(struct ioctrl512x, io_control_pata_ior), 6,
409 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
410 IO_PIN_FMUX(1) | IO_PIN_DS(2),
411 },
412 { /* GPIO keyboard */
413 offsetof(struct ioctrl512x, io_control_pci_ad30), 4,
414 IO_PIN_OVER_FMUX,
415 IO_PIN_FMUX(3),
416 },
417 { /* GPIO DN1 PF, LCD power, DN2 PF */
418 offsetof(struct ioctrl512x, io_control_pci_ad26), 3,
419 IO_PIN_OVER_FMUX,
420 IO_PIN_FMUX(3),
421 },
422 { /* GPIO reset AS-i */
423 offsetof(struct ioctrl512x, io_control_pci_ad21), 1,
424 IO_PIN_OVER_FMUX,
425 IO_PIN_FMUX(3),
426 },
427 { /* GPIO reset safety */
428 offsetof(struct ioctrl512x, io_control_pci_ad19), 1,
429 IO_PIN_OVER_FMUX,
430 IO_PIN_FMUX(3),
431 },
432 { /* GPIO reset netX */
433 offsetof(struct ioctrl512x, io_control_pci_ad16), 1,
434 IO_PIN_OVER_FMUX,
435 IO_PIN_FMUX(3),
436 },
437 { /* GPIO ma2 en */
438 offsetof(struct ioctrl512x, io_control_pci_ad15), 1,
439 IO_PIN_OVER_FMUX,
440 IO_PIN_FMUX(3),
441 },
442 { /* GPIO SD CD, SD WP */
443 offsetof(struct ioctrl512x, io_control_pci_ad08), 2,
444 IO_PIN_OVER_FMUX,
445 IO_PIN_FMUX(3),
446 },
447 { /* FEC RX DV */
448 offsetof(struct ioctrl512x, io_control_pci_ad06), 1,
449 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
450 IO_PIN_FMUX(2) | IO_PIN_DS(2),
451 },
452 { /* GPIO AS-i prog, AS-i done, LCD backlight */
453 offsetof(struct ioctrl512x, io_control_pci_ad05), 3,
454 IO_PIN_OVER_FMUX,
455 IO_PIN_FMUX(3),
456 },
457 { /* GPIO AS-i wdg */
458 offsetof(struct ioctrl512x, io_control_pci_req2), 1,
459 IO_PIN_OVER_FMUX,
460 IO_PIN_FMUX(3),
461 },
462 { /* GPIO safety wdg */
463 offsetof(struct ioctrl512x, io_control_pci_req1), 1,
464 IO_PIN_OVER_FMUX,
465 IO_PIN_FMUX(3),
466 },
467 { /* GPIO netX wdg */
468 offsetof(struct ioctrl512x, io_control_pci_req0), 1,
469 IO_PIN_OVER_FMUX,
470 IO_PIN_FMUX(3),
471 },
472 { /* GPIO IRQ powerfail */
473 offsetof(struct ioctrl512x, io_control_pci_inta), 1,
474 IO_PIN_OVER_FMUX,
475 IO_PIN_FMUX(3),
476 },
477 { /* GPIO AS-i PWRD */
478 offsetof(struct ioctrl512x, io_control_pci_frame), 1,
479 IO_PIN_OVER_FMUX,
480 IO_PIN_FMUX(3),
481 },
482 { /* GPIO LED0, LED1 */
483 offsetof(struct ioctrl512x, io_control_pci_idsel), 2,
484 IO_PIN_OVER_FMUX,
485 IO_PIN_FMUX(3),
486 },
487 { /* GPIO IRQ AS-i 1, IRQ AS-i 2, IRQ safety */
488 offsetof(struct ioctrl512x, io_control_pci_irdy), 3,
489 IO_PIN_OVER_FMUX,
490 IO_PIN_FMUX(3),
491 },
492 { /* DIU clk */
493 offsetof(struct ioctrl512x, io_control_spdif_txclk), 1,
494 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
495 IO_PIN_FMUX(2) | IO_PIN_DS(2),
496 },
497 { /* FEC TX ER, CRS */
498 offsetof(struct ioctrl512x, io_control_spdif_tx), 2,
499 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
500 IO_PIN_FMUX(1) | IO_PIN_DS(2),
501 },
502 { /* GPIO/GPT */ /* to *NOT* have the EXT IRQ0 float */
503 offsetof(struct ioctrl512x, io_control_irq0), 1,
504 IO_PIN_OVER_FMUX,
505 IO_PIN_FMUX(3),
506 },
507 { /*
508 * FEC col, tx en, tx clk, txd 0-3, mdc, rx er,
509 * rdx 3-0, mdio, rx clk
510 */
511 offsetof(struct ioctrl512x, io_control_psc0_0), 15,
512 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
513 IO_PIN_FMUX(1) | IO_PIN_DS(2),
514 },
515 /* optional: make sure PSC3 remains the serial console */
516 { /* LPC CS6 */
517 offsetof(struct ioctrl512x, io_control_psc3_4), 1,
518 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
519 IO_PIN_FMUX(1) | IO_PIN_DS(2),
520 },
521 /* make sure PSC4 remains available for SPI,
522 *BUT* PSC4_1 is a GPIO kind of SS! */
523 { /* enforce drive strength on the SPI pin */
524 offsetof(struct ioctrl512x, io_control_psc4_0), 5,
525 IO_PIN_OVER_DRVSTR,
526 IO_PIN_DS(2),
527 },
528 {
529 offsetof(struct ioctrl512x, io_control_psc4_1), 1,
530 IO_PIN_OVER_FMUX,
531 IO_PIN_FMUX(3),
532 },
533 /* optional: make sure PSC5 remains available for SPI */
534 { /* enforce drive strength on the SPI pin */
535 offsetof(struct ioctrl512x, io_control_psc5_0), 5,
536 IO_PIN_OVER_DRVSTR,
537 IO_PIN_DS(1),
538 },
539 { /* LPC TSIZ1 */
540 offsetof(struct ioctrl512x, io_control_psc6_0), 1,
541 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
542 IO_PIN_FMUX(1) | IO_PIN_DS(2),
543 },
544 { /* DIU hsync */
545 offsetof(struct ioctrl512x, io_control_psc6_1), 1,
546 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
547 IO_PIN_FMUX(2) | IO_PIN_DS(1),
548 },
549 { /* DIU vsync */
550 offsetof(struct ioctrl512x, io_control_psc6_4), 1,
551 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
552 IO_PIN_FMUX(2) | IO_PIN_DS(1),
553 },
554 { /* PSC7, part of DIU RGB */
555 offsetof(struct ioctrl512x, io_control_psc7_0), 2,
556 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
557 IO_PIN_FMUX(2) | IO_PIN_DS(1),
558 },
559 { /* PSC7, safety UART */
560 offsetof(struct ioctrl512x, io_control_psc7_2), 2,
561 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
562 IO_PIN_FMUX(0) | IO_PIN_DS(1),
563 },
564 { /* DIU (part of) RGB[] */
565 offsetof(struct ioctrl512x, io_control_psc8_3), 16,
566 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
567 IO_PIN_FMUX(2) | IO_PIN_DS(1),
568 },
569 { /* DIU data enable */
570 offsetof(struct ioctrl512x, io_control_psc11_4), 1,
571 IO_PIN_OVER_FMUX | IO_PIN_OVER_DRVSTR,
572 IO_PIN_FMUX(2) | IO_PIN_DS(1),
573 },
574 /* reduce LPB drive strength for improved EMI */
575 { /* LPC OE, LPC RW */
576 offsetof(struct ioctrl512x, io_control_lpc_oe), 2,
577 IO_PIN_OVER_DRVSTR,
578 IO_PIN_DS(2),
579 },
580 { /* LPC AX03 through LPC AD00 */
581 offsetof(struct ioctrl512x, io_control_lpc_ax03), 36,
582 IO_PIN_OVER_DRVSTR,
583 IO_PIN_DS(2),
584 },
585 { /* LPC CS5 */
586 offsetof(struct ioctrl512x, io_control_pata_ce2), 1,
587 IO_PIN_OVER_DRVSTR,
588 IO_PIN_DS(2),
589 },
590 { /* SDHC CLK */
591 offsetof(struct ioctrl512x, io_control_nfc_wp), 1,
592 IO_PIN_OVER_DRVSTR,
593 IO_PIN_DS(2),
594 },
595 { /* SDHC DATA */
596 offsetof(struct ioctrl512x, io_control_nfc_ale), 4,
597 IO_PIN_OVER_DRVSTR,
598 IO_PIN_DS(2),
599 },
600};
601
602int checkboard(void)
603{
604 puts("Board: ifm AC14xx\n");
605
606 /* initialize function mux & slew rate IO inter alia on IO Pins */
607 iopin_initialize_bits(ioregs_init, ARRAY_SIZE(ioregs_init));
608
609 return 0;
610}
611
612#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
613void ft_board_setup(void *blob, bd_t *bd)
614{
615 ft_cpu_setup(blob, bd);
616}
617#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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