[thirdparty/u-boot.git] / board / imgtec / xilfpga / xilfpga.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Imagination Technologies MIPSfpga platform code
 *
 * Copyright (C) 2016, Imagination Technologies Ltd.
 *
 * Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
 *
 */

#include <common.h>
#include <init.h>
#include <asm/global_data.h>

DECLARE_GLOBAL_DATA_PTR;

/* initialize the DDR Controller and PHY */
int dram_init(void)
{
	/* MIG IP block is smart and doesn't need SW
	 * to do any init */
	gd->ram_size = CFG_SYS_SDRAM_SIZE;	/* in bytes */

	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
ebf2b9e3 ZLK	2	/*
	3	* Imagination Technologies MIPSfpga platform code
	4	*
	5	* Copyright (C) 2016, Imagination Technologies Ltd.
	6	*
	7	* Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com>
	8	*
ebf2b9e3 ZLK	9	*/
ebf2b9e3 ZLK	10
d678a59d	11	#include <common.h>
691d719d	12	#include <init.h>
401d1c4f	13	#include <asm/global_data.h>
ebf2b9e3	14
088454cd SG	15	DECLARE_GLOBAL_DATA_PTR;
088454cd SG	16
ebf2b9e3	17	/* initialize the DDR Controller and PHY */
f1683aa7	18	int dram_init(void)
ebf2b9e3 ZLK	19	{
	20	/* MIG IP block is smart and doesn't need SW
	21	* to do any init */
aa6e94de	22	gd->ram_size = CFG_SYS_SDRAM_SIZE; /* in bytes */
088454cd SG	23
088454cd SG	24	return 0;
ebf2b9e3	25	}