]> git.ipfire.org Git - people/ms/u-boot.git/blame - board/ixdp425/ixdp425.c
Merge branch 'testing' into working
[people/ms/u-boot.git] / board / ixdp425 / ixdp425.c
CommitLineData
2d5b561e 1/*
ba94a1bb
WD
2 * (C) Copyright 2006
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
2d5b561e
WD
5 * (C) Copyright 2002
6 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
7 *
8 * (C) Copyright 2002
9 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
10 * Marius Groeger <mgroeger@sysgo.de>
11 *
12 * See file CREDITS for list of people who contributed to this
13 * project.
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
2d5b561e 31#include <common.h>
ba94a1bb
WD
32#include <command.h>
33#include <malloc.h>
34#include <asm/arch/ixp425.h>
2d5b561e 35
d87080b7 36DECLARE_GLOBAL_DATA_PTR;
2d5b561e
WD
37
38/*
39 * Miscelaneous platform dependent initialisations
40 */
289f932c 41int board_post_init (void)
2d5b561e
WD
42{
43 return (0);
44}
45
289f932c 46int board_init (void)
2d5b561e 47{
2d5b561e 48 /* arch number of IXDP */
731215eb 49 gd->bd->bi_arch_number = MACH_TYPE_IXDP425;
2d5b561e
WD
50
51 /* adress of boot parameters */
52 gd->bd->bi_boot_params = 0x00000100;
53
ba94a1bb
WD
54#ifdef CONFIG_IXDPG425
55 /* arch number of IXDP */
56 gd->bd->bi_arch_number = MACH_TYPE_IXDPG425;
57
58 /*
59 * Get realtek RTL8305 switch and SLIC out of reset
60 */
61 GPIO_OUTPUT_SET(CFG_GPIO_SWITCH_RESET_N);
62 GPIO_OUTPUT_ENABLE(CFG_GPIO_SWITCH_RESET_N);
63 GPIO_OUTPUT_SET(CFG_GPIO_SLIC_RESET_N);
64 GPIO_OUTPUT_ENABLE(CFG_GPIO_SLIC_RESET_N);
65
66 /*
67 * Setup GPIO's for PCI INTA & INTB
68 */
69 GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTA_N);
70 GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTA_N);
71 GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTB_N);
72 GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTB_N);
73
74 /*
75 * Setup GPIO's for 33MHz clock output
76 */
77 *IXP425_GPIO_GPCLKR = 0x01FF01FF;
78 GPIO_OUTPUT_ENABLE(CFG_GPIO_PCI_CLK);
79 GPIO_OUTPUT_ENABLE(CFG_GPIO_EXTBUS_CLK);
80#endif
81
2d5b561e
WD
82 return 0;
83}
84
ba94a1bb
WD
85/*
86 * Check Board Identity
87 */
88int checkboard(void)
89{
90 char *s = getenv("serial#");
91
92#ifdef CONFIG_IXDPG425
93 puts("Board: IXDPG425 - Intel Network Gateway Reference Platform");
94#else
95 puts("Board: IXDP425 - Intel Development Platform");
96#endif
97
98 if (s != NULL) {
99 puts(", serial# ");
100 puts(s);
101 }
102 putc('\n');
103
104 return (0);
105}
289f932c
WD
106
107int dram_init (void)
2d5b561e 108{
2d5b561e
WD
109 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
110 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
111
112 return (0);
113}
289f932c 114
c508a4ce 115#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
a1191902 116extern struct pci_controller hose;
3706ba1a 117extern void pci_ixp_init(struct pci_controller * hose);
289f932c 118
a1191902
WD
119void pci_init_board(void)
120{
289f932c
WD
121 extern void pci_ixp_init (struct pci_controller *hose);
122
a1191902 123 pci_ixp_init(&hose);
a1191902 124}
ba94a1bb 125#endif