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db01a2ea WD |
1 | /* |
2 | * Copyright (c) 2004 Picture Elements, Inc. | |
3 | * Stephen Williams (steve@icarus.com) | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
db01a2ea WD |
6 | */ |
7 | #ident "$Id:$" | |
8 | ||
9 | # include <common.h> | |
10 | # include <pci.h> | |
11 | # include "jse_priv.h" | |
12 | ||
13 | /* | |
14 | * The JSE board has an Intel 21555 non-transparent bridge for | |
15 | * communication with the host. We need to render it harmless on the | |
16 | * JSE side, but leave it alone on the host (primary) side. Normally, | |
17 | * this will all be done before the host BIOS can gain access to the | |
18 | * board, due to the Primary Access Lockout bit. | |
19 | * | |
20 | * The host_bridge_init function is called as a late initialization | |
21 | * function, after most of the board is set up, including a PCI scan. | |
22 | */ | |
23 | ||
24 | void host_bridge_init (void) | |
25 | { | |
26 | /* The bridge chip is at a fixed location. */ | |
27 | pci_dev_t dev = PCI_BDF (0, 10, 0); | |
28 | ||
cce625e5 WD |
29 | /* Set PCI Class code -- |
30 | The primary side sees this class code at 0x08 in the | |
31 | primary config space. This must be something other then a | |
32 | bridge, or MS Windows starts doing weird stuff to me. */ | |
33 | pci_write_config_dword (dev, 0x48, 0x04800000); | |
db01a2ea WD |
34 | |
35 | /* Set subsystem ID -- | |
36 | The primary side sees this value at 0x2c. We set it here so | |
37 | that the host can tell what sort of device this is: | |
38 | We are a Picture Elements [0x12c5] JSE [0x008a]. */ | |
39 | pci_write_config_dword (dev, 0x6c, 0x008a12c5); | |
40 | ||
41 | /* Downstream (Primary-to-Secondary) BARs are set up mostly | |
42 | off. We need only the Memory-0 Bar so that the host can get | |
43 | at the CSR region to set up tables and the lot. */ | |
44 | ||
45 | /* Downstream Memory 0 setup (4K for CSR) */ | |
46 | pci_write_config_dword (dev, 0xac, 0xfffff000); | |
47 | /* Downstream Memory 1 setup (off) */ | |
48 | pci_write_config_dword (dev, 0xb0, 0x00000000); | |
49 | /* Downstream Memory 2 setup (off) */ | |
50 | pci_write_config_dword (dev, 0xb4, 0x00000000); | |
51 | /* Downstream Memory 3 setup (off) */ | |
52 | pci_write_config_dword (dev, 0xb8, 0x00000000); | |
53 | ||
54 | /* Upstream (Secondary-to-Primary) BARs are used to get at | |
55 | host memory from the JSE card. Create two regions: a small | |
56 | one to manage individual word reads/writes, and a larger | |
57 | one for doing bulk frame moves. */ | |
58 | ||
59 | /* Upstream Memory 0 Setup -- (BAR2) 4K non-prefetchable */ | |
60 | pci_write_config_dword (dev, 0xc4, 0xfffff000); | |
61 | /* Upstream Memory 1 setup -- (BAR3) 4K non-prefetchable */ | |
62 | pci_write_config_dword (dev, 0xc8, 0xfffff000); | |
63 | ||
64 | /* Upstream Memory 2 (BAR4) uses page translation, and is set | |
65 | up in CCR1. Configure for 4K pages. */ | |
66 | ||
67 | /* Set CCR1,0 reigsters. This clears the Primary PCI Lockout | |
68 | bit as well, so we are done configuring after this | |
69 | point. Therefore, this must be the last step. | |
70 | ||
71 | CC1[15:12]= 0 (disable I2O message unit) | |
72 | CC1[11:8] = 0x5 (4K page size) | |
73 | CC0[11] = 1 (Secondary Clock Disable: disable clock) | |
74 | CC0[10] = 0 (Primary Access Lockout: allow primary access) | |
75 | */ | |
76 | pci_write_config_dword (dev, 0xcc, 0x05000800); | |
77 | } |