[people/ms/u-boot.git] / board / keymile / mgsuvd / mgsuvd.c

/*
 * (C) Copyright 2007
 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#if 0
#define DEBUG
#endif

#include <common.h>
#include <mpc8xx.h>

#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
#include <libfdt.h>
#endif

extern int ivm_read_eeprom (void);

DECLARE_GLOBAL_DATA_PTR;

const uint sdram_table[] =
{
	0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x0ff77c00,
	0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	/* 0x08 Burst Read */
	0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
	0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
	/* 0x10 Load mode register */
	0x0ffffc34, 0x0ff57c04, 0x0ffffc04, 0x1ffffc05,
	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	/* 0x18 Single Write */
	0x0f07fc04, 0x0ffffc00, 0x00bd7c04, 0x0ffffc04,
	0x0ff77c04, 0x1ffffc05, 0xfffffc04, 0xfffffc04,
	/* 0x20 Burst Write */
	0x0f07fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
	0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff77c04,
	0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	/* 0x30 Precharge all and Refresh */
	0x0ff77c04, 0x0ffffc04, 0x0ff5fc84, 0x0ffffc04,
	0x0ffffc04, 0x0ffffc84, 0x1ffffc05, 0xfffffc04,
	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	/* 0x3C Exception */
	0x7ffffc04, 0xfffffc07, 0xfffffc04, 0xfffffc04,
};

int checkboard (void)
{
	puts ("Board: Keymile mgsuvd\n");
	return (0);
}

phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size;

	upmconfig (UPMB, (uint *) sdram_table,
			   sizeof (sdram_table) / sizeof (uint));

	/*
	 * Preliminary prescaler for refresh (depends on number of
	 * banks): This value is selected for four cycles every 62.4 us
	 * with two SDRAM banks or four cycles every 31.2 us with one
	 * bank. It will be adjusted after memory sizing.
	 */
	memctl->memc_mptpr = CONFIG_SYS_MPTPR;

	/*
	 * The following value is used as an address (i.e. opcode) for
	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
	 * the port size is 32bit the SDRAM does NOT "see" the lower two
	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
	 * MICRON SDRAMs:
	 * ->    0 00 010 0 010
	 *       |  |   | |   +- Burst Length = 4
	 *       |  |   | +----- Burst Type   = Sequential
	 *       |  |   +------- CAS Latency  = 2
	 *       |  +----------- Operating Mode = Standard
	 *       +-------------- Write Burst Mode = Programmed Burst Length
	 */
	memctl->memc_mar = CONFIG_SYS_MAR;

	/*
	 * Map controller banks 1 to the SDRAM banks 1 at
	 * preliminary addresses - these have to be modified after the
	 * SDRAM size has been determined.
	 */
	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;

	memctl->memc_mbmr = CONFIG_SYS_MBMR & (~(MBMR_PTBE));	/* no refresh yet */

	udelay (200);

	/* perform SDRAM initializsation sequence */

	memctl->memc_mcr = 0x80802830;	/* SDRAM bank 0 */
	udelay (1);
	memctl->memc_mcr = 0x80802110;	/* SDRAM bank 0 - execute twice */
	udelay (1);

	memctl->memc_mbmr |= MBMR_PTBE;	/* enable refresh */

	udelay (1000);

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 */
	size =  get_ram_size(SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);

	udelay (1000);

	debug ("SDRAM Bank 0: %ld MB\n", size >> 20);

	return (size);
}

/*
 * Early board initalization.
 */
int board_early_init_r(void)
{
	/* setup the UPIOx */
	*(char *)(CONFIG_SYS_PIGGY_BASE + 0x02) = 0xc0;
	*(char *)(CONFIG_SYS_PIGGY_BASE + 0x03) = 0x35;
	return 0;
}

int hush_init_var (void)
{
	ivm_read_eeprom ();
	return 0;
}

#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
/*
 * update "memory" property in the blob
 */
void ft_blob_update(void *blob, bd_t *bd)
{
	int ret, nodeoffset = 0;
	ulong brg_data[1] = {0};
	ulong memory_data[2] = {0};
	ulong flash_data[4] = {0};

	memory_data[0] = cpu_to_be32(bd->bi_memstart);
	memory_data[1] = cpu_to_be32(bd->bi_memsize);

		nodeoffset = fdt_path_offset (blob, "/memory");
		if (nodeoffset >= 0) {
			ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
						sizeof(memory_data));
		if (ret < 0)
			printf("ft_blob_update(): cannot set /memory/reg "
				"property err:%s\n", fdt_strerror(ret));
		}
		else {
			/* memory node is required in dts */
			printf("ft_blob_update(): cannot find /memory node "
			"err:%s\n", fdt_strerror(nodeoffset));
	}

	flash_data[2] = cpu_to_be32(bd->bi_flashstart);
	flash_data[3] = cpu_to_be32(bd->bi_flashsize);
	nodeoffset = fdt_path_offset (blob, "/localbus");
	if (nodeoffset >= 0) {
		ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data,
					sizeof(flash_data));
	if (ret < 0)
		printf("ft_blob_update(): cannot set /localbus/ranges "
			"property err:%s\n", fdt_strerror(ret));
	}
	else {
		/* memory node is required in dts */
		printf("ft_blob_update(): cannot find /localbus node "
		"err:%s\n", fdt_strerror(nodeoffset));
	}
	/* BRG */
	brg_data[0] = cpu_to_be32(bd->bi_busfreq);
	nodeoffset = fdt_path_offset (blob, "/soc/cpm");
	if (nodeoffset >= 0) {
		ret = fdt_setprop(blob, nodeoffset, "brg-frequency", brg_data,
					sizeof(brg_data));
	if (ret < 0)
		printf("ft_blob_update(): cannot set /soc/cpm/brg-frequency "
			"property err:%s\n", fdt_strerror(ret));
	}
	else {
		/* memory node is required in dts */
		printf("ft_blob_update(): cannot find /soc/cpm node "
		"err:%s\n", fdt_strerror(nodeoffset));
	}
	/* MAC Adresse */
	nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet");
	if (nodeoffset >= 0) {
		ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr,
					sizeof(uchar) * 6);
	if (ret < 0)
		printf("ft_blob_update(): cannot set /soc/cpm/scc/mac-address "
			"property err:%s\n", fdt_strerror(ret));
	}
	else {
		/* memory node is required in dts */
		printf("ft_blob_update(): cannot find /soc/cpm/ethernet node "
		"err:%s\n", fdt_strerror(nodeoffset));
	}
}

void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup( blob, bd);
	ft_blob_update(blob, bd);
}
#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */

int i2c_soft_read_pin (void)
{
	int val;

	*(unsigned short *)(I2C_BASE_DIR) &=  ~SDA_CONF;
	udelay(1);
	val = *(unsigned char *)(I2C_BASE_PORT);

	return ((val & SDA_BIT) == SDA_BIT);
}
Commit	Line	Data
381e4e63 HS	1	/*
	2	* (C) Copyright 2007
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#if 0
	25	#define DEBUG
	26	#endif
	27
	28	#include <common.h>
	29	#include <mpc8xx.h>
	30
	31	#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
	32	#include <libfdt.h>
	33	#endif
	34
8f64da7f HS	35	extern int ivm_read_eeprom (void);
8f64da7f HS	36
381e4e63 HS	37	DECLARE_GLOBAL_DATA_PTR;
	38
	39	const uint sdram_table[] =
	40	{
	41	0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x0ff77c00,
	42	0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	43	/* 0x08 Burst Read */
	44	0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
	45	0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
	46	/* 0x10 Load mode register */
	47	0x0ffffc34, 0x0ff57c04, 0x0ffffc04, 0x1ffffc05,
	48	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	49	/* 0x18 Single Write */
	50	0x0f07fc04, 0x0ffffc00, 0x00bd7c04, 0x0ffffc04,
	51	0x0ff77c04, 0x1ffffc05, 0xfffffc04, 0xfffffc04,
	52	/* 0x20 Burst Write */
	53	0x0f07fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
	54	0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff77c04,
	55	0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	56	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	57	/* 0x30 Precharge all and Refresh */
	58	0x0ff77c04, 0x0ffffc04, 0x0ff5fc84, 0x0ffffc04,
	59	0x0ffffc04, 0x0ffffc84, 0x1ffffc05, 0xfffffc04,
	60	0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
	61	/* 0x3C Exception */
	62	0x7ffffc04, 0xfffffc07, 0xfffffc04, 0xfffffc04,
	63	};
	64
	65	int checkboard (void)
	66	{
	67	puts ("Board: Keymile mgsuvd\n");
	68	return (0);
	69	}
	70
9973e3c6	71	phys_size_t initdram (int board_type)
381e4e63	72	{
6d0f6bcf	73	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
381e4e63 HS	74	volatile memctl8xx_t *memctl = &immap->im_memctl;
	75	long int size;
	76
	77	upmconfig (UPMB, (uint *) sdram_table,
	78	sizeof (sdram_table) / sizeof (uint));
	79
	80	/*
	81	* Preliminary prescaler for refresh (depends on number of
	82	* banks): This value is selected for four cycles every 62.4 us
	83	* with two SDRAM banks or four cycles every 31.2 us with one
	84	* bank. It will be adjusted after memory sizing.
	85	*/
6d0f6bcf	86	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
381e4e63 HS	87
	88	/*
	89	* The following value is used as an address (i.e. opcode) for
	90	* the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
	91	* the port size is 32bit the SDRAM does NOT "see" the lower two
	92	* address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
	93	* MICRON SDRAMs:
	94	* -> 0 00 010 0 010
	95	* \| \| \| \| +- Burst Length = 4
	96	* \| \| \| +----- Burst Type = Sequential
	97	* \| \| +------- CAS Latency = 2
	98	* \| +----------- Operating Mode = Standard
	99	* +-------------- Write Burst Mode = Programmed Burst Length
	100	*/
6d0f6bcf	101	memctl->memc_mar = CONFIG_SYS_MAR;
381e4e63 HS	102
	103	/*
	104	* Map controller banks 1 to the SDRAM banks 1 at
	105	* preliminary addresses - these have to be modified after the
	106	* SDRAM size has been determined.
	107	*/
6d0f6bcf JCPV	108	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
6d0f6bcf JCPV	109	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
381e4e63	110
6d0f6bcf	111	memctl->memc_mbmr = CONFIG_SYS_MBMR & (~(MBMR_PTBE)); /* no refresh yet */
381e4e63 HS	112
	113	udelay (200);
	114
	115	/* perform SDRAM initializsation sequence */
	116
	117	memctl->memc_mcr = 0x80802830; /* SDRAM bank 0 */
	118	udelay (1);
	119	memctl->memc_mcr = 0x80802110; /* SDRAM bank 0 - execute twice */
	120	udelay (1);
	121
	122	memctl->memc_mbmr \|= MBMR_PTBE; /* enable refresh */
	123
	124	udelay (1000);
	125
	126	/*
	127	* Check Bank 0 Memory Size for re-configuration
	128	*
	129	*/
	130	size = get_ram_size(SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
	131
	132	udelay (1000);
	133
	134	debug ("SDRAM Bank 0: %ld MB\n", size >> 20);
	135
	136	return (size);
	137	}
	138
82afabfe HS	139	/*
	140	* Early board initalization.
	141	*/
	142	int board_early_init_r(void)
	143	{
	144	/* setup the UPIOx */
6d0f6bcf JCPV	145	(char )(CONFIG_SYS_PIGGY_BASE + 0x02) = 0xc0;
6d0f6bcf JCPV	146	(char )(CONFIG_SYS_PIGGY_BASE + 0x03) = 0x35;
82afabfe HS	147	return 0;
	148	}
	149
8f64da7f HS	150	int hush_init_var (void)
	151	{
	152	ivm_read_eeprom ();
	153	return 0;
	154	}
	155
381e4e63 HS	156	#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
	157	/*
	158	* update "memory" property in the blob
	159	*/
	160	void ft_blob_update(void blob, bd_t bd)
	161	{
	162	int ret, nodeoffset = 0;
	163	ulong brg_data[1] = {0};
	164	ulong memory_data[2] = {0};
	165	ulong flash_data[4] = {0};
	166
	167	memory_data[0] = cpu_to_be32(bd->bi_memstart);
	168	memory_data[1] = cpu_to_be32(bd->bi_memsize);
	169
	170	nodeoffset = fdt_path_offset (blob, "/memory");
	171	if (nodeoffset >= 0) {
	172	ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
	173	sizeof(memory_data));
	174	if (ret < 0)
27269417	175	printf("ft_blob_update(): cannot set /memory/reg "
381e4e63 HS	176	"property err:%s\n", fdt_strerror(ret));
	177	}
	178	else {
	179	/* memory node is required in dts */
	180	printf("ft_blob_update(): cannot find /memory node "
	181	"err:%s\n", fdt_strerror(nodeoffset));
	182	}
	183
	184	flash_data[2] = cpu_to_be32(bd->bi_flashstart);
	185	flash_data[3] = cpu_to_be32(bd->bi_flashsize);
	186	nodeoffset = fdt_path_offset (blob, "/localbus");
	187	if (nodeoffset >= 0) {
	188	ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data,
	189	sizeof(flash_data));
	190	if (ret < 0)
27269417	191	printf("ft_blob_update(): cannot set /localbus/ranges "
381e4e63 HS	192	"property err:%s\n", fdt_strerror(ret));
	193	}
	194	else {
	195	/* memory node is required in dts */
	196	printf("ft_blob_update(): cannot find /localbus node "
	197	"err:%s\n", fdt_strerror(nodeoffset));
	198	}
	199	/* BRG */
	200	brg_data[0] = cpu_to_be32(bd->bi_busfreq);
82afabfe	201	nodeoffset = fdt_path_offset (blob, "/soc/cpm");
381e4e63 HS	202	if (nodeoffset >= 0) {
	203	ret = fdt_setprop(blob, nodeoffset, "brg-frequency", brg_data,
	204	sizeof(brg_data));
	205	if (ret < 0)
27269417	206	printf("ft_blob_update(): cannot set /soc/cpm/brg-frequency "
381e4e63 HS	207	"property err:%s\n", fdt_strerror(ret));
	208	}
	209	else {
	210	/* memory node is required in dts */
82afabfe	211	printf("ft_blob_update(): cannot find /soc/cpm node "
381e4e63 HS	212	"err:%s\n", fdt_strerror(nodeoffset));
	213	}
	214	/* MAC Adresse */
82afabfe	215	nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet");
381e4e63 HS	216	if (nodeoffset >= 0) {
	217	ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr,
	218	sizeof(uchar) * 6);
	219	if (ret < 0)
27269417	220	printf("ft_blob_update(): cannot set /soc/cpm/scc/mac-address "
381e4e63 HS	221	"property err:%s\n", fdt_strerror(ret));
	222	}
	223	else {
	224	/* memory node is required in dts */
82afabfe	225	printf("ft_blob_update(): cannot find /soc/cpm/ethernet node "
381e4e63 HS	226	"err:%s\n", fdt_strerror(nodeoffset));
	227	}
	228	}
	229
	230	void ft_board_setup(void blob, bd_t bd)
	231	{
	232	ft_cpu_setup( blob, bd);
	233	ft_blob_update(blob, bd);
	234	}
	235	#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
9661bf9d HS	236
	237	int i2c_soft_read_pin (void)
	238	{
	239	int val;
	240
	241	(unsigned short )(I2C_BASE_DIR) &= ~SDA_CONF;
	242	udelay(1);
	243	val = (unsigned char )(I2C_BASE_PORT);
	244
	245	return ((val & SDA_BIT) == SDA_BIT);
	246	}