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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
f91c09ac MV |
2 | /* |
3 | * Novena SPL | |
4 | * | |
5 | * Copyright (C) 2014 Marek Vasut <marex@denx.de> | |
f91c09ac MV |
6 | */ |
7 | ||
8 | #include <common.h> | |
d96c2604 | 9 | #include <clock_legacy.h> |
5255932f | 10 | #include <init.h> |
f91c09ac MV |
11 | #include <asm/io.h> |
12 | #include <asm/arch/clock.h> | |
13 | #include <asm/arch/iomux.h> | |
14 | #include <asm/arch/mx6-ddr.h> | |
15 | #include <asm/arch/mx6-pins.h> | |
16 | #include <asm/arch/sys_proto.h> | |
17 | #include <asm/gpio.h> | |
552a848e SB |
18 | #include <asm/mach-imx/boot_mode.h> |
19 | #include <asm/mach-imx/iomux-v3.h> | |
20 | #include <asm/mach-imx/mxc_i2c.h> | |
7d29acd9 | 21 | #include <asm/arch/crm_regs.h> |
f91c09ac MV |
22 | #include <i2c.h> |
23 | #include <mmc.h> | |
e37ac717 | 24 | #include <fsl_esdhc_imx.h> |
f91c09ac MV |
25 | #include <spl.h> |
26 | ||
27 | #include <asm/arch/mx6-ddr.h> | |
28 | ||
d59d7b91 MV |
29 | #include "novena.h" |
30 | ||
f91c09ac MV |
31 | #define UART_PAD_CTRL \ |
32 | (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
33 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ | |
34 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
35 | ||
36 | #define USDHC_PAD_CTRL \ | |
37 | (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
38 | PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ | |
39 | PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) | |
40 | ||
41 | #define ENET_PAD_CTRL \ | |
42 | (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
43 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ | |
44 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | |
45 | ||
b99ed276 ND |
46 | #define ENET_PHY_CFG_PAD_CTRL \ |
47 | (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
48 | PAD_CTL_PUS_22K_UP | PAD_CTL_HYS) | |
49 | ||
f91c09ac MV |
50 | #define RGMII_PAD_CTRL \ |
51 | (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
52 | PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | |
53 | ||
54 | #define SPI_PAD_CTRL \ | |
55 | (PAD_CTL_HYS | \ | |
56 | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED | \ | |
57 | PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) | |
58 | ||
59 | #define I2C_PAD_CTRL \ | |
60 | (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
61 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ | |
62 | PAD_CTL_DSE_240ohm | PAD_CTL_HYS | \ | |
63 | PAD_CTL_ODE) | |
64 | ||
65 | #define BUTTON_PAD_CTRL \ | |
66 | (PAD_CTL_PKE | PAD_CTL_PUE | \ | |
67 | PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ | |
68 | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) | |
69 | ||
70 | #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) | |
71 | ||
f91c09ac MV |
72 | /* |
73 | * Audio | |
74 | */ | |
75 | static iomux_v3_cfg_t audio_pads[] = { | |
76 | /* AUD_PWRON */ | |
77 | MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
78 | }; | |
79 | ||
80 | static void novena_spl_setup_iomux_audio(void) | |
81 | { | |
82 | imx_iomux_v3_setup_multiple_pads(audio_pads, ARRAY_SIZE(audio_pads)); | |
83 | gpio_direction_output(NOVENA_AUDIO_PWRON, 1); | |
84 | } | |
85 | ||
86 | /* | |
87 | * ENET | |
88 | */ | |
89 | static iomux_v3_cfg_t enet_pads1[] = { | |
90 | MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
91 | MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
92 | MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), | |
93 | MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), | |
94 | MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), | |
95 | MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), | |
96 | MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), | |
97 | MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), | |
98 | MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), | |
b99ed276 ND |
99 | |
100 | /* pin 35, PHY_AD2 */ | |
101 | MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), | |
102 | /* pin 32, MODE0 */ | |
103 | MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), | |
104 | /* pin 31, MODE1 */ | |
105 | MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), | |
106 | /* pin 28, MODE2 */ | |
107 | MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), | |
108 | /* pin 27, MODE3 */ | |
109 | MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), | |
110 | /* pin 33, CLK125_EN */ | |
111 | MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(ENET_PHY_CFG_PAD_CTRL), | |
112 | ||
f91c09ac MV |
113 | /* pin 42 PHY nRST */ |
114 | MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
115 | }; | |
116 | ||
117 | static iomux_v3_cfg_t enet_pads2[] = { | |
118 | MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(RGMII_PAD_CTRL), | |
119 | MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(RGMII_PAD_CTRL), | |
120 | MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(RGMII_PAD_CTRL), | |
121 | MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(RGMII_PAD_CTRL), | |
122 | MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(RGMII_PAD_CTRL), | |
123 | MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(RGMII_PAD_CTRL), | |
124 | }; | |
125 | ||
126 | static void novena_spl_setup_iomux_enet(void) | |
127 | { | |
128 | imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); | |
129 | ||
b99ed276 | 130 | /* Assert Ethernet PHY nRST */ |
f91c09ac | 131 | gpio_direction_output(IMX_GPIO_NR(3, 23), 0); |
f91c09ac | 132 | |
b99ed276 ND |
133 | /* |
134 | * Use imx6 internal pull-ups to drive PHY mode pins during PHY reset | |
135 | * de-assertion. The intention is to use weak signal drivers (pull-ups) | |
136 | * to prevent the conflict between PHY pins becoming outputs after | |
137 | * reset and imx6 still driving the pins. The issue is described in PHY | |
138 | * datasheet, p.14 | |
139 | */ | |
140 | gpio_direction_input(IMX_GPIO_NR(6, 30)); /* PHY_AD2 = 1 */ | |
141 | gpio_direction_input(IMX_GPIO_NR(6, 25)); /* MODE0 = 1 */ | |
142 | gpio_direction_input(IMX_GPIO_NR(6, 27)); /* MODE1 = 1 */ | |
143 | gpio_direction_input(IMX_GPIO_NR(6, 28)); /* MODE2 = 1 */ | |
144 | gpio_direction_input(IMX_GPIO_NR(6, 29)); /* MODE3 = 1 */ | |
145 | gpio_direction_input(IMX_GPIO_NR(6, 24)); /* CLK125_EN = 1 */ | |
146 | ||
147 | /* Following reset timing (p.53, fig.8 from the PHY datasheet) */ | |
148 | mdelay(10); | |
149 | ||
150 | /* De-assert Ethernet PHY nRST */ | |
151 | gpio_set_value(IMX_GPIO_NR(3, 23), 1); | |
152 | ||
153 | /* PHY is now configured, connect FEC to the pads */ | |
f91c09ac | 154 | imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); |
b99ed276 ND |
155 | |
156 | /* | |
157 | * PHY datasheet recommends on p.53 to wait at least 100us after reset | |
158 | * before using MII, so we enforce the delay here | |
159 | */ | |
160 | udelay(100); | |
f91c09ac MV |
161 | } |
162 | ||
163 | /* | |
164 | * FPGA | |
165 | */ | |
166 | static iomux_v3_cfg_t fpga_pads[] = { | |
167 | /* FPGA_RESET_N */ | |
168 | MX6_PAD_DISP0_DAT13__GPIO5_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
169 | }; | |
170 | ||
171 | static void novena_spl_setup_iomux_fpga(void) | |
172 | { | |
173 | imx_iomux_v3_setup_multiple_pads(fpga_pads, ARRAY_SIZE(fpga_pads)); | |
174 | gpio_direction_output(NOVENA_FPGA_RESET_N_GPIO, 0); | |
175 | } | |
176 | ||
177 | /* | |
178 | * GPIO Button | |
179 | */ | |
180 | static iomux_v3_cfg_t button_pads[] = { | |
181 | /* Debug */ | |
182 | MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(BUTTON_PAD_CTRL), | |
183 | }; | |
184 | ||
185 | static void novena_spl_setup_iomux_buttons(void) | |
186 | { | |
187 | imx_iomux_v3_setup_multiple_pads(button_pads, ARRAY_SIZE(button_pads)); | |
188 | } | |
189 | ||
190 | /* | |
191 | * I2C | |
192 | */ | |
193 | /* | |
194 | * I2C1: | |
195 | * 0x1d ... MMA7455L | |
196 | * 0x30 ... SO-DIMM temp sensor | |
197 | * 0x44 ... STMPE610 | |
198 | * 0x50 ... SO-DIMM ID | |
199 | */ | |
200 | struct i2c_pads_info i2c_pad_info0 = { | |
201 | .scl = { | |
202 | .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC, | |
203 | .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC, | |
204 | .gp = IMX_GPIO_NR(3, 21) | |
205 | }, | |
206 | .sda = { | |
207 | .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC, | |
208 | .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC, | |
209 | .gp = IMX_GPIO_NR(3, 28) | |
210 | } | |
211 | }; | |
212 | ||
213 | /* | |
214 | * I2C2: | |
215 | * 0x08 ... PMIC | |
216 | * 0x3a ... HDMI DCC | |
217 | * 0x50 ... HDMI DCC | |
218 | */ | |
219 | static struct i2c_pads_info i2c_pad_info1 = { | |
220 | .scl = { | |
221 | .i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC, | |
222 | .gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC, | |
223 | .gp = IMX_GPIO_NR(2, 30) | |
224 | }, | |
225 | .sda = { | |
226 | .i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC, | |
227 | .gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC, | |
228 | .gp = IMX_GPIO_NR(3, 16) | |
229 | } | |
230 | }; | |
231 | ||
232 | /* | |
233 | * I2C3: | |
234 | * 0x11 ... ES8283 | |
235 | * 0x50 ... LCD EDID | |
236 | * 0x56 ... EEPROM | |
237 | */ | |
238 | static struct i2c_pads_info i2c_pad_info2 = { | |
239 | .scl = { | |
240 | .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, | |
241 | .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, | |
242 | .gp = IMX_GPIO_NR(3, 17) | |
243 | }, | |
244 | .sda = { | |
245 | .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, | |
246 | .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, | |
247 | .gp = IMX_GPIO_NR(3, 18) | |
248 | } | |
249 | }; | |
250 | ||
251 | static void novena_spl_setup_iomux_i2c(void) | |
252 | { | |
253 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); | |
254 | setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); | |
255 | setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); | |
256 | } | |
257 | ||
258 | /* | |
259 | * PCI express | |
260 | */ | |
261 | #ifdef CONFIG_CMD_PCI | |
262 | static iomux_v3_cfg_t pcie_pads[] = { | |
263 | /* "Reset" pin */ | |
264 | MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
265 | /* "Power on" pin */ | |
266 | MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
267 | /* "Wake up" pin (input) */ | |
268 | MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
269 | /* "Disable endpoint" (rfkill) pin */ | |
270 | MX6_PAD_EIM_A22__GPIO2_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
271 | }; | |
272 | ||
273 | static void novena_spl_setup_iomux_pcie(void) | |
274 | { | |
275 | imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads)); | |
276 | ||
277 | /* Ensure PCIe is powered down */ | |
278 | gpio_direction_output(NOVENA_PCIE_POWER_ON_GPIO, 0); | |
279 | ||
280 | /* Put the card into reset */ | |
281 | gpio_direction_output(NOVENA_PCIE_RESET_GPIO, 0); | |
282 | ||
283 | /* Input signal to wake system from mPCIe card */ | |
284 | gpio_direction_input(NOVENA_PCIE_WAKE_UP_GPIO); | |
285 | ||
286 | /* Drive RFKILL high, to ensure the radio is turned on */ | |
287 | gpio_direction_output(NOVENA_PCIE_DISABLE_GPIO, 1); | |
288 | } | |
289 | #else | |
290 | static inline void novena_spl_setup_iomux_pcie(void) {} | |
291 | #endif | |
292 | ||
293 | /* | |
294 | * SDHC | |
295 | */ | |
296 | static iomux_v3_cfg_t usdhc2_pads[] = { | |
297 | MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
298 | MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
299 | MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
300 | MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
301 | MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
302 | MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
303 | MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */ | |
304 | MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ | |
305 | }; | |
306 | ||
307 | static iomux_v3_cfg_t usdhc3_pads[] = { | |
308 | MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
309 | MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
310 | MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
311 | MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
312 | MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
313 | MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | |
314 | }; | |
315 | ||
316 | static void novena_spl_setup_iomux_sdhc(void) | |
317 | { | |
318 | imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); | |
319 | imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); | |
320 | ||
321 | /* Big SD write-protect and card-detect */ | |
322 | gpio_direction_input(IMX_GPIO_NR(1, 2)); | |
323 | gpio_direction_input(IMX_GPIO_NR(1, 4)); | |
324 | } | |
325 | ||
326 | /* | |
327 | * SPI | |
328 | */ | |
329 | #ifdef CONFIG_MXC_SPI | |
330 | static iomux_v3_cfg_t ecspi3_pads[] = { | |
331 | /* SS1 */ | |
332 | MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
333 | MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
334 | MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
335 | MX6_PAD_DISP0_DAT3__GPIO4_IO24 | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
336 | MX6_PAD_DISP0_DAT4__GPIO4_IO25 | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
337 | MX6_PAD_DISP0_DAT5__GPIO4_IO26 | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
338 | MX6_PAD_DISP0_DAT7__ECSPI3_RDY | MUX_PAD_CTRL(SPI_PAD_CTRL), | |
339 | }; | |
340 | ||
341 | static void novena_spl_setup_iomux_spi(void) | |
342 | { | |
343 | imx_iomux_v3_setup_multiple_pads(ecspi3_pads, ARRAY_SIZE(ecspi3_pads)); | |
344 | /* De-assert the nCS */ | |
345 | gpio_direction_output(MX6_PAD_DISP0_DAT3__GPIO4_IO24, 1); | |
346 | gpio_direction_output(MX6_PAD_DISP0_DAT4__GPIO4_IO25, 1); | |
347 | gpio_direction_output(MX6_PAD_DISP0_DAT5__GPIO4_IO26, 1); | |
348 | } | |
349 | #else | |
350 | static void novena_spl_setup_iomux_spi(void) {} | |
351 | #endif | |
352 | ||
353 | /* | |
354 | * UART | |
355 | */ | |
356 | static iomux_v3_cfg_t const uart2_pads[] = { | |
357 | MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
358 | MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
359 | }; | |
360 | ||
361 | static iomux_v3_cfg_t const uart3_pads[] = { | |
362 | MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
363 | MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
364 | }; | |
365 | ||
366 | static iomux_v3_cfg_t const uart4_pads[] = { | |
367 | MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
368 | MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), | |
369 | MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
370 | MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | |
371 | ||
372 | }; | |
373 | ||
374 | static void novena_spl_setup_iomux_uart(void) | |
375 | { | |
376 | imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); | |
377 | imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); | |
378 | imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); | |
379 | } | |
380 | ||
381 | /* | |
382 | * Video | |
383 | */ | |
384 | #ifdef CONFIG_VIDEO | |
385 | static iomux_v3_cfg_t hdmi_pads[] = { | |
386 | /* "Ghost HPD" pin */ | |
387 | MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
331ae846 MV |
388 | |
389 | /* LCD_PWR_CTL */ | |
390 | MX6_PAD_CSI0_DAT10__GPIO5_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
391 | /* LCD_BL_ON */ | |
392 | MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
393 | /* GPIO_PWM1 */ | |
394 | MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), | |
f91c09ac MV |
395 | }; |
396 | ||
397 | static void novena_spl_setup_iomux_video(void) | |
398 | { | |
399 | imx_iomux_v3_setup_multiple_pads(hdmi_pads, ARRAY_SIZE(hdmi_pads)); | |
400 | gpio_direction_input(NOVENA_HDMI_GHOST_HPD); | |
401 | } | |
402 | #else | |
403 | static inline void novena_spl_setup_iomux_video(void) {} | |
404 | #endif | |
405 | ||
406 | /* | |
407 | * SPL boots from uSDHC card | |
408 | */ | |
e37ac717 | 409 | #ifdef CONFIG_FSL_ESDHC_IMX |
f91c09ac MV |
410 | static struct fsl_esdhc_cfg usdhc_cfg = { |
411 | USDHC3_BASE_ADDR, 0, 4 | |
412 | }; | |
413 | ||
414 | int board_mmc_getcd(struct mmc *mmc) | |
415 | { | |
416 | /* There is no CD for a microSD card, assume always present. */ | |
417 | return 1; | |
418 | } | |
419 | ||
420 | int board_mmc_init(bd_t *bis) | |
421 | { | |
422 | usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); | |
423 | return fsl_esdhc_initialize(bis, &usdhc_cfg); | |
424 | } | |
425 | #endif | |
426 | ||
427 | /* Configure MX6Q/DUAL mmdc DDR io registers */ | |
428 | static struct mx6dq_iomux_ddr_regs novena_ddr_ioregs = { | |
429 | /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ | |
430 | .dram_sdclk_0 = 0x00020038, | |
431 | .dram_sdclk_1 = 0x00020038, | |
432 | .dram_cas = 0x00000038, | |
433 | .dram_ras = 0x00000038, | |
434 | .dram_reset = 0x00000038, | |
435 | /* SDCKE[0:1]: 100k pull-up */ | |
89d48594 MV |
436 | .dram_sdcke0 = 0x00000038, |
437 | .dram_sdcke1 = 0x00000038, | |
f91c09ac MV |
438 | /* SDBA2: pull-up disabled */ |
439 | .dram_sdba2 = 0x00000000, | |
440 | /* SDODT[0:1]: 100k pull-up, 40 ohm */ | |
441 | .dram_sdodt0 = 0x00000038, | |
442 | .dram_sdodt1 = 0x00000038, | |
443 | /* SDQS[0:7]: Differential input, 40 ohm */ | |
444 | .dram_sdqs0 = 0x00000038, | |
445 | .dram_sdqs1 = 0x00000038, | |
446 | .dram_sdqs2 = 0x00000038, | |
447 | .dram_sdqs3 = 0x00000038, | |
448 | .dram_sdqs4 = 0x00000038, | |
449 | .dram_sdqs5 = 0x00000038, | |
450 | .dram_sdqs6 = 0x00000038, | |
451 | .dram_sdqs7 = 0x00000038, | |
452 | ||
453 | /* DQM[0:7]: Differential input, 40 ohm */ | |
454 | .dram_dqm0 = 0x00000038, | |
455 | .dram_dqm1 = 0x00000038, | |
456 | .dram_dqm2 = 0x00000038, | |
457 | .dram_dqm3 = 0x00000038, | |
458 | .dram_dqm4 = 0x00000038, | |
459 | .dram_dqm5 = 0x00000038, | |
460 | .dram_dqm6 = 0x00000038, | |
461 | .dram_dqm7 = 0x00000038, | |
462 | }; | |
463 | ||
464 | /* Configure MX6Q/DUAL mmdc GRP io registers */ | |
465 | static struct mx6dq_iomux_grp_regs novena_grp_ioregs = { | |
466 | /* DDR3 */ | |
467 | .grp_ddr_type = 0x000c0000, | |
468 | .grp_ddrmode_ctl = 0x00020000, | |
469 | /* Disable DDR pullups */ | |
470 | .grp_ddrpke = 0x00000000, | |
471 | /* ADDR[00:16], SDBA[0:1]: 40 ohm */ | |
472 | .grp_addds = 0x00000038, | |
473 | /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ | |
474 | .grp_ctlds = 0x00000038, | |
475 | /* DATA[00:63]: Differential input, 40 ohm */ | |
476 | .grp_ddrmode = 0x00020000, | |
477 | .grp_b0ds = 0x00000038, | |
478 | .grp_b1ds = 0x00000038, | |
479 | .grp_b2ds = 0x00000038, | |
480 | .grp_b3ds = 0x00000038, | |
481 | .grp_b4ds = 0x00000038, | |
482 | .grp_b5ds = 0x00000038, | |
483 | .grp_b6ds = 0x00000038, | |
484 | .grp_b7ds = 0x00000038, | |
485 | }; | |
486 | ||
487 | static struct mx6_mmdc_calibration novena_mmdc_calib = { | |
488 | /* write leveling calibration determine */ | |
489 | .p0_mpwldectrl0 = 0x00420048, | |
490 | .p0_mpwldectrl1 = 0x006f0059, | |
491 | .p1_mpwldectrl0 = 0x005a0104, | |
492 | .p1_mpwldectrl1 = 0x01070113, | |
493 | /* Read DQS Gating calibration */ | |
494 | .p0_mpdgctrl0 = 0x437c040b, | |
495 | .p0_mpdgctrl1 = 0x0413040e, | |
496 | .p1_mpdgctrl0 = 0x444f0446, | |
497 | .p1_mpdgctrl1 = 0x044d0422, | |
498 | /* Read Calibration: DQS delay relative to DQ read access */ | |
499 | .p0_mprddlctl = 0x4c424249, | |
500 | .p1_mprddlctl = 0x4e48414f, | |
501 | /* Write Calibration: DQ/DM delay relative to DQS write access */ | |
502 | .p0_mpwrdlctl = 0x42414641, | |
503 | .p1_mpwrdlctl = 0x46374b43, | |
504 | }; | |
505 | ||
506 | static struct mx6_ddr_sysinfo novena_ddr_info = { | |
507 | /* Width of data bus: 0=16, 1=32, 2=64 */ | |
508 | .dsize = 2, | |
509 | /* Config for full 4GB range so that get_mem_size() works */ | |
510 | .cs_density = 32, /* 32Gb per CS */ | |
511 | /* Single chip select */ | |
512 | .ncs = 1, | |
513 | .cs1_mirror = 0, | |
89d48594 MV |
514 | .rtt_wr = 0, /* RTT_Wr = RZQ/4 */ |
515 | .rtt_nom = 1, /* RTT_Nom = RZQ/2 */ | |
516 | .walat = 0, /* Write additional latency */ | |
517 | .ralat = 5, /* Read additional latency */ | |
f91c09ac MV |
518 | .mif3_mode = 3, /* Command prediction working mode */ |
519 | .bi_on = 1, /* Bank interleaving enabled */ | |
520 | .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ | |
521 | .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ | |
edf00937 FE |
522 | .refsel = 1, /* Refresh cycles at 32KHz */ |
523 | .refr = 7, /* 8 refresh commands per refresh cycle */ | |
f91c09ac MV |
524 | }; |
525 | ||
526 | static struct mx6_ddr3_cfg elpida_4gib_1600 = { | |
527 | .mem_speed = 1600, | |
528 | .density = 4, | |
529 | .width = 64, | |
530 | .banks = 8, | |
531 | .rowaddr = 16, | |
532 | .coladdr = 10, | |
533 | .pagesz = 2, | |
89d48594 MV |
534 | .trcd = 1375, |
535 | .trcmin = 4875, | |
536 | .trasmin = 3500, | |
f91c09ac MV |
537 | }; |
538 | ||
7d29acd9 FE |
539 | static void ccgr_init(void) |
540 | { | |
541 | struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; | |
542 | ||
543 | writel(0x00C03F3F, &ccm->CCGR0); | |
544 | writel(0x0030FC03, &ccm->CCGR1); | |
545 | writel(0x0FFFC000, &ccm->CCGR2); | |
546 | writel(0x3FF00000, &ccm->CCGR3); | |
547 | writel(0xFFFFF300, &ccm->CCGR4); | |
548 | writel(0x0F0000C3, &ccm->CCGR5); | |
549 | writel(0x000003FF, &ccm->CCGR6); | |
550 | } | |
551 | ||
f91c09ac MV |
552 | /* |
553 | * called from C runtime startup code (arch/arm/lib/crt0.S:_main) | |
554 | * - we have a stack and a place to store GD, both in SRAM | |
555 | * - no variable global data is available | |
556 | */ | |
557 | void board_init_f(ulong dummy) | |
558 | { | |
559 | /* setup AIPS and disable watchdog */ | |
560 | arch_cpu_init(); | |
561 | ||
7d29acd9 FE |
562 | ccgr_init(); |
563 | gpr_init(); | |
564 | ||
f91c09ac MV |
565 | /* setup GP timer */ |
566 | timer_init(); | |
567 | ||
568 | #ifdef CONFIG_BOARD_POSTCLK_INIT | |
569 | board_postclk_init(); | |
570 | #endif | |
e37ac717 | 571 | #ifdef CONFIG_FSL_ESDHC_IMX |
f91c09ac MV |
572 | get_clocks(); |
573 | #endif | |
574 | ||
575 | /* Setup IOMUX and configure basics. */ | |
576 | novena_spl_setup_iomux_audio(); | |
577 | novena_spl_setup_iomux_buttons(); | |
578 | novena_spl_setup_iomux_enet(); | |
579 | novena_spl_setup_iomux_fpga(); | |
580 | novena_spl_setup_iomux_i2c(); | |
581 | novena_spl_setup_iomux_pcie(); | |
582 | novena_spl_setup_iomux_sdhc(); | |
583 | novena_spl_setup_iomux_spi(); | |
584 | novena_spl_setup_iomux_uart(); | |
585 | novena_spl_setup_iomux_video(); | |
586 | ||
587 | /* UART clocks enabled and gd valid - init serial console */ | |
588 | preloader_console_init(); | |
589 | ||
590 | /* Start the DDR DRAM */ | |
591 | mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs); | |
592 | mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600); | |
593 | ||
89d48594 MV |
594 | /* Perform DDR DRAM calibration */ |
595 | udelay(100); | |
7f17fb74 EN |
596 | mmdc_do_write_level_calibration(&novena_ddr_info); |
597 | mmdc_do_dqs_calibration(&novena_ddr_info); | |
f91c09ac | 598 | } |