[people/ms/u-boot.git] / board / logicpd / imx27lite / lowlevel_init.S

/*
 * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
 * Applications Processor Reference Manual, Rev. 0.2".
 *
 * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
 * (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */


#include <config.h>
#include <version.h>
#include <asm/macro.h>
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>

SOC_ESDCTL_BASE_W:	.word	IMX_ESD_BASE
SOC_SI_ID_REG_W:	.word	IMX_SYSTEM_CTL_BASE
SDRAM_ESDCFG_T1_W:	.word	SDRAM_ESDCFG_REGISTER_VAL(0)
SDRAM_ESDCFG_T2_W:	.word	SDRAM_ESDCFG_REGISTER_VAL(3)
SDRAM_PRECHARGE_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
				 ESDCTL_ROW13 | ESDCTL_COL10)
SDRAM_AUTOREF_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
				 ESDCTL_ROW13 | ESDCTL_COL10)
SDRAM_LOADMODE_CMD_W:	.word	(ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
				 ESDCTL_ROW13 | ESDCTL_COL10)
SDRAM_NORMAL_CMD_W:	.word	SDRAM_ESDCTL_REGISTER_VAL

.macro init_aipi
	/*
	 * setup AIPI1 and AIPI2
	 */
	write32 AIPI1_PSR0, AIPI1_PSR0_VAL
	write32 AIPI1_PSR1, AIPI1_PSR1_VAL
	write32 AIPI2_PSR0, AIPI2_PSR0_VAL
	write32 AIPI2_PSR1, AIPI2_PSR1_VAL

.endm /* init_aipi */

.macro init_clock
	ldr r0, =CSCR
	/* disable MPLL/SPLL first */
	ldr r1, [r0]
	bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
	str r1, [r0]

	write32 MPCTL0, MPCTL0_VAL
	write32 SPCTL0, SPCTL0_VAL

	write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART

	/*
	 * add some delay here
	 */
	wait_timer 0x1000

	/* peripheral clock divider */
	write32 PCDR0, PCDR0_VAL
	write32 PCDR1, PCDR1_VAL

	/* Configure PCCR0 and PCCR1 */
	write32 PCCR0, PCCR0_VAL
	write32 PCCR1, PCCR1_VAL

.endm /* init_clock */

.macro sdram_init
	ldr r0, SOC_ESDCTL_BASE_W
	mov r2, #PHYS_SDRAM_1

	/* Do initial reset */
	mov r1, #ESDMISC_MDDR_DL_RST
	str r1, [r0, #ESDMISC_ROF]

	/* Hold for more than 200ns */
	wait_timer 0x10000

	/* Activate LPDDR iface */
	mov r1, #ESDMISC_MDDREN
	str r1, [r0, #ESDMISC_ROF]

	/* Check The chip version TO1 or TO2 */
	ldr r1, SOC_SI_ID_REG_W
	ldr r1, [r1]
	ands r1, r1, #0xF0000000
	/* add Latency on CAS only for TO2 */
	ldreq r1, SDRAM_ESDCFG_T2_W
	ldrne r1, SDRAM_ESDCFG_T1_W
	str r1, [r0, #ESDCFG0_ROF]

	/* Run initialization sequence */
	ldr r1, SDRAM_PRECHARGE_CMD_W
	str r1, [r0, #ESDCTL0_ROF]
	ldr r1, [r2, #SDRAM_ALL_VAL]

	ldr r1, SDRAM_AUTOREF_CMD_W
	str r1, [r0, #ESDCTL0_ROF]
	ldr r1, [r2, #SDRAM_ALL_VAL]
	ldr r1, [r2, #SDRAM_ALL_VAL]

	ldr r1, SDRAM_LOADMODE_CMD_W
	str r1, [r0, #ESDCTL0_ROF]
	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
	ldrb r1, [r3]

	ldr r1, SDRAM_NORMAL_CMD_W
	str r1, [r0, #ESDCTL0_ROF]

#if (CONFIG_NR_DRAM_BANKS > 1)
	/* 2nd sdram */
	mov r2, #PHYS_SDRAM_2

	/* Check The chip version TO1 or TO2 */
	ldr r1, SOC_SI_ID_REG_W
	ldr r1, [r1]
	ands r1, r1, #0xF0000000
	/* add Latency on CAS only for TO2 */
	ldreq r1, SDRAM_ESDCFG_T2_W
	ldrne r1, SDRAM_ESDCFG_T1_W
	str r1, [r0, #ESDCFG1_ROF]

	/* Run initialization sequence */
	ldr r1, SDRAM_PRECHARGE_CMD_W
	str r1, [r0, #ESDCTL1_ROF]
	ldr r1, [r2, #SDRAM_ALL_VAL]

	ldr r1, SDRAM_AUTOREF_CMD_W
	str r1, [r0, #ESDCTL1_ROF]
	ldr r1, [r2, #SDRAM_ALL_VAL]
	ldr r1, [r2, #SDRAM_ALL_VAL]

	ldr r1, SDRAM_LOADMODE_CMD_W
	str r1, [r0, #ESDCTL1_ROF]
	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
	ldrb r1, [r3]

	ldr r1, SDRAM_NORMAL_CMD_W
	str r1, [r0, #ESDCTL1_ROF]
#endif  /* CONFIG_NR_DRAM_BANKS > 1 */

.endm /* sdram_init */

.globl	lowlevel_init
lowlevel_init:

	mov	r10, lr

	init_aipi

	init_clock

	sdram_init

	mov	pc,r10
Commit	Line	Data
10bc241d IY	1	/*
	2	* For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
	3	* Applications Processor Reference Manual, Rev. 0.2".
	4	*
	5	* (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
	6	* (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
10bc241d IY	9	*/
	10
	11
	12	#include <config.h>
	13	#include <version.h>
	14	#include <asm/macro.h>
	15	#include <asm/arch/imx-regs.h>
a4814a69	16	#include <generated/asm-offsets.h>
10bc241d IY	17
	18	SOC_ESDCTL_BASE_W: .word IMX_ESD_BASE
	19	SOC_SI_ID_REG_W: .word IMX_SYSTEM_CTL_BASE
	20	SDRAM_ESDCFG_T1_W: .word SDRAM_ESDCFG_REGISTER_VAL(0)
	21	SDRAM_ESDCFG_T2_W: .word SDRAM_ESDCFG_REGISTER_VAL(3)
	22	SDRAM_PRECHARGE_CMD_W: .word (ESDCTL_SDE \| ESDCTL_SMODE_PRECHARGE \| \
	23	ESDCTL_ROW13 \| ESDCTL_COL10)
	24	SDRAM_AUTOREF_CMD_W: .word (ESDCTL_SDE \| ESDCTL_SMODE_AUTO_REF \| \
	25	ESDCTL_ROW13 \| ESDCTL_COL10)
	26	SDRAM_LOADMODE_CMD_W: .word (ESDCTL_SDE \| ESDCTL_SMODE_LOAD_MODE \| \
	27	ESDCTL_ROW13 \| ESDCTL_COL10)
	28	SDRAM_NORMAL_CMD_W: .word SDRAM_ESDCTL_REGISTER_VAL
	29
	30	.macro init_aipi
	31	/*
	32	* setup AIPI1 and AIPI2
	33	*/
	34	write32 AIPI1_PSR0, AIPI1_PSR0_VAL
	35	write32 AIPI1_PSR1, AIPI1_PSR1_VAL
	36	write32 AIPI2_PSR0, AIPI2_PSR0_VAL
	37	write32 AIPI2_PSR1, AIPI2_PSR1_VAL
	38
	39	.endm /* init_aipi */
	40
	41	.macro init_clock
	42	ldr r0, =CSCR
	43	/* disable MPLL/SPLL first */
	44	ldr r1, [r0]
	45	bic r1, r1, #(CSCR_MPEN\|CSCR_SPEN)
	46	str r1, [r0]
	47
	48	write32 MPCTL0, MPCTL0_VAL
	49	write32 SPCTL0, SPCTL0_VAL
	50
	51	write32 CSCR, CSCR_VAL \| CSCR_MPLL_RESTART \| CSCR_SPLL_RESTART
	52
	53	/*
	54	* add some delay here
	55	*/
	56	wait_timer 0x1000
	57
	58	/* peripheral clock divider */
	59	write32 PCDR0, PCDR0_VAL
	60	write32 PCDR1, PCDR1_VAL
	61
	62	/* Configure PCCR0 and PCCR1 */
	63	write32 PCCR0, PCCR0_VAL
	64	write32 PCCR1, PCCR1_VAL
	65
	66	.endm /* init_clock */
	67
	68	.macro sdram_init
	69	ldr r0, SOC_ESDCTL_BASE_W
	70	mov r2, #PHYS_SDRAM_1
	71
	72	/* Do initial reset */
	73	mov r1, #ESDMISC_MDDR_DL_RST
	74	str r1, [r0, #ESDMISC_ROF]
	75
	76	/* Hold for more than 200ns */
	77	wait_timer 0x10000
	78
	79	/* Activate LPDDR iface */
	80	mov r1, #ESDMISC_MDDREN
81	str r1, [r0, #ESDMISC_ROF]
82
83	/* Check The chip version TO1 or TO2 */
84	ldr r1, SOC_SI_ID_REG_W
85	ldr r1, [r1]
86	ands r1, r1, #0xF0000000
87	/* add Latency on CAS only for TO2 */
88	ldreq r1, SDRAM_ESDCFG_T2_W
89	ldrne r1, SDRAM_ESDCFG_T1_W
90	str r1, [r0, #ESDCFG0_ROF]
91
92	/* Run initialization sequence */
93	ldr r1, SDRAM_PRECHARGE_CMD_W
94	str r1, [r0, #ESDCTL0_ROF]
95	ldr r1, [r2, #SDRAM_ALL_VAL]
96
97	ldr r1, SDRAM_AUTOREF_CMD_W
98	str r1, [r0, #ESDCTL0_ROF]
99	ldr r1, [r2, #SDRAM_ALL_VAL]
100	ldr r1, [r2, #SDRAM_ALL_VAL]
101
102	ldr r1, SDRAM_LOADMODE_CMD_W
103	str r1, [r0, #ESDCTL0_ROF]
104	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
105	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
106	ldrb r1, [r3]
107
108	ldr r1, SDRAM_NORMAL_CMD_W
109	str r1, [r0, #ESDCTL0_ROF]
110
111	#if (CONFIG_NR_DRAM_BANKS > 1)
112	/* 2nd sdram */
113	mov r2, #PHYS_SDRAM_2
114
115	/* Check The chip version TO1 or TO2 */
116	ldr r1, SOC_SI_ID_REG_W
117	ldr r1, [r1]
118	ands r1, r1, #0xF0000000
119	/* add Latency on CAS only for TO2 */
120	ldreq r1, SDRAM_ESDCFG_T2_W
121	ldrne r1, SDRAM_ESDCFG_T1_W
122	str r1, [r0, #ESDCFG1_ROF]
123
124	/* Run initialization sequence */
125	ldr r1, SDRAM_PRECHARGE_CMD_W
126	str r1, [r0, #ESDCTL1_ROF]
127	ldr r1, [r2, #SDRAM_ALL_VAL]
128
129	ldr r1, SDRAM_AUTOREF_CMD_W
130	str r1, [r0, #ESDCTL1_ROF]
131	ldr r1, [r2, #SDRAM_ALL_VAL]
132	ldr r1, [r2, #SDRAM_ALL_VAL]
133
134	ldr r1, SDRAM_LOADMODE_CMD_W
135	str r1, [r0, #ESDCTL1_ROF]
136	ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
137	add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
138	ldrb r1, [r3]
139
140	ldr r1, SDRAM_NORMAL_CMD_W
141	str r1, [r0, #ESDCTL1_ROF]
142	#endif /* CONFIG_NR_DRAM_BANKS > 1 */
143
144	.endm /* sdram_init */
145
146	.globl lowlevel_init
147	lowlevel_init:
148
149	mov r10, lr
150
151	init_aipi
152
153	init_clock
154
155	sdram_init
156
157	mov pc,r10