[people/ms/u-boot.git] / board / lubbock / lowlevel_init.S

/*
 * Most of this taken from Redboot hal_platform_setup.h with cleanup
 *
 * NOTE: I haven't clean this up considerably, just enough to get it
 * running. See hal_platform_setup.h for the source. See
 * board/cradle/lowlevel_init.S for another PXA250 setup that is
 * much cleaner.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>

DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE

/* wait for coprocessor write complete */
   .macro CPWAIT reg
   mrc  p15,0,\reg,c2,c0,0
   mov  \reg,\reg
   sub  pc,pc,#4
   .endm


/*
 *	Memory setup
 */

.globl lowlevel_init
lowlevel_init:

    mov      r10, lr

	/* Set up GPIO pins first ----------------------------------------- */

	ldr		r0,	=GPSR0
	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
	str		r1,   [r0]

	ldr		r0,	=GPSR1
	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
	str		r1,   [r0]

	ldr		r0,	=GPSR2
	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
	str		r1,   [r0]

	ldr		r0,	=GPCR0
	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
	str		r1,   [r0]

	ldr		r0,	=GPCR1
	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
	str		r1,   [r0]

	ldr		r0,	=GPCR2
	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
	str		r1,   [r0]

	ldr		r0,	=GPDR0
	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
	str		r1,   [r0]

	ldr		r0,	=GPDR1
	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
	str		r1,   [r0]

	ldr		r0,	=GPDR2
	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR0_L
	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR0_U
	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR1_L
	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR1_U
	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR2_L
	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR2_U
	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
	str		r1,   [r0]

	ldr	r0,	=PSSR		/* enable GPIO pins */
	ldr		r1,	=CONFIG_SYS_PSSR_VAL
	str		r1,   [r0]

	/* ---------------------------------------------------------------- */
	/* Enable memory interface                                          */
	/*                                                                  */
	/* The sequence below is based on the recommended init steps        */
	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
	/* Chapter 10.                                                      */
	/* ---------------------------------------------------------------- */

	/* ---------------------------------------------------------------- */
	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
	/*         clocks to settle. Only necessary after hard reset...     */
	/*         FIXME: can be optimized later                            */
	/* ---------------------------------------------------------------- */

	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
	mov r2, #0
	str r2, [r3]
	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
					/* so 0x300 should be plenty        */
1:
	ldr r2, [r3]
	cmp r4, r2
	bgt 1b

mem_init:

	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */

	/* ---------------------------------------------------------------- */
	/* Step 2a: Initialize Asynchronous static memory controller        */
	/* ---------------------------------------------------------------- */

	/* MSC registers: timing, bus width, mem type                       */

	/* MSC0: nCS(0,1)                                                   */
	ldr     r2,   =CONFIG_SYS_MSC0_VAL
	str     r2,   [r1, #MSC0_OFFSET]
	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
						/* that data latches        */
	/* MSC1: nCS(2,3)                                                   */
	ldr     r2,  =CONFIG_SYS_MSC1_VAL
	str     r2,  [r1, #MSC1_OFFSET]
	ldr     r2,  [r1, #MSC1_OFFSET]

	/* MSC2: nCS(4,5)                                                   */
	ldr     r2,  =CONFIG_SYS_MSC2_VAL
	str     r2,  [r1, #MSC2_OFFSET]
	ldr     r2,  [r1, #MSC2_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 2b: Initialize Card Interface                               */
	/* ---------------------------------------------------------------- */

	/* MECR: Memory Expansion Card Register                             */
	ldr     r2,  =CONFIG_SYS_MECR_VAL
	str     r2,  [r1, #MECR_OFFSET]
	ldr	r2,	[r1, #MECR_OFFSET]

	/* MCMEM0: Card Interface slot 0 timing                             */
	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
	str     r2,  [r1, #MCMEM0_OFFSET]
	ldr	r2,	[r1, #MCMEM0_OFFSET]

	/* MCMEM1: Card Interface slot 1 timing                             */
	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
	str     r2,  [r1, #MCMEM1_OFFSET]
	ldr	r2,	[r1, #MCMEM1_OFFSET]

	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
	str     r2,  [r1, #MCATT0_OFFSET]
	ldr	r2,	[r1, #MCATT0_OFFSET]

	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
	str     r2,  [r1, #MCATT1_OFFSET]
	ldr	r2,	[r1, #MCATT1_OFFSET]

	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
	str     r2,  [r1, #MCIO0_OFFSET]
	ldr	r2,	[r1, #MCIO0_OFFSET]

	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
	str     r2,  [r1, #MCIO1_OFFSET]
	ldr	r2,	[r1, #MCIO1_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
	/* ---------------------------------------------------------------- */


	/* ---------------------------------------------------------------- */
	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
	/* ---------------------------------------------------------------- */

	/* Before accessing MDREFR we need a valid DRI field, so we set     */
	/* this to power on defaults + DRI field.                           */

	ldr     r3,     =CONFIG_SYS_MDREFR_VAL
	ldr     r2,     =0xFFF
	and     r3,     r3,  r2
	ldr	r4,	=0x03ca4000
	orr     r4,     r4,  r3
	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
	ldr     r4,  [r1, #MDREFR_OFFSET]

	/* Note: preserve the mdrefr value in r4                            */


	/* ---------------------------------------------------------------- */
	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
	/* ---------------------------------------------------------------- */

	/* Initialize SXCNFG register. Assert the enable bits               */

	/* Write SXMRS to cause an MRS command to all enabled banks of      */
	/* synchronous static memory. Note that SXLCR need not be written   */
	/* at this time.                                                    */

	/* FIXME: we use async mode for now                                 */


	/* ---------------------------------------------------------------- */
	/* Step 4: Initialize SDRAM                                         */
	/* ---------------------------------------------------------------- */

	/* set MDREFR according to user define with exception of a few bits */

	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
	orr	r4,	r4,	#(MDREFR_SLFRSH)
	bic	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
	ldr     r4,  [r1, #MDREFR_OFFSET]

	/* Step 4b: de-assert MDREFR:SLFRSH.                                */

	bic	r4,	r4,	#(MDREFR_SLFRSH)
	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
	ldr     r4,  [r1, #MDREFR_OFFSET]


	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */

	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
	ldr     r4,     [r1, #MDREFR_OFFSET]


	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
	/*          configure but not enable each SDRAM partition pair.     */

	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)

	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
	ldr     r4,     [r1, #MDCNFG_OFFSET]


	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
Commit	Line	Data
fe8c2806 WD	1	/*
	2	* Most of this taken from Redboot hal_platform_setup.h with cleanup
	3	*
	4	* NOTE: I haven't clean this up considerably, just enough to get it
	5	* running. See hal_platform_setup.h for the source. See
400558b5	6	* board/cradle/lowlevel_init.S for another PXA250 setup that is
fe8c2806 WD	7	* much cleaner.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <config.h>
	29	#include <version.h>
	30	#include <asm/arch/pxa-regs.h>
	31
6d0f6bcf	32	DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
fe8c2806 WD	33
	34	/* wait for coprocessor write complete */
	35	.macro CPWAIT reg
	36	mrc p15,0,\reg,c2,c0,0
	37	mov \reg,\reg
	38	sub pc,pc,#4
	39	.endm
	40
	41
db2f721f	42	/*
53677ef1	43	* Memory setup
db2f721f WD	44	*/
db2f721f WD	45
400558b5 WD	46	.globl lowlevel_init
400558b5 WD	47	lowlevel_init:
fe8c2806 WD	48
	49	mov r10, lr
	50
db2f721f	51	/* Set up GPIO pins first ----------------------------------------- */
fe8c2806 WD	52
fe8c2806 WD	53	ldr r0, =GPSR0
6d0f6bcf	54	ldr r1, =CONFIG_SYS_GPSR0_VAL
fe8c2806 WD	55	str r1, [r0]
	56
	57	ldr r0, =GPSR1
6d0f6bcf	58	ldr r1, =CONFIG_SYS_GPSR1_VAL
fe8c2806 WD	59	str r1, [r0]
	60
	61	ldr r0, =GPSR2
6d0f6bcf	62	ldr r1, =CONFIG_SYS_GPSR2_VAL
fe8c2806 WD	63	str r1, [r0]
	64
	65	ldr r0, =GPCR0
6d0f6bcf	66	ldr r1, =CONFIG_SYS_GPCR0_VAL
fe8c2806 WD	67	str r1, [r0]
	68
	69	ldr r0, =GPCR1
6d0f6bcf	70	ldr r1, =CONFIG_SYS_GPCR1_VAL
fe8c2806 WD	71	str r1, [r0]
	72
	73	ldr r0, =GPCR2
6d0f6bcf	74	ldr r1, =CONFIG_SYS_GPCR2_VAL
fe8c2806 WD	75	str r1, [r0]
	76
	77	ldr r0, =GPDR0
6d0f6bcf	78	ldr r1, =CONFIG_SYS_GPDR0_VAL
fe8c2806 WD	79	str r1, [r0]
	80
	81	ldr r0, =GPDR1
6d0f6bcf	82	ldr r1, =CONFIG_SYS_GPDR1_VAL
fe8c2806 WD	83	str r1, [r0]
	84
	85	ldr r0, =GPDR2
6d0f6bcf	86	ldr r1, =CONFIG_SYS_GPDR2_VAL
fe8c2806 WD	87	str r1, [r0]
	88
	89	ldr r0, =GAFR0_L
6d0f6bcf	90	ldr r1, =CONFIG_SYS_GAFR0_L_VAL
fe8c2806 WD	91	str r1, [r0]
	92
	93	ldr r0, =GAFR0_U
6d0f6bcf	94	ldr r1, =CONFIG_SYS_GAFR0_U_VAL
fe8c2806 WD	95	str r1, [r0]
	96
	97	ldr r0, =GAFR1_L
6d0f6bcf	98	ldr r1, =CONFIG_SYS_GAFR1_L_VAL
fe8c2806 WD	99	str r1, [r0]
	100
	101	ldr r0, =GAFR1_U
6d0f6bcf	102	ldr r1, =CONFIG_SYS_GAFR1_U_VAL
fe8c2806 WD	103	str r1, [r0]
	104
	105	ldr r0, =GAFR2_L
6d0f6bcf	106	ldr r1, =CONFIG_SYS_GAFR2_L_VAL
fe8c2806 WD	107	str r1, [r0]
	108
	109	ldr r0, =GAFR2_U
6d0f6bcf	110	ldr r1, =CONFIG_SYS_GAFR2_U_VAL
fe8c2806 WD	111	str r1, [r0]
fe8c2806 WD	112
db2f721f	113	ldr r0, =PSSR /* enable GPIO pins */
6d0f6bcf	114	ldr r1, =CONFIG_SYS_PSSR_VAL
fe8c2806 WD	115	str r1, [r0]
fe8c2806 WD	116
db2f721f WD	117	/* ---------------------------------------------------------------- */
	118	/* Enable memory interface */
	119	/* */
	120	/* The sequence below is based on the recommended init steps */
	121	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
	122	/* Chapter 10. */
	123	/* ---------------------------------------------------------------- */
	124
	125	/* ---------------------------------------------------------------- */
	126	/* Step 1: Wait for at least 200 microsedonds to allow internal */
	127	/* clocks to settle. Only necessary after hard reset... */
	128	/* FIXME: can be optimized later */
	129	/* ---------------------------------------------------------------- */
	130
	131	ldr r3, =OSCR /* reset the OS Timer Count to zero */
fe8c2806 WD	132	mov r2, #0
fe8c2806 WD	133	str r2, [r3]
db2f721f WD	134	ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
db2f721f WD	135	/* so 0x300 should be plenty */
fe8c2806 WD	136	1:
	137	ldr r2, [r3]
	138	cmp r4, r2
	139	bgt 1b
	140
	141	mem_init:
fe8c2806	142
8bde7f77	143	ldr r1, =MEMC_BASE /* get memory controller base addr. */
fe8c2806	144
db2f721f WD	145	/* ---------------------------------------------------------------- */
	146	/* Step 2a: Initialize Asynchronous static memory controller */
	147	/* ---------------------------------------------------------------- */
	148
	149	/* MSC registers: timing, bus width, mem type */
	150
8bde7f77	151	/* MSC0: nCS(0,1) */
6d0f6bcf	152	ldr r2, =CONFIG_SYS_MSC0_VAL
8bde7f77 WD	153	str r2, [r1, #MSC0_OFFSET]
8bde7f77 WD	154	ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
db2f721f	155	/* that data latches */
8bde7f77	156	/* MSC1: nCS(2,3) */
6d0f6bcf	157	ldr r2, =CONFIG_SYS_MSC1_VAL
8bde7f77 WD	158	str r2, [r1, #MSC1_OFFSET]
8bde7f77 WD	159	ldr r2, [r1, #MSC1_OFFSET]
fe8c2806	160
db2f721f	161	/* MSC2: nCS(4,5) */
6d0f6bcf	162	ldr r2, =CONFIG_SYS_MSC2_VAL
8bde7f77 WD	163	str r2, [r1, #MSC2_OFFSET]
8bde7f77 WD	164	ldr r2, [r1, #MSC2_OFFSET]
fe8c2806	165
db2f721f WD	166	/* ---------------------------------------------------------------- */
	167	/* Step 2b: Initialize Card Interface */
	168	/* ---------------------------------------------------------------- */
	169
	170	/* MECR: Memory Expansion Card Register */
6d0f6bcf	171	ldr r2, =CONFIG_SYS_MECR_VAL
8bde7f77	172	str r2, [r1, #MECR_OFFSET]
db2f721f	173	ldr r2, [r1, #MECR_OFFSET]
fe8c2806	174
db2f721f	175	/* MCMEM0: Card Interface slot 0 timing */
6d0f6bcf	176	ldr r2, =CONFIG_SYS_MCMEM0_VAL
8bde7f77	177	str r2, [r1, #MCMEM0_OFFSET]
db2f721f	178	ldr r2, [r1, #MCMEM0_OFFSET]
fe8c2806	179
8bde7f77	180	/* MCMEM1: Card Interface slot 1 timing */
6d0f6bcf	181	ldr r2, =CONFIG_SYS_MCMEM1_VAL
8bde7f77	182	str r2, [r1, #MCMEM1_OFFSET]
db2f721f	183	ldr r2, [r1, #MCMEM1_OFFSET]
fe8c2806	184
db2f721f	185	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
6d0f6bcf	186	ldr r2, =CONFIG_SYS_MCATT0_VAL
8bde7f77	187	str r2, [r1, #MCATT0_OFFSET]
db2f721f	188	ldr r2, [r1, #MCATT0_OFFSET]
fe8c2806	189
db2f721f	190	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
6d0f6bcf	191	ldr r2, =CONFIG_SYS_MCATT1_VAL
8bde7f77	192	str r2, [r1, #MCATT1_OFFSET]
db2f721f	193	ldr r2, [r1, #MCATT1_OFFSET]
fe8c2806	194
db2f721f	195	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
6d0f6bcf	196	ldr r2, =CONFIG_SYS_MCIO0_VAL
8bde7f77	197	str r2, [r1, #MCIO0_OFFSET]
db2f721f	198	ldr r2, [r1, #MCIO0_OFFSET]
fe8c2806	199
db2f721f	200	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
6d0f6bcf	201	ldr r2, =CONFIG_SYS_MCIO1_VAL
8bde7f77	202	str r2, [r1, #MCIO1_OFFSET]
db2f721f	203	ldr r2, [r1, #MCIO1_OFFSET]
fe8c2806	204
db2f721f	205	/* ---------------------------------------------------------------- */
8bde7f77 WD	206	/* Step 2c: Write FLYCNFG FIXME: what's that??? */
8bde7f77 WD	207	/* ---------------------------------------------------------------- */
fe8c2806	208
fe8c2806	209
db2f721f	210	/* ---------------------------------------------------------------- */
8bde7f77 WD	211	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
8bde7f77 WD	212	/* ---------------------------------------------------------------- */
fe8c2806	213
db2f721f WD	214	/* Before accessing MDREFR we need a valid DRI field, so we set */
db2f721f WD	215	/* this to power on defaults + DRI field. */
fe8c2806	216
6d0f6bcf	217	ldr r3, =CONFIG_SYS_MDREFR_VAL
8bde7f77 WD	218	ldr r2, =0xFFF
8bde7f77 WD	219	and r3, r3, r2
db2f721f	220	ldr r4, =0x03ca4000
8bde7f77	221	orr r4, r4, r3
db2f721f	222	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
8bde7f77	223	ldr r4, [r1, #MDREFR_OFFSET]
fe8c2806	224
8bde7f77	225	/* Note: preserve the mdrefr value in r4 */
fe8c2806	226
fe8c2806	227
db2f721f WD	228	/* ---------------------------------------------------------------- */
	229	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
	230	/* ---------------------------------------------------------------- */
fe8c2806	231
db2f721f	232	/* Initialize SXCNFG register. Assert the enable bits */
fe8c2806	233
db2f721f WD	234	/* Write SXMRS to cause an MRS command to all enabled banks of */
	235	/* synchronous static memory. Note that SXLCR need not be written */
	236	/* at this time. */
fe8c2806	237
db2f721f	238	/* FIXME: we use async mode for now */
fe8c2806	239
fe8c2806	240
8bde7f77 WD	241	/* ---------------------------------------------------------------- */
	242	/* Step 4: Initialize SDRAM */
	243	/* ---------------------------------------------------------------- */
db2f721f	244
8bde7f77	245	/* set MDREFR according to user define with exception of a few bits */
db2f721f	246
6d0f6bcf	247	ldr r4, =CONFIG_SYS_MDREFR_VAL
db2f721f WD	248	orr r4, r4, #(MDREFR_SLFRSH)
	249	bic r4, r4, #(MDREFR_E1PIN\|MDREFR_E0PIN)
	250	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
8bde7f77	251	ldr r4, [r1, #MDREFR_OFFSET]
fe8c2806	252
db2f721f	253	/* Step 4b: de-assert MDREFR:SLFRSH. */
fe8c2806	254
db2f721f	255	bic r4, r4, #(MDREFR_SLFRSH)
8bde7f77 WD	256	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
8bde7f77 WD	257	ldr r4, [r1, #MDREFR_OFFSET]
fe8c2806	258
fe8c2806	259
db2f721f	260	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
fe8c2806	261
6d0f6bcf	262	ldr r4, =CONFIG_SYS_MDREFR_VAL
8bde7f77 WD	263	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
8bde7f77 WD	264	ldr r4, [r1, #MDREFR_OFFSET]
fe8c2806 WD	265
fe8c2806 WD	266
db2f721f WD	267	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
db2f721f WD	268	/* configure but not enable each SDRAM partition pair. */
fe8c2806	269
6d0f6bcf	270	ldr r4, =CONFIG_SYS_MDCNFG_VAL
db2f721f	271	bic r4, r4, #(MDCNFG_DE0\|MDCNFG_DE1)
fe8c2806	272
8bde7f77 WD	273	str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
8bde7f77 WD	274	ldr r4, [r1, #MDCNFG_OFFSET]
db2f721f WD	275
	276
	277	/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
	278