[people/ms/u-boot.git] / board / lwmon / lwmon.c

/***********************************************************************
 *
M* Modul:         lwmon.c
M*
M* Content:       LWMON specific U-Boot commands.
 *
 * (C) Copyright 2001, 2002
 * DENX Software Engineering
 * Wolfgang Denk, wd@denx.de
 *
D* Design:        wd@denx.de
C* Coding:        wd@denx.de
V* Verification:  dzu@denx.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 ***********************************************************************/

/*---------------------------- Headerfiles ----------------------------*/
#include <common.h>
#include <mpc8xx.h>
#include <commproc.h>
#include <i2c.h>
#include <command.h>
#include <malloc.h>
#include <post.h>
#include <serial.h>

#include <linux/types.h>
#include <linux/string.h>	/* for strdup */

DECLARE_GLOBAL_DATA_PTR;

/*------------------------ Local prototypes ---------------------------*/
static long int dram_size (long int, long int *, long int);
static void kbd_init (void);
static int compare_magic (uchar *kbd_data, uchar *str);


/*--------------------- Local macros and constants --------------------*/
#define	_NOT_USED_	0xFFFFFFFF

#ifdef CONFIG_MODEM_SUPPORT
static int key_pressed(void);
extern void disable_putc(void);
#endif /* CONFIG_MODEM_SUPPORT */

/*
 * 66 MHz SDRAM access using UPM A
 */
const uint sdram_table[] =
{
#if defined(CONFIG_SYS_MEMORY_75) || defined(CONFIG_SYS_MEMORY_8E)
	/*
	 * Single Read. (Offset 0 in UPM RAM)
	 */
	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
	0x1FF5FC47, /* last */
	/*
	 * SDRAM Initialization (offset 5 in UPM RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	/*
	 * Burst Read. (Offset 8 in UPM RAM)
	 */
	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPM RAM)
	 */
	0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPM RAM)
	 */
	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
	0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPM RAM)
	 */
	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC84, 0xFFFFFC07, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPM RAM)
	 */
	0x7FFFFC07, /* last */
		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
#endif
#ifdef CONFIG_SYS_MEMORY_7E
	/*
	 * Single Read. (Offset 0 in UPM RAM)
	 */
	0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */
	_NOT_USED_,
	/*
	 * SDRAM Initialization (offset 5 in UPM RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
		    0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	/*
	 * Burst Read. (Offset 8 in UPM RAM)
	 */
	0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00,
	0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Single Write. (Offset 18 in UPM RAM)
	 */
	0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */
					    _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPM RAM)
	 */
	0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00,
	0xE1BAFC04, 0x1FF5FC47, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Refresh  (Offset 30 in UPM RAM)
	 */
	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC84, 0xFFFFFC07, /* last */
				_NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/*
	 * Exception. (Offset 3c in UPM RAM)
	 */
	0x7FFFFC07, /* last */
		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
#endif
};

/*
 * Check Board Identity:
 *
 */

/***********************************************************************
F* Function:     int checkboard (void) P*A*Z*
 *
P* Parameters:   none
P*
P* Returnvalue:  int - 0 is always returned
 *
Z* Intention:    This function is the checkboard() method implementation
Z*               for the lwmon board.  Only a standard message is printed.
 *
D* Design:       wd@denx.de
C* Coding:       wd@denx.de
V* Verification: dzu@denx.de
 ***********************************************************************/
int checkboard (void)
{
	puts ("Board: LICCON Konsole LCD3\n");
	return (0);
}

/***********************************************************************
F* Function:     phys_size_t initdram (int board_type) P*A*Z*
 *
P* Parameters:   int board_type
P*                - Usually type of the board - ignored here.
P*
P* Returnvalue:  long int
P*                - Size of initialized memory
 *
Z* Intention:    This function is the initdram() method implementation
Z*               for the lwmon board.
Z*               The memory controller is initialized to access the
Z*               DRAM.
 *
D* Design:       wd@denx.de
C* Coding:       wd@denx.de
V* Verification: dzu@denx.de
 ***********************************************************************/
phys_size_t initdram (int board_type)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;
	long int size_b0;
	long int size8, size9;
	int i;

	/*
	 * Configure UPMA for SDRAM
	 */
	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));

	memctl->memc_mptpr = CONFIG_SYS_MPTPR;

	/* burst length=4, burst type=sequential, CAS latency=2 */
	memctl->memc_mar = CONFIG_SYS_MAR;

	/*
	 * Map controller bank 3 to the SDRAM bank at preliminary address.
	 */
	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;

	/* initialize memory address register */
	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;	/* refresh not enabled yet */

	/* mode initialization (offset 5) */
	udelay (200);				/* 0x80006105 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x05);

	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
	udelay (1);				/* 0x80006130 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);
	udelay (1);				/* 0x80006130 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x30);

	udelay (1);				/* 0x80006106 */
	memctl->memc_mcr = MCR_OP_RUN | MCR_MB_CS3 | MCR_MLCF (1) | MCR_MAD (0x06);

	memctl->memc_mamr |= MAMR_PTAE;	/* refresh enabled */

	udelay (200);

	/* Need at least 10 DRAM accesses to stabilize */
	for (i = 0; i < 10; ++i) {
		volatile unsigned long *addr =
			(volatile unsigned long *) SDRAM_BASE3_PRELIM;
		unsigned long val;

		val = *(addr + i);
		*(addr + i) = val;
	}

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 * try 8 column mode
	 */
	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);

	udelay (1000);

	/*
	 * try 9 column mode
	 */
	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);

	if (size8 < size9) {		/* leave configuration at 9 columns */
		size_b0 = size9;
		memctl->memc_mamr = CONFIG_SYS_MAMR_9COL | MAMR_PTAE;
		udelay (500);
	} else {			/* back to 8 columns            */
		size_b0 = size8;
		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE;
		udelay (500);
	}

	/*
	 * Final mapping:
	 */

	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) |
			OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
	udelay (1000);

	return (size_b0);
}

/***********************************************************************
F* Function:     static long int dram_size (long int mamr_value,
F*                                          long int *base,
F*                                          long int maxsize) P*A*Z*
 *
P* Parameters:   long int mamr_value
P*                - Value for MAMR for the test
P*               long int *base
P*                - Base address for the test
P*               long int maxsize
P*                - Maximum size to test for
P*
P* Returnvalue:  long int
P*                - Size of probed memory
 *
Z* Intention:    Check memory range for valid RAM. A simple memory test
Z*               determines the actually available RAM size between
Z*               addresses `base' and `base + maxsize'. Some (not all)
Z*               hardware errors are detected:
Z*                - short between address lines
Z*                - short between data lines
 *
D* Design:       wd@denx.de
C* Coding:       wd@denx.de
V* Verification: dzu@denx.de
 ***********************************************************************/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immr->im_memctl;

	memctl->memc_mamr = mamr_value;

	return (get_ram_size(base, maxsize));
}

/* ------------------------------------------------------------------------- */

#ifndef	PB_ENET_TENA
# define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
#endif

/***********************************************************************
F* Function:     int board_early_init_f (void) P*A*Z*
 *
P* Parameters:   none
P*
P* Returnvalue:  int
P*                - 0 is always returned.
 *
Z* Intention:    This function is the board_early_init_f() method implementation
Z*               for the lwmon board.
Z*               Disable Ethernet TENA on Port B.
 *
D* Design:       wd@denx.de
C* Coding:       wd@denx.de
V* Verification: dzu@denx.de
 ***********************************************************************/
int board_early_init_f (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;

	/* Disable Ethernet TENA on Port B
	 * Necessary because of pull up in COM3 port.
	 *
	 * This is just a preliminary fix, intended to turn off TENA
	 * as soon as possible to avoid noise on the network. Once
Commit	Line	Data
e2211743 WD	1	/***********************************************************************
	2	*
	3	M* Modul: lwmon.c
	4	M*
	5	M* Content: LWMON specific U-Boot commands.
	6	*
	7	* (C) Copyright 2001, 2002
	8	* DENX Software Engineering
	9	* Wolfgang Denk, wd@denx.de
e2211743 WD	10	*
	11	D* Design: wd@denx.de
	12	C* Coding: wd@denx.de
	13	V* Verification: dzu@denx.de
	14	*
	15	* See file CREDITS for list of people who contributed to this
	16	* project.
	17	*
	18	* This program is free software; you can redistribute it and/or
	19	* modify it under the terms of the GNU General Public License as
	20	* published by the Free Software Foundation; either version 2 of
	21	* the License, or (at your option) any later version.
	22	*
	23	* This program is distributed in the hope that it will be useful,
	24	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	25	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	26	* GNU General Public License for more details.
	27	*
	28	* You should have received a copy of the GNU General Public License
	29	* along with this program; if not, write to the Free Software
	30	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	31	* MA 02111-1307 USA
	32	***********************************************************************/
	33
	34	/---------------------------- Headerfiles ----------------------------/
	35	#include <common.h>
	36	#include <mpc8xx.h>
	37	#include <commproc.h>
	38	#include <i2c.h>
	39	#include <command.h>
e2211743 WD	40	#include <malloc.h>
e2211743 WD	41	#include <post.h>
281e00a3	42	#include <serial.h>
e2211743 WD	43
	44	#include <linux/types.h>
	45	#include <linux/string.h> /* for strdup */
	46
d87080b7 WD	47	DECLARE_GLOBAL_DATA_PTR;
d87080b7 WD	48
e2211743 WD	49	/------------------------ Local prototypes ---------------------------/
e2211743 WD	50	static long int dram_size (long int, long int *, long int);
4532cb69 WD	51	static void kbd_init (void);
4532cb69 WD	52	static int compare_magic (uchar kbd_data, uchar str);
e2211743 WD	53
	54
	55	/--------------------- Local macros and constants --------------------/
	56	#define _NOT_USED_ 0xFFFFFFFF
	57
4532cb69 WD	58	#ifdef CONFIG_MODEM_SUPPORT
	59	static int key_pressed(void);
	60	extern void disable_putc(void);
	61	#endif /* CONFIG_MODEM_SUPPORT */
	62
e2211743 WD	63	/*
	64	* 66 MHz SDRAM access using UPM A
	65	*/
	66	const uint sdram_table[] =
	67	{
6d0f6bcf	68	#if defined(CONFIG_SYS_MEMORY_75) \|\| defined(CONFIG_SYS_MEMORY_8E)
e2211743 WD	69	/*
	70	* Single Read. (Offset 0 in UPM RAM)
	71	*/
	72	0x1F0DFC04, 0xEEAFBC04, 0x11AF7C04, 0xEFBAFC00,
	73	0x1FF5FC47, /* last */
	74	/*
	75	* SDRAM Initialization (offset 5 in UPM RAM)
	76	*
8bde7f77 WD	77	* This is no UPM entry point. The following definition uses
	78	* the remaining space to establish an initialization
	79	* sequence, which is executed by a RUN command.
e2211743 WD	80	*
	81	*/
	82	0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	83	/*
	84	* Burst Read. (Offset 8 in UPM RAM)
	85	*/
	86	0x1F0DFC04, 0xEEAFBC04, 0x10AF7C04, 0xF0AFFC00,
	87	0xF0AFFC00, 0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
	88	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	89	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	90	/*
	91	* Single Write. (Offset 18 in UPM RAM)
	92	*/
	93	0x1F2DFC04, 0xEEABBC00, 0x01B27C04, 0x1FF5FC47, /* last */
	94	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	95	/*
	96	* Burst Write. (Offset 20 in UPM RAM)
	97	*/
	98	0x1F0DFC04, 0xEEABBC00, 0x10A77C00, 0xF0AFFC00,
	99	0xF0AFFC00, 0xE1BAFC04, 0x01FF5FC47, /* last */
	100	_NOT_USED_,
	101	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	102	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	103	/*
	104	* Refresh (Offset 30 in UPM RAM)
	105	*/
	106	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	107	0xFFFFFC84, 0xFFFFFC07, /* last */
	108	_NOT_USED_, _NOT_USED_,
	109	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	110	/*
	111	* Exception. (Offset 3c in UPM RAM)
	112	*/
	113	0x7FFFFC07, /* last */
	114	0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
	115	#endif
6d0f6bcf	116	#ifdef CONFIG_SYS_MEMORY_7E
e2211743 WD	117	/*
	118	* Single Read. (Offset 0 in UPM RAM)
	119	*/
	120	0x0E2DBC04, 0x11AF7C04, 0xEFBAFC00, 0x1FF5FC47, /* last */
	121	_NOT_USED_,
	122	/*
	123	* SDRAM Initialization (offset 5 in UPM RAM)
	124	*
8bde7f77 WD	125	* This is no UPM entry point. The following definition uses
	126	* the remaining space to establish an initialization
	127	* sequence, which is executed by a RUN command.
e2211743 WD	128	*
	129	*/
	130	0x1FF5FC34, 0xEFEABC34, 0x1FB57C35, /* last */
	131	/*
	132	* Burst Read. (Offset 8 in UPM RAM)
	133	*/
	134	0x0E2DBC04, 0x10AF7C04, 0xF0AFFC00, 0xF0AFFC00,
	135	0xF1AFFC00, 0xEFBAFC00, 0x1FF5FC47, /* last */
8bde7f77	136	_NOT_USED_,
e2211743 WD	137	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	138	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	139	/*
	140	* Single Write. (Offset 18 in UPM RAM)
	141	*/
	142	0x0E29BC04, 0x01B27C04, 0x1FF5FC47, /* last */
	143	_NOT_USED_,
	144	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	145	/*
	146	* Burst Write. (Offset 20 in UPM RAM)
	147	*/
	148	0x0E29BC04, 0x10A77C00, 0xF0AFFC00, 0xF0AFFC00,
	149	0xE1BAFC04, 0x1FF5FC47, /* last */
8bde7f77	150	_NOT_USED_, _NOT_USED_,
e2211743 WD	151	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	152	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	153	/*
	154	* Refresh (Offset 30 in UPM RAM)
	155	*/
	156	0x1FFD7C84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	157	0xFFFFFC84, 0xFFFFFC07, /* last */
	158	_NOT_USED_, _NOT_USED_,
	159	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	160	/*
	161	* Exception. (Offset 3c in UPM RAM)
	162	*/
	163	0x7FFFFC07, /* last */
	164	0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
	165	#endif
	166	};
	167
	168	/*
	169	* Check Board Identity:
	170	*
	171	*/
	172
	173	/***********************************************************************
	174	F* Function: int checkboard (void) PAZ*
	175	*
	176	P* Parameters: none
	177	P*
	178	P* Returnvalue: int - 0 is always returned
	179	*
	180	Z* Intention: This function is the checkboard() method implementation
	181	Z* for the lwmon board. Only a standard message is printed.
	182	*
	183	D* Design: wd@denx.de
	184	C* Coding: wd@denx.de
	185	V* Verification: dzu@denx.de
	186	***********************************************************************/
	187	int checkboard (void)
	188	{
ee073a55	189	puts ("Board: LICCON Konsole LCD3\n");
e2211743 WD	190	return (0);
	191	}
	192
	193	/***********************************************************************
9973e3c6	194	F* Function: phys_size_t initdram (int board_type) PAZ*
e2211743 WD	195	*
	196	P* Parameters: int board_type
	197	P* - Usually type of the board - ignored here.
	198	P*
	199	P* Returnvalue: long int
	200	P* - Size of initialized memory
	201	*
	202	Z* Intention: This function is the initdram() method implementation
	203	Z* for the lwmon board.
	204	Z* The memory controller is initialized to access the
	205	Z* DRAM.
	206	*
	207	D* Design: wd@denx.de
	208	C* Coding: wd@denx.de
	209	V* Verification: dzu@denx.de
	210	***********************************************************************/
9973e3c6	211	phys_size_t initdram (int board_type)
e2211743	212	{
6d0f6bcf	213	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
e2211743 WD	214	volatile memctl8xx_t *memctl = &immr->im_memctl;
	215	long int size_b0;
	216	long int size8, size9;
	217	int i;
	218
	219	/*
	220	* Configure UPMA for SDRAM
	221	*/
	222	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
	223
6d0f6bcf	224	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
e2211743 WD	225
e2211743 WD	226	/* burst length=4, burst type=sequential, CAS latency=2 */
6d0f6bcf	227	memctl->memc_mar = CONFIG_SYS_MAR;
e2211743 WD	228
	229	/*
	230	* Map controller bank 3 to the SDRAM bank at preliminary address.
	231	*/
6d0f6bcf JCPV	232	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
6d0f6bcf JCPV	233	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
e2211743 WD	234
e2211743 WD	235	/* initialize memory address register */
6d0f6bcf	236	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL; /* refresh not enabled yet */
e2211743 WD	237
	238	/* mode initialization (offset 5) */
	239	udelay (200); /* 0x80006105 */
	240	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS3 \| MCR_MLCF (1) \| MCR_MAD (0x05);
	241
	242	/* run 2 refresh sequence with 4-beat refresh burst (offset 0x30) */
	243	udelay (1); /* 0x80006130 */
	244	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS3 \| MCR_MLCF (1) \| MCR_MAD (0x30);
	245	udelay (1); /* 0x80006130 */
	246	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS3 \| MCR_MLCF (1) \| MCR_MAD (0x30);
	247
	248	udelay (1); /* 0x80006106 */
	249	memctl->memc_mcr = MCR_OP_RUN \| MCR_MB_CS3 \| MCR_MLCF (1) \| MCR_MAD (0x06);
	250
2535d602	251	memctl->memc_mamr \|= MAMR_PTAE; /* refresh enabled */
e2211743 WD	252
	253	udelay (200);
	254
	255	/* Need at least 10 DRAM accesses to stabilize */
	256	for (i = 0; i < 10; ++i) {
	257	volatile unsigned long *addr =
	258	(volatile unsigned long *) SDRAM_BASE3_PRELIM;
	259	unsigned long val;
	260
	261	val = *(addr + i);
	262	*(addr + i) = val;
	263	}
	264
	265	/*
	266	* Check Bank 0 Memory Size for re-configuration
	267	*
	268	* try 8 column mode
	269	*/
6d0f6bcf	270	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
e2211743 WD	271
	272	udelay (1000);
	273
	274	/*
	275	* try 9 column mode
	276	*/
6d0f6bcf	277	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
e2211743 WD	278
	279	if (size8 < size9) { /* leave configuration at 9 columns */
	280	size_b0 = size9;
6d0f6bcf	281	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL \| MAMR_PTAE;
e2211743 WD	282	udelay (500);
	283	} else { /* back to 8 columns */
	284	size_b0 = size8;
6d0f6bcf	285	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL \| MAMR_PTAE;
e2211743 WD	286	udelay (500);
	287	}
	288
	289	/*
	290	* Final mapping:
	291	*/
	292
	293	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) \|
	294	OR_CSNT_SAM \| OR_G5LS \| SDRAM_TIMING;
6d0f6bcf	295	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
e2211743 WD	296	udelay (1000);
	297
	298	return (size_b0);
	299	}
	300
	301	/***********************************************************************
	302	F* Function: static long int dram_size (long int mamr_value,
	303	F* long int *base,
	304	F* long int maxsize) PAZ*
	305	*
	306	P* Parameters: long int mamr_value
	307	P* - Value for MAMR for the test
	308	P* long int *base
	309	P* - Base address for the test
	310	P* long int maxsize
	311	P* - Maximum size to test for
	312	P*
	313	P* Returnvalue: long int
	314	P* - Size of probed memory
	315	*
	316	Z* Intention: Check memory range for valid RAM. A simple memory test
	317	Z* determines the actually available RAM size between
	318	Z* addresses `base' and `base + maxsize'. Some (not all)
	319	Z* hardware errors are detected:
	320	Z* - short between address lines
	321	Z* - short between data lines
	322	*
	323	D* Design: wd@denx.de
	324	C* Coding: wd@denx.de
	325	V* Verification: dzu@denx.de
	326	***********************************************************************/
	327	static long int dram_size (long int mamr_value, long int *base, long int maxsize)
	328	{
6d0f6bcf	329	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
e2211743	330	volatile memctl8xx_t *memctl = &immr->im_memctl;
e2211743 WD	331
	332	memctl->memc_mamr = mamr_value;
	333
c83bf6a2	334	return (get_ram_size(base, maxsize));
e2211743 WD	335	}
	336
	337	/* ------------------------------------------------------------------------- */
	338
	339	#ifndef PB_ENET_TENA
	340	# define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
	341	#endif
	342
	343	/***********************************************************************
c837dcb1	344	F* Function: int board_early_init_f (void) PAZ*
e2211743 WD	345	*
	346	P* Parameters: none
	347	P*
	348	P* Returnvalue: int
	349	P* - 0 is always returned.
	350	*
c837dcb1	351	Z* Intention: This function is the board_early_init_f() method implementation
e2211743 WD	352	Z* for the lwmon board.
	353	Z* Disable Ethernet TENA on Port B.
	354	*
	355	D* Design: wd@denx.de
	356	C* Coding: wd@denx.de
	357	V* Verification: dzu@denx.de
	358	***********************************************************************/
c837dcb1	359	int board_early_init_f (void)
e2211743	360	{
6d0f6bcf	361	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
e2211743 WD	362
	363	/* Disable Ethernet TENA on Port B
	364	* Necessary because of pull up in COM3 port.
	365	*
	366	* This is just a preliminary fix, intended to turn off TENA
	367	* as soon as possible to avoid noise on the network. Once
	368