[people/ms/u-boot.git] / board / lwmon5 / sdram.c

/*
 * (C) Copyright 2006
 * Sylvie Gohl,		    AMCC/IBM, gohl.sylvie@fr.ibm.com
 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
 * Thierry Roman,	    AMCC/IBM, thierry_roman@fr.ibm.com
 * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com
 * Robert Snyder,	    AMCC/IBM, rob.snyder@fr.ibm.com
 *
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* define DEBUG for debugging output (obviously ;-)) */
#if 0
#define DEBUG
#endif

#include <common.h>
#include <asm/processor.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <ppc440.h>

#include "sdram.h"

/*
 * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
 * region. Right now the cache should still be disabled in U-Boot because of the
 * EMAC driver, that need it's buffer descriptor to be located in non cached
 * memory.
 *
 * If at some time this restriction doesn't apply anymore, just define
 * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
 * everything correctly.
 */
#ifdef CFG_ENABLE_SDRAM_CACHE
#define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
#else
#define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
#endif

void dcbz_area(u32 start_address, u32 num_bytes);
void dflush(void);

static u32 is_ecc_enabled(void)
{
	u32 val;

	mfsdram(DDR0_22, val);
	val &= DDR0_22_CTRL_RAW_MASK;
	if (val)
		return 1;
	else
		return 0;
}

void board_add_ram_info(int use_default)
{
	PPC440_SYS_INFO board_cfg;
	u32 val;

	if (is_ecc_enabled())
		puts(" (ECC");
	else
		puts(" (ECC not");

	get_sys_info(&board_cfg);
	printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000);

	mfsdram(DDR0_03, val);
	val = DDR0_03_CASLAT_DECODE(val);
	printf(", CL%d)", val);
}

static int wait_for_dlllock(void)
{
	u32 val;
	int wait = 0;

	/*
	 * Wait for the DCC master delay line to finish calibration
	 */
	mtdcr(ddrcfga, DDR0_17);
	val = DDR0_17_DLLLOCKREG_UNLOCKED;

	while (wait != 0xffff) {
		val = mfdcr(ddrcfgd);
		if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
			/* dlllockreg bit on */
			return 0;
		else
			wait++;
	}
	debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
	debug("Waiting for dlllockreg bit to raise\n");

	return -1;
}

#if defined(CONFIG_DDR_DATA_EYE)
int wait_for_dram_init_complete(void)
{
	u32 val;
	int wait = 0;

	/*
	 * Wait for 'DRAM initialization complete' bit in status register
	 */
	mtdcr(ddrcfga, DDR0_00);

	while (wait != 0xffff) {
		val = mfdcr(ddrcfgd);
		if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
			/* 'DRAM initialization complete' bit */
			return 0;
		else
			wait++;
	}

	debug("DRAM initialization complete bit in status register did not rise\n");

	return -1;
}

#define NUM_TRIES 64
#define NUM_READS 10

void denali_core_search_data_eye(u32 start_addr, u32 memory_size)
{
	int k, j;
	u32 val;
	u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
	u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
	u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
	u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
	volatile u32 *ram_pointer;
	u32 test[NUM_TRIES] = {
		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };

	ram_pointer = (volatile u32 *)start_addr;

	for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
		/*for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {*/

		/*
		 * De-assert 'start' parameter.
		 */
		mtdcr(ddrcfga, DDR0_02);
		val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
		mtdcr(ddrcfgd, val);

		/*
		 * Set 'wr_dqs_shift'
		 */
		mtdcr(ddrcfga, DDR0_09);
		val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
			| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
		mtdcr(ddrcfgd, val);

		/*
		 * Set 'dqs_out_shift' = wr_dqs_shift + 32
		 */
		dqs_out_shift = wr_dqs_shift + 32;
		mtdcr(ddrcfga, DDR0_22);
		val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
			| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
		mtdcr(ddrcfgd, val);

		passing_cases = 0;

		for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
			/*for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {*/
			/*
			 * Set 'dll_dqs_delay_X'.
			 */
			/* dll_dqs_delay_0 */
			mtdcr(ddrcfga, DDR0_17);
			val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
				| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
			mtdcr(ddrcfgd, val);
			/* dll_dqs_delay_1 to dll_dqs_delay_4 */
			mtdcr(ddrcfga, DDR0_18);
			val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
				| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
				| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
				| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
				| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
			mtdcr(ddrcfgd, val);
			/* dll_dqs_delay_5 to dll_dqs_delay_8 */
			mtdcr(ddrcfga, DDR0_19);
			val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
				| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
				| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
				| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
				| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
			mtdcr(ddrcfgd, val);

			ppcMsync();
			ppcMbar();

			/*
			 * Assert 'start' parameter.
			 */
			mtdcr(ddrcfga, DDR0_02);
			val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
			mtdcr(ddrcfgd, val);

			ppcMsync();
			ppcMbar();

			/*
			 * Wait for the DCC master delay line to finish calibration
			 */
			if (wait_for_dlllock() != 0) {
				printf("dlllock did not occur !!!\n");
				printf("denali_core_search_data_eye!!!\n");
				printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
				       wr_dqs_shift, dll_dqs_delay_X);
				hang();
			}
			ppcMsync();
			ppcMbar();

			if (wait_for_dram_init_complete() != 0) {
				printf("dram init complete did not occur !!!\n");
				printf("denali_core_search_data_eye!!!\n");
				printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
				       wr_dqs_shift, dll_dqs_delay_X);
				hang();
			}
			udelay(100);  /* wait 100us to ensure init is really completed !!! */

			/* write values */
			for (j=0; j<NUM_TRIES; j++) {
				ram_pointer[j] = test[j];

				/* clear any cache at ram location */
				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
			}

			/* read values back */
			for (j=0; j<NUM_TRIES; j++) {
				for (k=0; k<NUM_READS; k++) {
					/* clear any cache at ram location */
					__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));

					if (ram_pointer[j] != test[j])
						break;
				}

				/* read error */
				if (k != NUM_READS)
					break;
			}

			/* See if the dll_dqs_delay_X value passed.*/
			if (j < NUM_TRIES) {
				/* Failed */
				passing_cases = 0;
				/* break; */
			} else {
				/* Passed */
				if (passing_cases == 0)
					dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
				passing_cases++;
				if (passing_cases >= max_passing_cases) {
					max_passing_cases = passing_cases;
					wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
					dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
					dll_dqs_delay_X_end_window = dll_dqs_delay_X;
				}
			}

			/*
			 * De-assert 'start' parameter.
			 */
			mtdcr(ddrcfga, DDR0_02);
			val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
			mtdcr(ddrcfgd, val);

		} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */

	} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */

	/*
	 * Largest passing window is now detected.
	 */

	/* Compute dll_dqs_delay_X value */
	dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
	wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;

	debug("DQS calibration - Window detected:\n");
	debug("max_passing_cases = %d\n", max_passing_cases);
	debug("wr_dqs_shift	 = %d\n", wr_dqs_shift);
	debug("dll_dqs_delay_X	 = %d\n", dll_dqs_delay_X);
	debug("dll_dqs_delay_X window = %d - %d\n",
	      dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);

	/*
	 * De-assert 'start' parameter.
	 */
	mtdcr(ddrcfga, DDR0_02);
	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_OFF;
	mtdcr(ddrcfgd, val);

	/*
	 * Set 'wr_dqs_shift'
	 */
	mtdcr(ddrcfga, DDR0_09);
	val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
		| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
	mtdcr(ddrcfgd, val);
	debug("DDR0_09=0x%08lx\n", val);

	/*
	 * Set 'dqs_out_shift' = wr_dqs_shift + 32
	 */
	dqs_out_shift = wr_dqs_shift + 32;
	mtdcr(ddrcfga, DDR0_22);
	val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
		| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
	mtdcr(ddrcfgd, val);
	debug("DDR0_22=0x%08lx\n", val);

	/*
	 * Set 'dll_dqs_delay_X'.
	 */
	/* dll_dqs_delay_0 */
	mtdcr(ddrcfga, DDR0_17);
	val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
		| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
	mtdcr(ddrcfgd, val);
	debug("DDR0_17=0x%08lx\n", val);

	/* dll_dqs_delay_1 to dll_dqs_delay_4 */
	mtdcr(ddrcfga, DDR0_18);
	val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
		| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
		| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
		| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
		| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
	mtdcr(ddrcfgd, val);
	debug("DDR0_18=0x%08lx\n", val);

	/* dll_dqs_delay_5 to dll_dqs_delay_8 */
	mtdcr(ddrcfga, DDR0_19);
	val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
		| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
		| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
		| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
		| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
	mtdcr(ddrcfgd, val);
	debug("DDR0_19=0x%08lx\n", val);

	/*
	 * Assert 'start' parameter.
	 */
	mtdcr(ddrcfga, DDR0_02);
	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) | DDR0_02_START_ON;
	mtdcr(ddrcfgd, val);

	ppcMsync();
	ppcMbar();

	/*
	 * Wait for the DCC master delay line to finish calibration
	 */
	if (wait_for_dlllock() != 0) {
		printf("dlllock did not occur !!!\n");
		hang();
	}
	ppcMsync();
	ppcMbar();

	if (wait_for_dram_init_complete() != 0) {
		printf("dram init complete did not occur !!!\n");
		hang();
	}
	udelay(100);  /* wait 100us to ensure init is really completed !!! */
}
#endif /* CONFIG_DDR_DATA_EYE */

#ifdef CONFIG_DDR_ECC
static void wait_ddr_idle(void)
{
	/*
	 * Controller idle status cannot be determined for Denali
	 * DDR2 code. Just return here.
	 */
}

static void blank_string(int size)
{
	int i;

	for (i=0; i<size; i++)
		putc('\b');
	for (i=0; i<size; i++)
		putc(' ');
	for (i=0; i<size; i++)
		putc('\b');
}

static void program_ecc(u32 start_address,
			u32 num_bytes,
			u32 tlb_word2_i_value)
{
	u32 current_address;
	u32 end_address;
	u32 address_increment;
	u32 val;
	char str[] = "ECC generation -";
	char slash[] = "\\|/-\\|/-";
	int loop = 0;
	int loopi = 0;

	current_address = start_address;

	sync();
	eieio();
	wait_ddr_idle();

	if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
		/* ECC bit set method for non-cached memory */
		address_increment = 4;
		end_address = current_address + num_bytes;

		puts(str);

		while (current_address < end_address) {
			*((u32 *)current_address) = 0x00000000;
			current_address += address_increment;

			if ((loop++ % (2 << 20)) == 0) {
				putc('\b');
				putc(slash[loopi++ % 8]);
			}
		}

		blank_string(strlen(str));
	} else {
		/* ECC bit set method for cached memory */
#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
		/*
		 * Some boards (like lwmon5) need to preserve the memory
		 * content upon ECC generation (for the log-buffer).
		 * Therefore we don't fill the memory with a pattern or
		 * just zero it, but write the same values back that are
		 * already in the memory cells.
		 */
		address_increment = CFG_CACHELINE_SIZE;
		end_address = current_address + num_bytes;

		current_address = start_address;
		while (current_address < end_address) {
			/*
			 * TODO: Th following sequence doesn't work correctly.
			 * Just invalidating and flushing the cache doesn't
			 * seem to trigger the re-write of the memory.
			 */
			ppcDcbi(current_address);
			ppcDcbf(current_address);
			current_address += CFG_CACHELINE_SIZE;
		}
#else
		dcbz_area(start_address, num_bytes);
		dflush();
#endif
	}

	sync();
	eieio();
	wait_ddr_idle();

	/* Clear error status */
	mfsdram(DDR0_00, val);
	mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);

	/* Set 'int_mask' parameter to functionnal value */
	mfsdram(DDR0_01, val);
	mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) | DDR0_01_INT_MASK_ALL_OFF));

	sync();
	eieio();
	wait_ddr_idle();
}
#endif

/*************************************************************************
 *
 * initdram -- 440EPx's DDR controller is a DENALI Core
 *
 ************************************************************************/
long int initdram (int board_type)
{
#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
	/* CL=3 */
	mtsdram(DDR0_02, 0x00000000);

	mtsdram(DDR0_00, 0x0000190A);
	mtsdram(DDR0_01, 0x01000000);
	mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */

	mtsdram(DDR0_04, 0x0A030300);
	mtsdram(DDR0_05, 0x02020308);
	mtsdram(DDR0_06, 0x0103C812);
	mtsdram(DDR0_07, 0x00090100);
	mtsdram(DDR0_08, 0x02c80001);
	mtsdram(DDR0_09, 0x00011D5F);
	mtsdram(DDR0_10, 0x00000300);
	mtsdram(DDR0_11, 0x000CC800);
	mtsdram(DDR0_12, 0x00000003);
	mtsdram(DDR0_14, 0x00000000);
	mtsdram(DDR0_17, 0x1e000000);
	mtsdram(DDR0_18, 0x1e1e1e1e);
	mtsdram(DDR0_19, 0x1e1e1e1e);
	mtsdram(DDR0_20, 0x0B0B0B0B);
	mtsdram(DDR0_21, 0x0B0B0B0B);
#ifdef CONFIG_DDR_ECC
	mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC	*/
#else
	mtsdram(DDR0_22, 0x00267F0B);
#endif

	mtsdram(DDR0_23, 0x01000000);
	mtsdram(DDR0_24, 0x01010001);

	mtsdram(DDR0_26, 0x2D93028A);
	mtsdram(DDR0_27, 0x0784682B);

	mtsdram(DDR0_28, 0x00000080);
	mtsdram(DDR0_31, 0x00000000);
	mtsdram(DDR0_42, 0x01000006);

	mtsdram(DDR0_43, 0x030A0200);
	mtsdram(DDR0_44, 0x00000003);
	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
#else
	/* CL=4 */
	mtsdram(DDR0_02, 0x00000000);

	mtsdram(DDR0_00, 0x0000190A);
	mtsdram(DDR0_01, 0x01000000);
	mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */

	mtsdram(DDR0_04, 0x0B030300);
	mtsdram(DDR0_05, 0x02020308);
	mtsdram(DDR0_06, 0x0003C812);
	mtsdram(DDR0_07, 0x00090100);
	mtsdram(DDR0_08, 0x03c80001);
	mtsdram(DDR0_09, 0x00011D5F);
	mtsdram(DDR0_10, 0x00000300);
	mtsdram(DDR0_11, 0x000CC800);
	mtsdram(DDR0_12, 0x00000003);
	mtsdram(DDR0_14, 0x00000000);
	mtsdram(DDR0_17, 0x1e000000);
	mtsdram(DDR0_18, 0x1e1e1e1e);
	mtsdram(DDR0_19, 0x1e1e1e1e);
	mtsdram(DDR0_20, 0x0B0B0B0B);
	mtsdram(DDR0_21, 0x0B0B0B0B);
#ifdef CONFIG_DDR_ECC
	mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC       */
#else
	mtsdram(DDR0_22, 0x00267F0B);
#endif

	mtsdram(DDR0_23, 0x01000000);
	mtsdram(DDR0_24, 0x01010001);

	mtsdram(DDR0_26, 0x2D93028A);
	mtsdram(DDR0_27, 0x0784682B);

	mtsdram(DDR0_28, 0x00000080);
	mtsdram(DDR0_31, 0x00000000);
	mtsdram(DDR0_42, 0x01000008);

	mtsdram(DDR0_43, 0x050A0200);
	mtsdram(DDR0_44, 0x00000005);
	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
#endif

	wait_for_dlllock();

	/*
	 * Program tlb entries for this size (dynamic)
	 */
	program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);

	/*
	 * Setup 2nd TLB with same physical address but different virtual address
	 * with cache enabled. This is done for fast ECC generation.
	 */
	program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);

#ifdef CONFIG_DDR_DATA_EYE
	/*
	 * Perform data eye search if requested.
	 */
	denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
#endif

#ifdef CONFIG_DDR_ECC
	/*
	 * If ECC is enabled, initialize the parity bits.
	 */
	program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
#endif

	/*
	 * Clear possible errors resulting from data-eye-search.
	 * If not done, then we could get an interrupt later on when
	 * exceptions are enabled.
	 */
	set_mcsr(get_mcsr());

	return (CFG_MBYTES_SDRAM << 20);
}
Commit	Line	Data
b765ffb7 SR	1	/*
b765ffb7 SR	2	* (C) Copyright 2006
83b4cfa3	3	* Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
b765ffb7	4	* Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
83b4cfa3 WD	5	* Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
	6	* Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
	7	* Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
b765ffb7 SR	8	*
	9	* (C) Copyright 2007
	10	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	/* define DEBUG for debugging output (obviously ;-)) */
	29	#if 0
	30	#define DEBUG
	31	#endif
	32
	33	#include <common.h>
	34	#include <asm/processor.h>
	35	#include <asm/mmu.h>
	36	#include <asm/io.h>
	37	#include <ppc440.h>
	38
	39	#include "sdram.h"
	40
	41	/*
	42	* This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
	43	* region. Right now the cache should still be disabled in U-Boot because of the
	44	* EMAC driver, that need it's buffer descriptor to be located in non cached
	45	* memory.
	46	*
	47	* If at some time this restriction doesn't apply anymore, just define
	48	* CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
	49	* everything correctly.
	50	*/
	51	#ifdef CFG_ENABLE_SDRAM_CACHE
83b4cfa3	52	#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
b765ffb7	53	#else
83b4cfa3	54	#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
b765ffb7 SR	55	#endif
b765ffb7 SR	56
b765ffb7 SR	57	void dcbz_area(u32 start_address, u32 num_bytes);
	58	void dflush(void);
	59
b765ffb7 SR	60	static u32 is_ecc_enabled(void)
	61	{
	62	u32 val;
	63
	64	mfsdram(DDR0_22, val);
	65	val &= DDR0_22_CTRL_RAW_MASK;
	66	if (val)
	67	return 1;
	68	else
	69	return 0;
	70	}
	71
	72	void board_add_ram_info(int use_default)
	73	{
	74	PPC440_SYS_INFO board_cfg;
	75	u32 val;
	76
	77	if (is_ecc_enabled())
	78	puts(" (ECC");
	79	else
	80	puts(" (ECC not");
	81
	82	get_sys_info(&board_cfg);
	83	printf(" enabled, %d MHz", (board_cfg.freqPLB * 2) / 1000000);
	84
	85	mfsdram(DDR0_03, val);
	86	val = DDR0_03_CASLAT_DECODE(val);
	87	printf(", CL%d)", val);
	88	}
b765ffb7 SR	89
	90	static int wait_for_dlllock(void)
	91	{
	92	u32 val;
	93	int wait = 0;
	94
	95	/*
	96	* Wait for the DCC master delay line to finish calibration
	97	*/
	98	mtdcr(ddrcfga, DDR0_17);
	99	val = DDR0_17_DLLLOCKREG_UNLOCKED;
	100
	101	while (wait != 0xffff) {
	102	val = mfdcr(ddrcfgd);
	103	if ((val & DDR0_17_DLLLOCKREG_MASK) == DDR0_17_DLLLOCKREG_LOCKED)
	104	/* dlllockreg bit on */
	105	return 0;
	106	else
	107	wait++;
	108	}
	109	debug("0x%04x: DDR0_17 Value (dlllockreg bit): 0x%08x\n", wait, val);
	110	debug("Waiting for dlllockreg bit to raise\n");
	111
	112	return -1;
	113	}
	114
	115	#if defined(CONFIG_DDR_DATA_EYE)
	116	int wait_for_dram_init_complete(void)
	117	{
	118	u32 val;
	119	int wait = 0;
	120
	121	/*
	122	* Wait for 'DRAM initialization complete' bit in status register
	123	*/
	124	mtdcr(ddrcfga, DDR0_00);
	125
	126	while (wait != 0xffff) {
	127	val = mfdcr(ddrcfgd);
	128	if ((val & DDR0_00_INT_STATUS_BIT6) == DDR0_00_INT_STATUS_BIT6)
	129	/* 'DRAM initialization complete' bit */
	130	return 0;
	131	else
	132	wait++;
	133	}
	134
	135	debug("DRAM initialization complete bit in status register did not rise\n");
	136
	137	return -1;
	138	}
	139
	140	#define NUM_TRIES 64
	141	#define NUM_READS 10
	142
	143	void denali_core_search_data_eye(u32 start_addr, u32 memory_size)
	144	{
	145	int k, j;
	146	u32 val;
	147	u32 wr_dqs_shift, dqs_out_shift, dll_dqs_delay_X;
	148	u32 max_passing_cases = 0, wr_dqs_shift_with_max_passing_cases = 0;
	149	u32 passing_cases = 0, dll_dqs_delay_X_sw_val = 0;
	150	u32 dll_dqs_delay_X_start_window = 0, dll_dqs_delay_X_end_window = 0;
	151	volatile u32 *ram_pointer;
	152	u32 test[NUM_TRIES] = {
153	0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
154	0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
155	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
156	0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
157	0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
158	0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
159	0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
160	0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
161	0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
162	0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
163	0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
164	0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
165	0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
166	0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
167	0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
168	0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };
169
170	ram_pointer = (volatile u32 *)start_addr;
171
172	for (wr_dqs_shift = 64; wr_dqs_shift < 96; wr_dqs_shift++) {
173	/for (wr_dqs_shift=1; wr_dqs_shift<96; wr_dqs_shift++) {/
174
175	/*
176	* De-assert 'start' parameter.
177	*/
178	mtdcr(ddrcfga, DDR0_02);
179	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) \| DDR0_02_START_OFF;
180	mtdcr(ddrcfgd, val);
181
182	/*
183	* Set 'wr_dqs_shift'
184	*/
185	mtdcr(ddrcfga, DDR0_09);
186	val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
187	\| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
188	mtdcr(ddrcfgd, val);
189
190	/*
191	* Set 'dqs_out_shift' = wr_dqs_shift + 32
192	*/
193	dqs_out_shift = wr_dqs_shift + 32;
194	mtdcr(ddrcfga, DDR0_22);
195	val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
196	\| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
197	mtdcr(ddrcfgd, val);
198
199	passing_cases = 0;
200
201	for (dll_dqs_delay_X = 1; dll_dqs_delay_X < 64; dll_dqs_delay_X++) {
202	/for (dll_dqs_delay_X=1; dll_dqs_delay_X<128; dll_dqs_delay_X++) {/
203	/*
204	* Set 'dll_dqs_delay_X'.
205	*/
206	/* dll_dqs_delay_0 */
207	mtdcr(ddrcfga, DDR0_17);
208	val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
209	\| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
210	mtdcr(ddrcfgd, val);
211	/* dll_dqs_delay_1 to dll_dqs_delay_4 */
212	mtdcr(ddrcfga, DDR0_18);
213	val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
214	\| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
215	\| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
216	\| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
217	\| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
218	mtdcr(ddrcfgd, val);
219	/* dll_dqs_delay_5 to dll_dqs_delay_8 */
220	mtdcr(ddrcfga, DDR0_19);
221	val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
222	\| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
223	\| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
224	\| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
225	\| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
226	mtdcr(ddrcfgd, val);
227
228	ppcMsync();
229	ppcMbar();
230
231	/*
232	* Assert 'start' parameter.
233	*/
234	mtdcr(ddrcfga, DDR0_02);
235	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) \| DDR0_02_START_ON;
236	mtdcr(ddrcfgd, val);
237
238	ppcMsync();
239	ppcMbar();
240
241	/*
242	* Wait for the DCC master delay line to finish calibration
243	*/
244	if (wait_for_dlllock() != 0) {
245	printf("dlllock did not occur !!!\n");
246	printf("denali_core_search_data_eye!!!\n");
247	printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
248	wr_dqs_shift, dll_dqs_delay_X);
249	hang();
250	}
251	ppcMsync();
252	ppcMbar();
253
254	if (wait_for_dram_init_complete() != 0) {
255	printf("dram init complete did not occur !!!\n");
256	printf("denali_core_search_data_eye!!!\n");
257	printf("wr_dqs_shift = %d - dll_dqs_delay_X = %d\n",
258	wr_dqs_shift, dll_dqs_delay_X);
259	hang();
260	}
261	udelay(100); /* wait 100us to ensure init is really completed !!! */
262
263	/* write values */
264	for (j=0; j<NUM_TRIES; j++) {
265	ram_pointer[j] = test[j];
266
267	/* clear any cache at ram location */
268	__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
269	}
270
271	/* read values back */
272	for (j=0; j<NUM_TRIES; j++) {
273	for (k=0; k<NUM_READS; k++) {
274	/* clear any cache at ram location */
275	__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));
276
277	if (ram_pointer[j] != test[j])
278	break;
279	}
280
281	/* read error */
282	if (k != NUM_READS)
283	break;
284	}
285
286	/* See if the dll_dqs_delay_X value passed.*/
287	if (j < NUM_TRIES) {
288	/* Failed */
289	passing_cases = 0;
290	/* break; */
291	} else {
292	/* Passed */
293	if (passing_cases == 0)
294	dll_dqs_delay_X_sw_val = dll_dqs_delay_X;
295	passing_cases++;
296	if (passing_cases >= max_passing_cases) {
297	max_passing_cases = passing_cases;
298	wr_dqs_shift_with_max_passing_cases = wr_dqs_shift;
299	dll_dqs_delay_X_start_window = dll_dqs_delay_X_sw_val;
300	dll_dqs_delay_X_end_window = dll_dqs_delay_X;
301	}
302	}
303
304	/*
305	* De-assert 'start' parameter.
306	*/
307	mtdcr(ddrcfga, DDR0_02);
308	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) \| DDR0_02_START_OFF;
309	mtdcr(ddrcfgd, val);
310
311	} /* for (dll_dqs_delay_X=0; dll_dqs_delay_X<128; dll_dqs_delay_X++) */
312
313	} /* for (wr_dqs_shift=0; wr_dqs_shift<96; wr_dqs_shift++) */
314
315	/*
316	* Largest passing window is now detected.
317	*/
318
319	/* Compute dll_dqs_delay_X value */
320	dll_dqs_delay_X = (dll_dqs_delay_X_end_window + dll_dqs_delay_X_start_window) / 2;
321	wr_dqs_shift = wr_dqs_shift_with_max_passing_cases;
322
323	debug("DQS calibration - Window detected:\n");
324	debug("max_passing_cases = %d\n", max_passing_cases);
83b4cfa3 WD	325	debug("wr_dqs_shift = %d\n", wr_dqs_shift);
83b4cfa3 WD	326	debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
b765ffb7 SR	327	debug("dll_dqs_delay_X window = %d - %d\n",
	328	dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
	329
	330	/*
	331	* De-assert 'start' parameter.
	332	*/
	333	mtdcr(ddrcfga, DDR0_02);
	334	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) \| DDR0_02_START_OFF;
	335	mtdcr(ddrcfgd, val);
	336
	337	/*
	338	* Set 'wr_dqs_shift'
	339	*/
	340	mtdcr(ddrcfga, DDR0_09);
	341	val = (mfdcr(ddrcfgd) & ~DDR0_09_WR_DQS_SHIFT_MASK)
	342	\| DDR0_09_WR_DQS_SHIFT_ENCODE(wr_dqs_shift);
	343	mtdcr(ddrcfgd, val);
	344	debug("DDR0_09=0x%08lx\n", val);
	345
	346	/*
	347	* Set 'dqs_out_shift' = wr_dqs_shift + 32
	348	*/
	349	dqs_out_shift = wr_dqs_shift + 32;
	350	mtdcr(ddrcfga, DDR0_22);
	351	val = (mfdcr(ddrcfgd) & ~DDR0_22_DQS_OUT_SHIFT_MASK)
	352	\| DDR0_22_DQS_OUT_SHIFT_ENCODE(dqs_out_shift);
	353	mtdcr(ddrcfgd, val);
	354	debug("DDR0_22=0x%08lx\n", val);
	355
	356	/*
	357	* Set 'dll_dqs_delay_X'.
	358	*/
	359	/* dll_dqs_delay_0 */
	360	mtdcr(ddrcfga, DDR0_17);
	361	val = (mfdcr(ddrcfgd) & ~DDR0_17_DLL_DQS_DELAY_0_MASK)
	362	\| DDR0_17_DLL_DQS_DELAY_0_ENCODE(dll_dqs_delay_X);
	363	mtdcr(ddrcfgd, val);
	364	debug("DDR0_17=0x%08lx\n", val);
	365
	366	/* dll_dqs_delay_1 to dll_dqs_delay_4 */
	367	mtdcr(ddrcfga, DDR0_18);
	368	val = (mfdcr(ddrcfgd) & ~DDR0_18_DLL_DQS_DELAY_X_MASK)
	369	\| DDR0_18_DLL_DQS_DELAY_4_ENCODE(dll_dqs_delay_X)
	370	\| DDR0_18_DLL_DQS_DELAY_3_ENCODE(dll_dqs_delay_X)
	371	\| DDR0_18_DLL_DQS_DELAY_2_ENCODE(dll_dqs_delay_X)
	372	\| DDR0_18_DLL_DQS_DELAY_1_ENCODE(dll_dqs_delay_X);
	373	mtdcr(ddrcfgd, val);
	374	debug("DDR0_18=0x%08lx\n", val);
	375
	376	/* dll_dqs_delay_5 to dll_dqs_delay_8 */
	377	mtdcr(ddrcfga, DDR0_19);
	378	val = (mfdcr(ddrcfgd) & ~DDR0_19_DLL_DQS_DELAY_X_MASK)
	379	\| DDR0_19_DLL_DQS_DELAY_8_ENCODE(dll_dqs_delay_X)
	380	\| DDR0_19_DLL_DQS_DELAY_7_ENCODE(dll_dqs_delay_X)
	381	\| DDR0_19_DLL_DQS_DELAY_6_ENCODE(dll_dqs_delay_X)
	382	\| DDR0_19_DLL_DQS_DELAY_5_ENCODE(dll_dqs_delay_X);
	383	mtdcr(ddrcfgd, val);
	384	debug("DDR0_19=0x%08lx\n", val);
	385
	386	/*
	387	* Assert 'start' parameter.
	388	*/
	389	mtdcr(ddrcfga, DDR0_02);
	390	val = (mfdcr(ddrcfgd) & ~DDR0_02_START_MASK) \| DDR0_02_START_ON;
391	mtdcr(ddrcfgd, val);
392
393	ppcMsync();
394	ppcMbar();
395
396	/*
397	* Wait for the DCC master delay line to finish calibration
398	*/
399	if (wait_for_dlllock() != 0) {
400	printf("dlllock did not occur !!!\n");
401	hang();
402	}
403	ppcMsync();
404	ppcMbar();
405
406	if (wait_for_dram_init_complete() != 0) {
407	printf("dram init complete did not occur !!!\n");
408	hang();
409	}
410	udelay(100); /* wait 100us to ensure init is really completed !!! */
411	}
412	#endif /* CONFIG_DDR_DATA_EYE */
413
414	#ifdef CONFIG_DDR_ECC
415	static void wait_ddr_idle(void)
416	{
417	/*
418	* Controller idle status cannot be determined for Denali
419	* DDR2 code. Just return here.
420	*/
421	}
422
423	static void blank_string(int size)
424	{
425	int i;
426
427	for (i=0; i<size; i++)
428	putc('\b');
429	for (i=0; i<size; i++)
430	putc(' ');
431	for (i=0; i<size; i++)
432	putc('\b');
433	}
434
435	static void program_ecc(u32 start_address,
436	u32 num_bytes,
437	u32 tlb_word2_i_value)
438	{
439	u32 current_address;
440	u32 end_address;
441	u32 address_increment;
442	u32 val;
443	char str[] = "ECC generation -";
444	char slash[] = "\\\|/-\\\|/-";
445	int loop = 0;
446	int loopi = 0;
447
448	current_address = start_address;
449
450	sync();
451	eieio();
452	wait_ddr_idle();
453
454	if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) {
455	/* ECC bit set method for non-cached memory */
456	address_increment = 4;
457	end_address = current_address + num_bytes;
458
459	puts(str);
460
461	while (current_address < end_address) {
462	((u32 )current_address) = 0x00000000;
463	current_address += address_increment;
464
465	if ((loop++ % (2 << 20)) == 0) {
466	putc('\b');
467	putc(slash[loopi++ % 8]);
468	}
469	}
470
471	blank_string(strlen(str));
472	} else {
473	/* ECC bit set method for cached memory */
ea9f6bce	474	#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
04e6c38b SR	475	/*
	476	* Some boards (like lwmon5) need to preserve the memory
	477	* content upon ECC generation (for the log-buffer).
	478	* Therefore we don't fill the memory with a pattern or
	479	* just zero it, but write the same values back that are
	480	* already in the memory cells.
	481	*/
	482	address_increment = CFG_CACHELINE_SIZE;
	483	end_address = current_address + num_bytes;
	484
	485	current_address = start_address;
	486	while (current_address < end_address) {
ea9f6bce SR	487	/*
	488	* TODO: Th following sequence doesn't work correctly.
	489	* Just invalidating and flushing the cache doesn't
	490	* seem to trigger the re-write of the memory.
	491	*/
04e6c38b SR	492	ppcDcbi(current_address);
	493	ppcDcbf(current_address);
	494	current_address += CFG_CACHELINE_SIZE;
	495	}
	496	#else
b765ffb7 SR	497	dcbz_area(start_address, num_bytes);
b765ffb7 SR	498	dflush();
04e6c38b	499	#endif
b765ffb7 SR	500	}
	501
	502	sync();
	503	eieio();
	504	wait_ddr_idle();
	505
	506	/* Clear error status */
	507	mfsdram(DDR0_00, val);
	508	mtsdram(DDR0_00, val \| DDR0_00_INT_ACK_ALL);
	509
	510	/* Set 'int_mask' parameter to functionnal value */
	511	mfsdram(DDR0_01, val);
	512	mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) \| DDR0_01_INT_MASK_ALL_OFF));
	513
	514	sync();
	515	eieio();
	516	wait_ddr_idle();
	517	}
	518	#endif
	519
b765ffb7 SR	520	/*************************************************************************
	521	*
	522	* initdram -- 440EPx's DDR controller is a DENALI Core
	523	*
	524	************************************************************************/
	525	long int initdram (int board_type)
	526	{
04e6c38b SR	527	#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
04e6c38b SR	528	/* CL=3 */
b765ffb7 SR	529	mtsdram(DDR0_02, 0x00000000);
	530
	531	mtsdram(DDR0_00, 0x0000190A);
	532	mtsdram(DDR0_01, 0x01000000);
	533	mtsdram(DDR0_03, 0x02030603); /* A suitable burst length was taken. CAS is right for our board */
	534
	535	mtsdram(DDR0_04, 0x0A030300);
	536	mtsdram(DDR0_05, 0x02020308);
	537	mtsdram(DDR0_06, 0x0103C812);
	538	mtsdram(DDR0_07, 0x00090100);
	539	mtsdram(DDR0_08, 0x02c80001);
	540	mtsdram(DDR0_09, 0x00011D5F);
	541	mtsdram(DDR0_10, 0x00000300);
	542	mtsdram(DDR0_11, 0x000CC800);
	543	mtsdram(DDR0_12, 0x00000003);
	544	mtsdram(DDR0_14, 0x00000000);
	545	mtsdram(DDR0_17, 0x1e000000);
	546	mtsdram(DDR0_18, 0x1e1e1e1e);
	547	mtsdram(DDR0_19, 0x1e1e1e1e);
	548	mtsdram(DDR0_20, 0x0B0B0B0B);
	549	mtsdram(DDR0_21, 0x0B0B0B0B);
	550	#ifdef CONFIG_DDR_ECC
	551	mtsdram(DDR0_22, 0x00267F0B \| DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
	552	#else
	553	mtsdram(DDR0_22, 0x00267F0B);
	554	#endif
	555
	556	mtsdram(DDR0_23, 0x01000000);
	557	mtsdram(DDR0_24, 0x01010001);
	558
	559	mtsdram(DDR0_26, 0x2D93028A);
	560	mtsdram(DDR0_27, 0x0784682B);
	561
	562	mtsdram(DDR0_28, 0x00000080);
	563	mtsdram(DDR0_31, 0x00000000);
	564	mtsdram(DDR0_42, 0x01000006);
	565
	566	mtsdram(DDR0_43, 0x030A0200);
	567	mtsdram(DDR0_44, 0x00000003);
	568	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
04e6c38b SR	569	#else
	570	/* CL=4 */
	571	mtsdram(DDR0_02, 0x00000000);
	572
	573	mtsdram(DDR0_00, 0x0000190A);
	574	mtsdram(DDR0_01, 0x01000000);
	575	mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
	576
	577	mtsdram(DDR0_04, 0x0B030300);
	578	mtsdram(DDR0_05, 0x02020308);
	579	mtsdram(DDR0_06, 0x0003C812);
	580	mtsdram(DDR0_07, 0x00090100);
	581	mtsdram(DDR0_08, 0x03c80001);
	582	mtsdram(DDR0_09, 0x00011D5F);
	583	mtsdram(DDR0_10, 0x00000300);
	584	mtsdram(DDR0_11, 0x000CC800);
	585	mtsdram(DDR0_12, 0x00000003);
	586	mtsdram(DDR0_14, 0x00000000);
	587	mtsdram(DDR0_17, 0x1e000000);
	588	mtsdram(DDR0_18, 0x1e1e1e1e);
	589	mtsdram(DDR0_19, 0x1e1e1e1e);
	590	mtsdram(DDR0_20, 0x0B0B0B0B);
	591	mtsdram(DDR0_21, 0x0B0B0B0B);
	592	#ifdef CONFIG_DDR_ECC
	593	mtsdram(DDR0_22, 0x00267F0B \| DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
	594	#else
	595	mtsdram(DDR0_22, 0x00267F0B);
	596	#endif
	597
	598	mtsdram(DDR0_23, 0x01000000);
	599	mtsdram(DDR0_24, 0x01010001);
	600
	601	mtsdram(DDR0_26, 0x2D93028A);
	602	mtsdram(DDR0_27, 0x0784682B);
	603
	604	mtsdram(DDR0_28, 0x00000080);
	605	mtsdram(DDR0_31, 0x00000000);
	606	mtsdram(DDR0_42, 0x01000008);
	607
	608	mtsdram(DDR0_43, 0x050A0200);
	609	mtsdram(DDR0_44, 0x00000005);
	610	mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
	611	#endif
b765ffb7 SR	612
	613	wait_for_dlllock();
	614
83b4cfa3	615	/*
b765ffb7 SR	616	* Program tlb entries for this size (dynamic)
b765ffb7 SR	617	*/
83b4cfa3	618	program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
b765ffb7 SR	619
	620	/*
	621	* Setup 2nd TLB with same physical address but different virtual address
	622	* with cache enabled. This is done for fast ECC generation.
	623	*/
83b4cfa3	624	program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
b765ffb7 SR	625
	626	#ifdef CONFIG_DDR_DATA_EYE
	627	/*
	628	* Perform data eye search if requested.
	629	*/
	630	denali_core_search_data_eye(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20);
b765ffb7 SR	631	#endif
	632
	633	#ifdef CONFIG_DDR_ECC
	634	/*
	635	* If ECC is enabled, initialize the parity bits.
	636	*/
	637	program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
	638	#endif
	639
ea9f6bce SR	640	/*
	641	* Clear possible errors resulting from data-eye-search.
	642	* If not done, then we could get an interrupt later on when
	643	* exceptions are enabled.
	644	*/
	645	set_mcsr(get_mcsr());
	646
b765ffb7 SR	647	return (CFG_MBYTES_SDRAM << 20);
b765ffb7 SR	648	}