[people/ms/u-boot.git] / board / matrix_vision / mvblm7 / fpga.c

/*
 * (C) Copyright 2002
 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
 * Keith Outwater, keith_outwater@mvis.com.
 *
 * (C) Copyright 2008
 * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <common.h>
#include <ACEX1K.h>
#include <command.h>
#include "fpga.h"
#include "mvblm7.h"

#ifdef FPGA_DEBUG
#define fpga_debug(fmt, args...)      printf("%s: "fmt, __func__, ##args)
#else
#define fpga_debug(fmt, args...)
#endif

Altera_CYC2_Passive_Serial_fns altera_fns = {
	fpga_null_fn,
	fpga_config_fn,
	fpga_status_fn,
	fpga_done_fn,
	fpga_wr_fn,
	fpga_null_fn,
	fpga_null_fn,
	0
};

Altera_desc cyclone2 = {
	Altera_CYC2,
	passive_serial,
	Altera_EP2C20_SIZE,
	(void *) &altera_fns,
	NULL,
	0
};

DECLARE_GLOBAL_DATA_PTR;

int mvblm7_init_fpga(void)
{
	fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n",
		gd->reloc_off);
	fpga_init(gd->reloc_off);
	fpga_add(fpga_altera, &cyclone2);
	fpga_config_fn(0, 1, 0);
	udelay(60);

	return 1;
}

int fpga_null_fn(int cookie)
{
	return 0;
}

int fpga_config_fn(int assert, int flush, int cookie)
{
	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
	u32 dvo = gpio->dat;

	fpga_debug("SET config : %s\n", assert ? "low" : "high");
	if (assert)
		dvo |= FPGA_CONFIG;
	else
		dvo &= ~FPGA_CONFIG;

	if (flush)
		gpio->dat = dvo;

	return assert;
}

int fpga_done_fn(int cookie)
{
	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
	int result = 0;

	udelay(10);
	fpga_debug("CONF_DONE check ... ");
	if (gpio->dat & FPGA_CONF_DONE)  {
		fpga_debug("high\n");
		result = 1;
	} else
		fpga_debug("low\n");

	return result;
}

int fpga_status_fn(int cookie)
{
	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
	int result = 0;

	fpga_debug("STATUS check ... ");
	if (gpio->dat & FPGA_STATUS)  {
		fpga_debug("high\n");
		result = 1;
	} else
		fpga_debug("low\n");

	return result;
}

int fpga_clk_fn(int assert_clk, int flush, int cookie)
{
	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
	u32 dvo = gpio->dat;

	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
	if (assert_clk)
		dvo |= FPGA_CCLK;
	else
		dvo &= ~FPGA_CCLK;

	if (flush)
		gpio->dat = dvo;

	return assert_clk;
}

static inline int _write_fpga(u8 val, int dump)
{
	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
	int i;
	u32 dvo = gpio->dat;

	if (dump)
		fpga_debug("  %02x -> ", val);
	for (i = 0; i < 8; i++) {
		dvo &= ~FPGA_CCLK;
		gpio->dat = dvo;
		dvo &= ~FPGA_DIN;
		if (dump)
			fpga_debug("%d ", val&1);
		if (val & 1)
			dvo |= FPGA_DIN;
		gpio->dat = dvo;
		dvo |= FPGA_CCLK;
		gpio->dat = dvo;
		val >>= 1;
	}
	if (dump)
		fpga_debug("\n");

	return 0;
}

int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
{
	unsigned char *data = (unsigned char *) buf;
	int i;

	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
	for (i = 0; i < len; i++)
		_write_fpga(data[i], 0);
	fpga_debug("\n");

	return FPGA_SUCCESS;
}
Commit	Line	Data
a1293e54 AS	1	/*
	2	* (C) Copyright 2002
	3	* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
	4	* Keith Outwater, keith_outwater@mvis.com.
	5	*
	6	* (C) Copyright 2008
	7	* Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*
	27	*/
	28
	29	#include <common.h>
	30	#include <ACEX1K.h>
	31	#include <command.h>
	32	#include "fpga.h"
	33	#include "mvblm7.h"
	34
	35	#ifdef FPGA_DEBUG
	36	#define fpga_debug(fmt, args...) printf("%s: "fmt, __func__, ##args)
	37	#else
	38	#define fpga_debug(fmt, args...)
	39	#endif
	40
	41	Altera_CYC2_Passive_Serial_fns altera_fns = {
	42	fpga_null_fn,
	43	fpga_config_fn,
	44	fpga_status_fn,
	45	fpga_done_fn,
	46	fpga_wr_fn,
	47	fpga_null_fn,
	48	fpga_null_fn,
	49	0
	50	};
	51
	52	Altera_desc cyclone2 = {
	53	Altera_CYC2,
	54	passive_serial,
	55	Altera_EP2C20_SIZE,
	56	(void *) &altera_fns,
	57	NULL,
	58	0
	59	};
	60
	61	DECLARE_GLOBAL_DATA_PTR;
	62
	63	int mvblm7_init_fpga(void)
	64	{
65	fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n",
66	gd->reloc_off);
67	fpga_init(gd->reloc_off);
68	fpga_add(fpga_altera, &cyclone2);
69	fpga_config_fn(0, 1, 0);
70	udelay(60);
71
72	return 1;
73	}
74
75	int fpga_null_fn(int cookie)
76	{
77	return 0;
78	}
79
80	int fpga_config_fn(int assert, int flush, int cookie)
81	{
6d0f6bcf	82	volatile immap_t im = (volatile immap_t )CONFIG_SYS_IMMR;
a1293e54 AS	83	volatile gpio83xx_t gpio = (volatile gpio83xx_t )&im->gpio[0];
	84	u32 dvo = gpio->dat;
	85
	86	fpga_debug("SET config : %s\n", assert ? "low" : "high");
	87	if (assert)
	88	dvo \|= FPGA_CONFIG;
	89	else
	90	dvo &= ~FPGA_CONFIG;
	91
	92	if (flush)
	93	gpio->dat = dvo;
	94
	95	return assert;
	96	}
	97
	98	int fpga_done_fn(int cookie)
	99	{
6d0f6bcf	100	volatile immap_t im = (volatile immap_t )CONFIG_SYS_IMMR;
a1293e54 AS	101	volatile gpio83xx_t gpio = (volatile gpio83xx_t )&im->gpio[0];
	102	int result = 0;
	103
	104	udelay(10);
	105	fpga_debug("CONF_DONE check ... ");
	106	if (gpio->dat & FPGA_CONF_DONE) {
	107	fpga_debug("high\n");
	108	result = 1;
	109	} else
	110	fpga_debug("low\n");
	111
	112	return result;
	113	}
	114
	115	int fpga_status_fn(int cookie)
	116	{
6d0f6bcf	117	volatile immap_t im = (volatile immap_t )CONFIG_SYS_IMMR;
a1293e54 AS	118	volatile gpio83xx_t gpio = (volatile gpio83xx_t )&im->gpio[0];
	119	int result = 0;
	120
	121	fpga_debug("STATUS check ... ");
	122	if (gpio->dat & FPGA_STATUS) {
	123	fpga_debug("high\n");
	124	result = 1;
	125	} else
	126	fpga_debug("low\n");
	127
	128	return result;
	129	}
	130
	131	int fpga_clk_fn(int assert_clk, int flush, int cookie)
	132	{
6d0f6bcf	133	volatile immap_t im = (volatile immap_t )CONFIG_SYS_IMMR;
a1293e54 AS	134	volatile gpio83xx_t gpio = (volatile gpio83xx_t )&im->gpio[0];
	135	u32 dvo = gpio->dat;
	136
	137	fpga_debug("CLOCK %s\n", assert_clk ? "high" : "low");
	138	if (assert_clk)
	139	dvo \|= FPGA_CCLK;
	140	else
	141	dvo &= ~FPGA_CCLK;
	142
	143	if (flush)
	144	gpio->dat = dvo;
	145
	146	return assert_clk;
	147	}
	148
	149	static inline int _write_fpga(u8 val, int dump)
	150	{
6d0f6bcf	151	volatile immap_t im = (volatile immap_t )CONFIG_SYS_IMMR;
a1293e54 AS	152	volatile gpio83xx_t gpio = (volatile gpio83xx_t )&im->gpio[0];
	153	int i;
	154	u32 dvo = gpio->dat;
	155
	156	if (dump)
	157	fpga_debug(" %02x -> ", val);
	158	for (i = 0; i < 8; i++) {
	159	dvo &= ~FPGA_CCLK;
	160	gpio->dat = dvo;
	161	dvo &= ~FPGA_DIN;
	162	if (dump)
	163	fpga_debug("%d ", val&1);
	164	if (val & 1)
	165	dvo \|= FPGA_DIN;
	166	gpio->dat = dvo;
	167	dvo \|= FPGA_CCLK;
	168	gpio->dat = dvo;
	169	val >>= 1;
	170	}
	171	if (dump)
	172	fpga_debug("\n");
	173
	174	return 0;
	175	}
	176
	177	int fpga_wr_fn(void *buf, size_t len, int flush, int cookie)
	178	{
	179	unsigned char data = (unsigned char ) buf;
	180	int i;
	181
	182	fpga_debug("fpga_wr: buf %p / size %d\n", buf, len);
	183	for (i = 0; i < len; i++)
	184	_write_fpga(data[i], 0);
	185	fpga_debug("\n");
	186
	187	return FPGA_SUCCESS;
	188	}