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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
a4884831 SR |
2 | /* |
3 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> | |
a4884831 SR |
4 | */ |
5 | ||
d678a59d | 6 | #include <common.h> |
691d719d | 7 | #include <init.h> |
a4884831 | 8 | #include <miiphy.h> |
401d1c4f | 9 | #include <asm/global_data.h> |
a4884831 SR |
10 | #include <asm/io.h> |
11 | #include <asm/arch/cpu.h> | |
12 | #include <asm/arch/soc.h> | |
13 | #include <linux/mbus.h> | |
14 | ||
29b103c7 SR |
15 | #include "../drivers/ddr/marvell/axp/ddr3_hw_training.h" |
16 | #include "../arch/arm/mach-mvebu/serdes/axp/high_speed_env_spec.h" | |
e7778ec1 | 17 | |
a4884831 SR |
18 | DECLARE_GLOBAL_DATA_PTR; |
19 | ||
20 | /* Base addresses for the external device chip selects */ | |
21 | #define DEV_CS0_BASE 0xe0000000 | |
22 | #define DEV_CS1_BASE 0xe1000000 | |
23 | #define DEV_CS2_BASE 0xe2000000 | |
24 | #define DEV_CS3_BASE 0xe3000000 | |
25 | ||
e7778ec1 SR |
26 | /* DDR3 static configuration */ |
27 | MV_DRAM_MC_INIT ddr3_b0_maxbcm[MV_MAX_DDR3_STATIC_SIZE] = { | |
28 | {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */ | |
29 | {0x00001404, 0x30000820}, /* Dunit Control Low Register */ | |
30 | {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */ | |
31 | {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */ | |
32 | {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */ | |
33 | {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */ | |
34 | {0x00001418, 0x00000e00}, /* DDR SDRAM Operation Register */ | |
35 | {0x0000141C, 0x00000672}, /* DDR SDRAM Mode Register */ | |
36 | {0x00001420, 0x00000004}, /* DDR SDRAM Extended Mode Register */ | |
37 | {0x00001424, 0x0000F3FF}, /* Dunit Control High Register */ | |
38 | {0x00001428, 0x0011A940}, /* Dunit Control High Register */ | |
39 | {0x0000142C, 0x014C5134}, /* Dunit Control High Register */ | |
40 | {0x0000147C, 0x0000D771}, | |
41 | ||
42 | {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */ | |
43 | {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */ | |
44 | {0x000014A0, 0x00000001}, | |
45 | {0x000014A8, 0x00000101}, | |
46 | ||
47 | /* Recommended Settings from Marvell for 4 x 16 bit devices: */ | |
48 | {0x000014C0, 0x192424C9}, /* DRAM addr and Ctrl Driving Strenght*/ | |
49 | {0x000014C4, 0xAAA24C9}, /* DRAM Data and DQS Driving Strenght */ | |
50 | ||
51 | /* | |
52 | * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the | |
53 | * training sequence | |
54 | */ | |
55 | {0x000200e8, 0x3FFF0E01}, | |
56 | {0x00020184, 0x3FFFFFE0}, /* Close fast path Window to - 2G */ | |
57 | ||
58 | {0x0001504, 0x3FFFFFE1}, /* CS0 Size */ | |
59 | {0x000150C, 0x00000000}, /* CS1 Size */ | |
60 | {0x0001514, 0x00000000}, /* CS2 Size */ | |
61 | {0x000151C, 0x00000000}, /* CS3 Size */ | |
62 | ||
63 | {0x0020220, 0x00000007}, /* Reserved */ | |
64 | ||
65 | {0x00001538, 0x0000000B}, /* Read Data Sample Delays Register */ | |
66 | {0x0000153C, 0x0000000B}, /* Read Data Ready Delay Register */ | |
67 | ||
68 | {0x000015D0, 0x00000670}, /* MR0 */ | |
69 | {0x000015D4, 0x00000044}, /* MR1 */ | |
70 | {0x000015D8, 0x00000018}, /* MR2 */ | |
71 | {0x000015DC, 0x00000000}, /* MR3 */ | |
72 | {0x000015E0, 0x00000001}, | |
73 | {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */ | |
74 | {0x000015EC, 0xF800A225}, /* DDR PHY */ | |
75 | ||
76 | {0x0, 0x0} | |
77 | }; | |
78 | ||
79 | MV_DRAM_MODES maxbcm_ddr_modes[MV_DDR3_MODES_NUMBER] = { | |
80 | {"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm, NULL}, | |
81 | }; | |
82 | ||
83 | extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; | |
84 | ||
85 | /* MAXBCM: SERDES 0-4 PCIE, Serdes 7 = SGMII 0, all others = unconnected */ | |
86 | MV_BIN_SERDES_CFG maxbcm_serdes_cfg[] = { | |
87 | { MV_PEX_ROOT_COMPLEX, 0x20011111, 0x00000000, | |
88 | { PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, | |
89 | PEX_BUS_DISABLED }, | |
90 | 0x1f, serdes_change_m_phy | |
91 | } | |
92 | }; | |
93 | ||
94 | MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) | |
95 | { | |
96 | /* Only one mode supported for this board */ | |
97 | return &maxbcm_ddr_modes[0]; | |
98 | } | |
99 | ||
0a590243 | 100 | MV_BIN_SERDES_CFG *board_serdes_cfg_get(void) |
e7778ec1 SR |
101 | { |
102 | return &maxbcm_serdes_cfg[0]; | |
103 | } | |
a4884831 SR |
104 | |
105 | int board_early_init_f(void) | |
106 | { | |
107 | /* | |
108 | * Don't configure MPP (pin multiplexing) and GPIO here, | |
109 | * its already done in bin_hdr | |
110 | */ | |
111 | ||
112 | /* | |
113 | * Setup some board specific mbus address windows | |
114 | */ | |
5692e5b2 | 115 | mbus_dt_setup_win(DEV_CS0_BASE, 16 << 20, |
a4884831 | 116 | CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS0); |
5692e5b2 | 117 | mbus_dt_setup_win(DEV_CS1_BASE, 16 << 20, |
a4884831 | 118 | CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS1); |
5692e5b2 | 119 | mbus_dt_setup_win(DEV_CS2_BASE, 16 << 20, |
a4884831 | 120 | CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS2); |
5692e5b2 | 121 | mbus_dt_setup_win(DEV_CS3_BASE, 16 << 20, |
a4884831 SR |
122 | CPU_TARGET_DEVICEBUS_BOOTROM_SPI, CPU_ATTR_DEV_CS3); |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
127 | int board_init(void) | |
128 | { | |
129 | /* adress of boot parameters */ | |
130 | gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
135 | int checkboard(void) | |
136 | { | |
137 | puts("Board: maxBCM\n"); | |
138 | ||
139 | return 0; | |
140 | } | |
141 | ||
a4884831 | 142 | /* Configure and enable MV88E6185 switch */ |
e3b9c98a | 143 | int board_phy_config(struct phy_device *phydev) |
a4884831 | 144 | { |
e3b9c98a SR |
145 | /* |
146 | * todo: | |
147 | * Fill this with the real setup / config code. | |
148 | * Please see board/Marvell/db-mv784mp-gp/db-mv784mp-gp.c | |
149 | * for details. | |
150 | */ | |
151 | printf("88E6185 Initialized\n"); | |
152 | return 0; | |
a4884831 | 153 | } |