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1 | #ifndef __csr_h |
2 | #define __csr_h | |
3 | ||
4 | /* | |
5 | * (C) Copyright 2000 | |
6 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
7 | * Marius Groeger <mgroeger@sysgo.de> | |
8 | * | |
9 | * Control and Status Register definitions for the MBX | |
10 | * | |
11 | *-------------------------------------------------------------------- | |
12 | * See file CREDITS for list of people who contributed to this | |
13 | * project. | |
14 | * | |
15 | * This program is free software; you can redistribute it and/or | |
16 | * modify it under the terms of the GNU General Public License as | |
17 | * published by the Free Software Foundation; either version 2 of | |
18 | * the License, or (at your option) any later version. | |
19 | * | |
20 | * This program is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU General Public License for more details. | |
24 | * | |
25 | * You should have received a copy of the GNU General Public License | |
26 | * along with this program; if not, write to the Free Software | |
27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
28 | * MA 02111-1307 USA | |
29 | */ | |
30 | ||
31 | /* bits for control register #1 / status register #1 */ | |
32 | #define CSR1_ETEN 0x80 /* Ethernet Transceiver Enabled */ | |
33 | #define CSR1_ELEN 0x40 /* Ethernet XCVR in Internal Loopback */ | |
34 | #define CSR1_EAEN 0x20 /* Auto selection TP/AUI Enabled */ | |
35 | #define CSR1_TPEN 0x10 /* TP manually selected */ | |
36 | #define CSR1_FDDIS 0x08 /* Full Duplex Mode disabled */ | |
37 | #define CSR1_FCTEN 0x04 /* Collision Testing of XCVR disabled */ | |
38 | #define CSR1_COM1EN 0x02 /* COM1 signals routed to RS232 Transceiver */ | |
39 | #define CSR1_XCVRDIS 0x01 /* Onboard RS232 Transceiver Disabled */ | |
40 | ||
41 | /* bits for control register #2 */ | |
42 | #define CR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ | |
43 | #define CR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ | |
44 | #define CR2_BRDFAIL 0x08 /* Board fail */ | |
45 | #define CR2_SWS1 0x04 /* Software Status #2 LED */ | |
46 | #define CR2_SWS2 0x02 /* Software Status #2 LED */ | |
47 | #define CR2_QSPANRST 0x01 /* Reset QSPAN */ | |
48 | ||
49 | /* bits for status register #2 */ | |
50 | #define SR2_VDDSEL 0xC0 /* PCMCIA Supply Voltage */ | |
51 | #define SR2_VPPSEL 0x30 /* PCMCIA Programming Voltage */ | |
52 | #define SR2_BATGD 0x08 /* Low Voltage indication for onboard bat */ | |
53 | #define SR2_NVBATGD 0x04 /* Low Voltage indication for NVRAM */ | |
54 | #define SR2_RDY 0x02 /* Flash programming status bit */ | |
55 | #define SR2_FT 0x01 /* Reserved for Factory test purposes */ | |
56 | ||
6d0f6bcf JCPV |
57 | #define MBX_CSR1 (*((uchar *)CONFIG_SYS_CSR_BASE)) |
58 | #define MBX_CSR2 (*((uchar *)CONFIG_SYS_CSR_BASE + 1)) | |
4a5b6a35 WD |
59 | |
60 | #endif /* __csr_h */ |