[thirdparty/u-boot.git] / board / menlo / m53menlo / m53menlo.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Menlosystems M53Menlo board
 *
 * Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
 * Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
 */

#include <common.h>
#include <dm.h>
#include <init.h>
#include <malloc.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/mx5_video.h>
#include <asm/mach-imx/video.h>
#include <asm/gpio.h>
#include <asm/spl.h>
#include <env.h>
#include <fdt_support.h>
#include <fsl_esdhc_imx.h>
#include <gzip.h>
#include <i2c.h>
#include <ipu_pixfmt.h>
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/fb.h>
#include <mmc.h>
#include <netdev.h>
#include <spl.h>
#include <splash.h>
#include <usb/ehci-ci.h>
#include <video_console.h>

DECLARE_GLOBAL_DATA_PTR;

static u32 mx53_dram_size[2];

phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
{
	/*
	 * WARNING: We must override get_effective_memsize() function here
	 * to report only the size of the first DRAM bank. This is to make
	 * U-Boot relocator place U-Boot into valid memory, that is, at the
	 * end of the first DRAM bank. If we did not override this function
	 * like so, U-Boot would be placed at the address of the first DRAM
	 * bank + total DRAM size - sizeof(uboot), which in the setup where
	 * each DRAM bank contains 512MiB of DRAM would result in placing
	 * U-Boot into invalid memory area close to the end of the first
	 * DRAM bank.
	 */
	return PHYS_SDRAM_2 + mx53_dram_size[1];
}

int dram_init(void)
{
	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);

	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];

	return 0;
}

int dram_init_banksize(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size = mx53_dram_size[0];

	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	gd->bd->bi_dram[1].size = mx53_dram_size[1];

	return 0;
}

static void setup_iomux_uart(void)
{
	static const iomux_v3_cfg_t uart_pads[] = {
		MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
		MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
	};

	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
}

static void setup_iomux_fec(void)
{
	static const iomux_v3_cfg_t fec_pads[] = {
		/* MDIO pads */
		NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS |
			PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP | PAD_CTL_ODE),
		NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),

		/* FEC 0 pads */
		NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),

		/* FEC 1 pads */
		NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
			     PAD_CTL_HYS | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
	};

	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}

#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg esdhc_cfg = {
	MMC_SDHC1_BASE_ADDR,
};

int board_mmc_getcd(struct mmc *mmc)
{
	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
	gpio_direction_input(IMX_GPIO_NR(1, 1));

	return !gpio_get_value(IMX_GPIO_NR(1, 1));
}

#define SD_CMD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
				 PAD_CTL_PUS_100K_UP)
#define SD_PAD_CTRL		(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
				 PAD_CTL_DSE_HIGH)

int board_mmc_init(struct bd_info *bis)
{
	static const iomux_v3_cfg_t sd1_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
		NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
	};

	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));

	return fsl_esdhc_initialize(bis, &esdhc_cfg);
}
#endif

static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
{
	static struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
	int ret;

	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);

	/*
	 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
	 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	 */
	ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
	if (ret)
		puts("IPU:   Failed to configure LDB clock\n");

	/* Configure CCM_CSCMR2 */
	clrsetbits_le32(&mxc_ccm->cscmr2,
			(0x7 << 26) | BIT(10) | BIT(8),
			(0x5 << 26) | BIT(10) | BIT(8));

	/* Configure LDB_CTRL */
	writel(0x201, 0x53fa8008);
}

static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
{
	gpio_request(IMX_GPIO_NR(6, 0), "LCD");

	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);

	/*
	 * Set LVDS clock to 9 MHz for the display. The PLL4 is set to
	 * 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	 */
	enable_lvds_clock(dev, 63);
}

static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
{
	gpio_request(IMX_GPIO_NR(6, 0), "LCD");

	/*
	 * Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
	 * 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	 */
	enable_lvds_clock(dev, 233);

	/* For ETM0700G0DH6 model, this may be enabled after the clock. */
	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
}

static const char *lvds_compat_string;

static int detect_lvds(struct display_info_t const *dev)
{
	struct udevice *idev, *ibus;
	u8 touchid[23];
	u8 *touchptr = &touchid[0];
	int ret;

	ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &ibus);
	if (ret)
		return 0;

	ret = dm_i2c_probe(ibus, 0x38, 0, &idev);
	if (ret)
		return 0;

	/* Touchscreen is at address 0x38, ID register is 0xbb. */
	ret = dm_i2c_read(idev, 0xbb, touchid, sizeof(touchid));
	if (ret)
		return 0;

	/* EP0430 prefixes the response with 0xbb, skip it. */
	if (*touchptr == 0xbb)
		touchptr++;

	/* Skip the 'EP' prefix. */
	touchptr += 2;

	ret = !memcmp(touchptr, &dev->mode.name[7], 4);
	if (ret)
		lvds_compat_string = dev->mode.name;

	return ret;
}

void board_preboot_os(void)
{
	/* Power off the LCD to prevent awful color flicker */
	gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
}

#if CONFIG_IS_ENABLED(OF_LIBFDT)
int ft_board_setup(void *blob, struct bd_info *bd)
{
	if (lvds_compat_string)
		do_fixup_by_path_string(blob, "/panel", "compatible",
					lvds_compat_string);

	return 0;
}
#endif

struct display_info_t const displays[] = {
	{
		.bus	= 0,
		.addr	= 0,
		.detect	= detect_lvds,
		.enable	= enable_lvds_etm0430g0dh6,
		.pixfmt	= IPU_PIX_FMT_RGB666,
		.mode	= {
			.name		= "edt,etm0430g0dh6",
			.refresh	= 60,
			.xres		= 480,
			.yres		= 272,
			.pixclock	= 111111, /* picosecond (9 MHz) */
			.left_margin	= 2,
			.right_margin	= 2,
			.upper_margin	= 2,
			.lower_margin	= 2,
			.hsync_len	= 41,
			.vsync_len	= 10,
			.sync		= 0x40000000,
			.vmode          = FB_VMODE_NONINTERLACED
		}
	}, {
		.bus	= 0,
		.addr	= 0,
		.detect	= detect_lvds,
		.enable	= enable_lvds_etm0700g0dh6,
		.pixfmt	= IPU_PIX_FMT_RGB666,
		.mode	= {
			.name		= "edt,etm0700g0dh6",
			.refresh	= 60,
			.xres		= 800,
			.yres		= 480,
			.pixclock	= 30048, /* picosecond (33.28 MHz) */
			.left_margin	= 40,
			.right_margin	= 88,
			.upper_margin	= 10,
			.lower_margin	= 33,
			.hsync_len	= 128,
			.vsync_len	= 2,
			.sync		= FB_SYNC_EXT,
			.vmode          = FB_VMODE_NONINTERLACED
		}
	}
};

size_t display_count = ARRAY_SIZE(displays);

#ifdef CONFIG_SPLASH_SCREEN
static struct splash_location default_splash_locations[] = {
	{
		.name		= "mmc_fs",
		.storage	= SPLASH_STORAGE_MMC,
		.flags		= SPLASH_STORAGE_FS,
		.devpart	= "0:1",
	},
};

int splash_screen_prepare(void)
{
	return splash_source_load(default_splash_locations,
				  ARRAY_SIZE(default_splash_locations));
}
#endif

int board_late_init(void)
{
#ifdef CONFIG_CMD_BMODE
	add_board_boot_modes(NULL);
#endif

#if defined(CONFIG_VIDEO_IPUV3)
	struct udevice *dev;
	int xpos, ypos, ret;
	char *s;
	void *dst;
	ulong addr, len;

	splash_get_pos(&xpos, &ypos);

	s = env_get("splashimage");
	if (!s)
		return 0;

	addr = hextoul(s, NULL);
	dst = malloc(CONFIG_VIDEO_LOGO_MAX_SIZE);
	if (!dst)
		return -ENOMEM;

	ret = splash_screen_prepare();
	if (ret < 0)
		goto splasherr;

	len = CONFIG_VIDEO_LOGO_MAX_SIZE;
	ret = gunzip(dst + 2, CONFIG_VIDEO_LOGO_MAX_SIZE - 2,
		     (uchar *)addr, &len);
	if (ret) {
		printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
		goto splasherr;
	}

	ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
	if (ret)
		goto splasherr;

	ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
	if (ret)
		goto splasherr;

	return 0;

splasherr:
	free(dst);
#endif
	return 0;
}

static void setup_iomux_video(void)
{
	static const iomux_v3_cfg_t lcd_pads[] = {
		MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
		MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
		MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
		MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
		MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
	};

	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
}

static void setup_iomux_nand(void)
{
	static const iomux_v3_cfg_t nand_pads[] = {
		NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
			     PAD_CTL_PUS_100K_UP),
		NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
			     PAD_CTL_PUS_100K_UP),
		NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
			     PAD_CTL_DSE_HIGH),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
		NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
			     PAD_CTL_DSE_HIGH | PAD_CTL_PKE),
	};

	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
}

static void m53_set_clock(void)
{
	int ret;
	const u32 ref_clk = MXC_HCLK;
	const u32 dramclk = 400;
	u32 cpuclk;

	gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");

	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
					    PAD_CTL_DSE_HIGH | PAD_CTL_PKE));
	gpio_direction_input(IMX_GPIO_NR(4, 0));

	/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
	cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;

	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
	if (ret)
		printf("CPU:   Switch CPU clock to %dMHz failed\n", cpuclk);

	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
	if (ret) {
		printf("CPU:   Switch peripheral clock to %dMHz failed\n",
		       dramclk);
	}

	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
	if (ret)
		printf("CPU:   Switch DDR clock to %dMHz failed\n", dramclk);
}

static void m53_set_nand(void)
{
	u32 i;

	/* NAND flash is muxed on ATA pins */
	setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);

	/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
	for (i = 0x4; i < 0x94; i += 0x18) {
		clrbits_le32(WEIM_BASE_ADDR + i,
			     WEIM_GCR2_MUX16_BYP_GRANT_MASK);
	}

	mxc_set_clock(0, 33, MXC_NFC_CLK);
	enable_nfc_clk(1);
}

int board_early_init_f(void)
{
	setup_iomux_uart();
	setup_iomux_fec();
	setup_iomux_nand();
	setup_iomux_video();

	m53_set_clock();

	mxc_set_sata_internal_clock();

	/* NAND clock @ 33MHz */
	m53_set_nand();

	return 0;
}

int board_init(void)
{
	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;

	return 0;
}

int checkboard(void)
{
	puts("Board: Menlosystems M53Menlo\n");

	return 0;
}

/*
 * NAND SPL
 */
#ifdef CONFIG_SPL_BUILD
void spl_board_init(void)
{
	setup_iomux_nand();
	m53_set_clock();
	m53_set_nand();
}

u32 spl_boot_device(void)
{
	return BOOT_DEVICE_NAND;
}
#endif
Commit	Line	Data
39cb4f3c MV	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Menlosystems M53Menlo board
	4	*
	5	* Copyright (C) 2012-2017 Marek Vasut <marex@denx.de>
	6	* Copyright (C) 2014-2017 Olaf Mandel <o.mandel@menlosystems.com>
	7	*/
	8
d678a59d	9	#include <common.h>
f0be8ff4	10	#include <dm.h>
67c4e9f8	11	#include <init.h>
336d4615	12	#include <malloc.h>
401d1c4f	13	#include <asm/global_data.h>
39cb4f3c MV	14	#include <asm/io.h>
	15	#include <asm/arch/imx-regs.h>
	16	#include <asm/arch/sys_proto.h>
	17	#include <asm/arch/crm_regs.h>
	18	#include <asm/arch/clock.h>
	19	#include <asm/arch/iomux-mx53.h>
92f67189	20	#include <asm/mach-imx/boot_mode.h>
39cb4f3c MV	21	#include <asm/mach-imx/mx5_video.h>
	22	#include <asm/mach-imx/video.h>
	23	#include <asm/gpio.h>
	24	#include <asm/spl.h>
7b51b576	25	#include <env.h>
39cb4f3c	26	#include <fdt_support.h>
e37ac717	27	#include <fsl_esdhc_imx.h>
0c670fc1	28	#include <gzip.h>
39cb4f3c MV	29	#include <i2c.h>
39cb4f3c MV	30	#include <ipu_pixfmt.h>
cd93d625	31	#include <linux/bitops.h>
39cb4f3c MV	32	#include <linux/errno.h>
	33	#include <linux/fb.h>
	34	#include <mmc.h>
	35	#include <netdev.h>
	36	#include <spl.h>
	37	#include <splash.h>
	38	#include <usb/ehci-ci.h>
f0be8ff4	39	#include <video_console.h>
39cb4f3c MV	40
	41	DECLARE_GLOBAL_DATA_PTR;
	42
	43	static u32 mx53_dram_size[2];
	44
d768dd88	45	phys_addr_t board_get_usable_ram_top(phys_size_t total_size)
39cb4f3c MV	46	{
	47	/*
	48	* WARNING: We must override get_effective_memsize() function here
	49	* to report only the size of the first DRAM bank. This is to make
	50	* U-Boot relocator place U-Boot into valid memory, that is, at the
	51	* end of the first DRAM bank. If we did not override this function
	52	* like so, U-Boot would be placed at the address of the first DRAM
	53	* bank + total DRAM size - sizeof(uboot), which in the setup where
	54	* each DRAM bank contains 512MiB of DRAM would result in placing
	55	* U-Boot into invalid memory area close to the end of the first
	56	* DRAM bank.
	57	*/
	58	return PHYS_SDRAM_2 + mx53_dram_size[1];
	59	}
	60
	61	int dram_init(void)
	62	{
	63	mx53_dram_size[0] = get_ram_size((void *)PHYS_SDRAM_1, 1 << 30);
	64	mx53_dram_size[1] = get_ram_size((void *)PHYS_SDRAM_2, 1 << 30);
	65
	66	gd->ram_size = mx53_dram_size[0] + mx53_dram_size[1];
	67
	68	return 0;
	69	}
	70
	71	int dram_init_banksize(void)
	72	{
	73	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	74	gd->bd->bi_dram[0].size = mx53_dram_size[0];
	75
	76	gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
	77	gd->bd->bi_dram[1].size = mx53_dram_size[1];
	78
	79	return 0;
	80	}
	81
	82	static void setup_iomux_uart(void)
	83	{
	84	static const iomux_v3_cfg_t uart_pads[] = {
	85	MX53_PAD_PATA_DMACK__UART1_RXD_MUX,
	86	MX53_PAD_PATA_DIOW__UART1_TXD_MUX,
	87	};
	88
	89	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
	90	}
	91
39cb4f3c MV	92	static void setup_iomux_fec(void)
	93	{
	94	static const iomux_v3_cfg_t fec_pads[] = {
	95	/* MDIO pads */
	96	NEW_PAD_CTRL(MX53_PAD_FEC_MDIO__FEC_MDIO, PAD_CTL_HYS \|
	97	PAD_CTL_DSE_HIGH \| PAD_CTL_PUS_22K_UP \| PAD_CTL_ODE),
	98	NEW_PAD_CTRL(MX53_PAD_FEC_MDC__FEC_MDC, PAD_CTL_DSE_HIGH),
	99
	100	/* FEC 0 pads */
	101	NEW_PAD_CTRL(MX53_PAD_FEC_CRS_DV__FEC_RX_DV,
	102	PAD_CTL_HYS \| PAD_CTL_PKE),
	103	NEW_PAD_CTRL(MX53_PAD_FEC_REF_CLK__FEC_TX_CLK,
	104	PAD_CTL_HYS \| PAD_CTL_PKE),
	105	NEW_PAD_CTRL(MX53_PAD_FEC_RX_ER__FEC_RX_ER,
	106	PAD_CTL_HYS \| PAD_CTL_PKE),
	107	NEW_PAD_CTRL(MX53_PAD_FEC_TX_EN__FEC_TX_EN, PAD_CTL_DSE_HIGH),
	108	NEW_PAD_CTRL(MX53_PAD_FEC_RXD0__FEC_RDATA_0,
	109	PAD_CTL_HYS \| PAD_CTL_PKE),
	110	NEW_PAD_CTRL(MX53_PAD_FEC_RXD1__FEC_RDATA_1,
	111	PAD_CTL_HYS \| PAD_CTL_PKE),
	112	NEW_PAD_CTRL(MX53_PAD_FEC_TXD0__FEC_TDATA_0, PAD_CTL_DSE_HIGH),
	113	NEW_PAD_CTRL(MX53_PAD_FEC_TXD1__FEC_TDATA_1, PAD_CTL_DSE_HIGH),
	114
	115	/* FEC 1 pads */
	116	NEW_PAD_CTRL(MX53_PAD_KEY_COL0__FEC_RDATA_3,
	117	PAD_CTL_HYS \| PAD_CTL_PKE),
	118	NEW_PAD_CTRL(MX53_PAD_KEY_ROW0__FEC_TX_ER,
	119	PAD_CTL_HYS \| PAD_CTL_PKE),
	120	NEW_PAD_CTRL(MX53_PAD_KEY_COL1__FEC_RX_CLK,
	121	PAD_CTL_HYS \| PAD_CTL_PKE),
	122	NEW_PAD_CTRL(MX53_PAD_KEY_ROW1__FEC_COL,
	123	PAD_CTL_HYS \| PAD_CTL_PKE),
	124	NEW_PAD_CTRL(MX53_PAD_KEY_COL2__FEC_RDATA_2,
	125	PAD_CTL_HYS \| PAD_CTL_PKE),
	126	NEW_PAD_CTRL(MX53_PAD_KEY_ROW2__FEC_TDATA_2, PAD_CTL_DSE_HIGH),
	127	NEW_PAD_CTRL(MX53_PAD_KEY_COL3__FEC_CRS,
	128	PAD_CTL_HYS \| PAD_CTL_PKE),
	129	NEW_PAD_CTRL(MX53_PAD_GPIO_19__FEC_TDATA_3, PAD_CTL_DSE_HIGH),
	130	};
	131
	132	imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
	133	}
	134
e37ac717	135	#ifdef CONFIG_FSL_ESDHC_IMX
39cb4f3c MV	136	struct fsl_esdhc_cfg esdhc_cfg = {
	137	MMC_SDHC1_BASE_ADDR,
	138	};
	139
	140	int board_mmc_getcd(struct mmc *mmc)
	141	{
	142	imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
	143	gpio_direction_input(IMX_GPIO_NR(1, 1));
	144
	145	return !gpio_get_value(IMX_GPIO_NR(1, 1));
	146	}
	147
	148	#define SD_CMD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_DSE_HIGH \| \
	149	PAD_CTL_PUS_100K_UP)
	150	#define SD_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_PUS_47K_UP \| \
	151	PAD_CTL_DSE_HIGH)
	152
b75d8dc5	153	int board_mmc_init(struct bd_info *bis)
39cb4f3c MV	154	{
	155	static const iomux_v3_cfg_t sd1_pads[] = {
	156	NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
	157	NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_PAD_CTRL),
	158	NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
	159	NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
	160	NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
	161	NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
	162	};
	163
	164	esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
	165
	166	imx_iomux_v3_setup_multiple_pads(sd1_pads, ARRAY_SIZE(sd1_pads));
	167
	168	return fsl_esdhc_initialize(bis, &esdhc_cfg);
	169	}
	170	#endif
	171
39cb4f3c MV	172	static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk)
	173	{
	174	static struct mxc_ccm_reg mxc_ccm = (struct mxc_ccm_reg )MXC_CCM_BASE;
	175	int ret;
	176
	177	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
	178	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
	179
	180	/*
	181	* Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
	182	* 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	183	*/
	184	ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
	185	if (ret)
	186	puts("IPU: Failed to configure LDB clock\n");
	187
	188	/* Configure CCM_CSCMR2 */
	189	clrsetbits_le32(&mxc_ccm->cscmr2,
	190	(0x7 << 26) \| BIT(10) \| BIT(8),
	191	(0x5 << 26) \| BIT(10) \| BIT(8));
	192
	193	/* Configure LDB_CTRL */
	194	writel(0x201, 0x53fa8008);
	195	}
	196
	197	static void enable_lvds_etm0430g0dh6(struct display_info_t const *dev)
	198	{
9b352ae1 MV	199	gpio_request(IMX_GPIO_NR(6, 0), "LCD");
9b352ae1 MV	200
39cb4f3c MV	201	/* For ETM0430G0DH6 model, this must be enabled before the clock. */
	202	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
	203
	204	/*
	205	* Set LVDS clock to 9 MHz for the display. The PLL4 is set to
	206	* 63 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	207	*/
	208	enable_lvds_clock(dev, 63);
	209	}
	210
	211	static void enable_lvds_etm0700g0dh6(struct display_info_t const *dev)
	212	{
9b352ae1 MV	213	gpio_request(IMX_GPIO_NR(6, 0), "LCD");
9b352ae1 MV	214
39cb4f3c MV	215	/*
	216	* Set LVDS clock to 33.28 MHz for the display. The PLL4 is set to
	217	* 233 MHz, divided by 7 by setting CCM_CSCMR2 LDB_DI0_IPU_DIV=1 .
	218	*/
	219	enable_lvds_clock(dev, 233);
	220
	221	/* For ETM0700G0DH6 model, this may be enabled after the clock. */
	222	gpio_direction_output(IMX_GPIO_NR(6, 0), 1);
	223	}
	224
	225	static const char *lvds_compat_string;
	226
	227	static int detect_lvds(struct display_info_t const *dev)
	228	{
9d371e5f	229	struct udevice idev, ibus;
39cb4f3c MV	230	u8 touchid[23];
	231	u8 *touchptr = &touchid[0];
	232	int ret;
	233
9d371e5f MV	234	ret = uclass_get_device_by_seq(UCLASS_I2C, 0, &ibus);
	235	if (ret)
	236	return 0;
	237
	238	ret = dm_i2c_probe(ibus, 0x38, 0, &idev);
39cb4f3c MV	239	if (ret)
	240	return 0;
	241
	242	/* Touchscreen is at address 0x38, ID register is 0xbb. */
9d371e5f	243	ret = dm_i2c_read(idev, 0xbb, touchid, sizeof(touchid));
39cb4f3c MV	244	if (ret)
	245	return 0;
	246
	247	/* EP0430 prefixes the response with 0xbb, skip it. */
	248	if (*touchptr == 0xbb)
	249	touchptr++;
	250
	251	/* Skip the 'EP' prefix. */
	252	touchptr += 2;
	253
	254	ret = !memcmp(touchptr, &dev->mode.name[7], 4);
	255	if (ret)
	256	lvds_compat_string = dev->mode.name;
	257
	258	return ret;
	259	}
	260
	261	void board_preboot_os(void)
	262	{
	263	/* Power off the LCD to prevent awful color flicker */
	264	gpio_direction_output(IMX_GPIO_NR(6, 0), 0);
	265	}
	266
e775fc67	267	#if CONFIG_IS_ENABLED(OF_LIBFDT)
b75d8dc5	268	int ft_board_setup(void blob, struct bd_info bd)
39cb4f3c MV	269	{
	270	if (lvds_compat_string)
	271	do_fixup_by_path_string(blob, "/panel", "compatible",
	272	lvds_compat_string);
	273
	274	return 0;
	275	}
e775fc67	276	#endif
39cb4f3c MV	277
	278	struct display_info_t const displays[] = {
	279	{
	280	.bus = 0,
	281	.addr = 0,
	282	.detect = detect_lvds,
	283	.enable = enable_lvds_etm0430g0dh6,
	284	.pixfmt = IPU_PIX_FMT_RGB666,
	285	.mode = {
	286	.name = "edt,etm0430g0dh6",
	287	.refresh = 60,
	288	.xres = 480,
	289	.yres = 272,
	290	.pixclock = 111111, /* picosecond (9 MHz) */
	291	.left_margin = 2,
	292	.right_margin = 2,
	293	.upper_margin = 2,
	294	.lower_margin = 2,
	295	.hsync_len = 41,
	296	.vsync_len = 10,
	297	.sync = 0x40000000,
	298	.vmode = FB_VMODE_NONINTERLACED
	299	}
	300	}, {
	301	.bus = 0,
	302	.addr = 0,
	303	.detect = detect_lvds,
	304	.enable = enable_lvds_etm0700g0dh6,
	305	.pixfmt = IPU_PIX_FMT_RGB666,
	306	.mode = {
	307	.name = "edt,etm0700g0dh6",
	308	.refresh = 60,
	309	.xres = 800,
	310	.yres = 480,
	311	.pixclock = 30048, /* picosecond (33.28 MHz) */
	312	.left_margin = 40,
	313	.right_margin = 88,
	314	.upper_margin = 10,
	315	.lower_margin = 33,
	316	.hsync_len = 128,
	317	.vsync_len = 2,
	318	.sync = FB_SYNC_EXT,
	319	.vmode = FB_VMODE_NONINTERLACED
	320	}
	321	}
	322	};
	323
	324	size_t display_count = ARRAY_SIZE(displays);
39cb4f3c MV	325
	326	#ifdef CONFIG_SPLASH_SCREEN
	327	static struct splash_location default_splash_locations[] = {
	328	{
	329	.name = "mmc_fs",
	330	.storage = SPLASH_STORAGE_MMC,
	331	.flags = SPLASH_STORAGE_FS,
	332	.devpart = "0:1",
	333	},
	334	};
	335
	336	int splash_screen_prepare(void)
	337	{
	338	return splash_source_load(default_splash_locations,
	339	ARRAY_SIZE(default_splash_locations));
	340	}
	341	#endif
	342
f0be8ff4 MV	343	int board_late_init(void)
f0be8ff4 MV	344	{
92f67189 MV	345	#ifdef CONFIG_CMD_BMODE
	346	add_board_boot_modes(NULL);
	347	#endif
	348
f0be8ff4 MV	349	#if defined(CONFIG_VIDEO_IPUV3)
	350	struct udevice *dev;
	351	int xpos, ypos, ret;
	352	char *s;
	353	void *dst;
	354	ulong addr, len;
	355
	356	splash_get_pos(&xpos, &ypos);
	357
	358	s = env_get("splashimage");
	359	if (!s)
	360	return 0;
	361
7e5f460e	362	addr = hextoul(s, NULL);
e6550033	363	dst = malloc(CONFIG_VIDEO_LOGO_MAX_SIZE);
f0be8ff4 MV	364	if (!dst)
	365	return -ENOMEM;
	366
	367	ret = splash_screen_prepare();
	368	if (ret < 0)
dae6cb8f	369	goto splasherr;
f0be8ff4	370
e6550033 SG	371	len = CONFIG_VIDEO_LOGO_MAX_SIZE;
e6550033 SG	372	ret = gunzip(dst + 2, CONFIG_VIDEO_LOGO_MAX_SIZE - 2,
f0be8ff4 MV	373	(uchar *)addr, &len);
	374	if (ret) {
	375	printf("Error: no valid bmp or bmp.gz image at %lx\n", addr);
dae6cb8f	376	goto splasherr;
f0be8ff4 MV	377	}
	378
	379	ret = uclass_get_device(UCLASS_VIDEO, 0, &dev);
	380	if (ret)
dae6cb8f	381	goto splasherr;
f0be8ff4 MV	382
	383	ret = video_bmp_display(dev, (ulong)dst + 2, xpos, ypos, true);
	384	if (ret)
dae6cb8f MV	385	goto splasherr;
	386
	387	return 0;
	388
	389	splasherr:
	390	free(dst);
f0be8ff4 MV	391	#endif
	392	return 0;
	393	}
	394
39cb4f3c MV	395	static void setup_iomux_video(void)
	396	{
	397	static const iomux_v3_cfg_t lcd_pads[] = {
	398	MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3,
	399	MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK,
	400	MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2,
	401	MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1,
	402	MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0,
	403	};
	404
	405	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
	406	}
	407
	408	static void setup_iomux_nand(void)
	409	{
	410	static const iomux_v3_cfg_t nand_pads[] = {
	411	NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
	412	PAD_CTL_DSE_HIGH),
	413	NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
	414	PAD_CTL_DSE_HIGH),
	415	NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
	416	PAD_CTL_DSE_HIGH),
	417	NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
	418	PAD_CTL_DSE_HIGH),
	419	NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
	420	PAD_CTL_PUS_100K_UP),
	421	NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
	422	PAD_CTL_PUS_100K_UP),
	423	NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
	424	PAD_CTL_DSE_HIGH),
	425	NEW_PAD_CTRL(MX53_PAD_PATA_DATA0__EMI_NANDF_D_0,
	426	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	427	NEW_PAD_CTRL(MX53_PAD_PATA_DATA1__EMI_NANDF_D_1,
	428	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	429	NEW_PAD_CTRL(MX53_PAD_PATA_DATA2__EMI_NANDF_D_2,
	430	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	431	NEW_PAD_CTRL(MX53_PAD_PATA_DATA3__EMI_NANDF_D_3,
	432	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	433	NEW_PAD_CTRL(MX53_PAD_PATA_DATA4__EMI_NANDF_D_4,
	434	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	435	NEW_PAD_CTRL(MX53_PAD_PATA_DATA5__EMI_NANDF_D_5,
	436	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	437	NEW_PAD_CTRL(MX53_PAD_PATA_DATA6__EMI_NANDF_D_6,
	438	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	439	NEW_PAD_CTRL(MX53_PAD_PATA_DATA7__EMI_NANDF_D_7,
	440	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE),
	441	};
	442
	443	imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
	444	}
	445
	446	static void m53_set_clock(void)
	447	{
	448	int ret;
	449	const u32 ref_clk = MXC_HCLK;
	450	const u32 dramclk = 400;
	451	u32 cpuclk;
	452
9b352ae1 MV	453	gpio_request(IMX_GPIO_NR(4, 0), "CPUCLK");
9b352ae1 MV	454
39cb4f3c MV	455	imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX53_PAD_GPIO_10__GPIO4_0,
	456	PAD_CTL_DSE_HIGH \| PAD_CTL_PKE));
	457	gpio_direction_input(IMX_GPIO_NR(4, 0));
	458
	459	/* GPIO10 selects modules' CPU speed, 1 = 1200MHz ; 0 = 800MHz */
	460	cpuclk = gpio_get_value(IMX_GPIO_NR(4, 0)) ? 1200 : 800;
	461
	462	ret = mxc_set_clock(ref_clk, cpuclk, MXC_ARM_CLK);
	463	if (ret)
	464	printf("CPU: Switch CPU clock to %dMHz failed\n", cpuclk);
	465
	466	ret = mxc_set_clock(ref_clk, dramclk, MXC_PERIPH_CLK);
	467	if (ret) {
	468	printf("CPU: Switch peripheral clock to %dMHz failed\n",
	469	dramclk);
	470	}
	471
	472	ret = mxc_set_clock(ref_clk, dramclk, MXC_DDR_CLK);
	473	if (ret)
	474	printf("CPU: Switch DDR clock to %dMHz failed\n", dramclk);
	475	}
	476
	477	static void m53_set_nand(void)
	478	{
	479	u32 i;
	480
	481	/* NAND flash is muxed on ATA pins */
	482	setbits_le32(M4IF_BASE_ADDR + 0xc, M4IF_GENP_WEIM_MM_MASK);
	483
	484	/* Wait for Grant/Ack sequence (see EIM_CSnGCR2:MUX16_BYP_GRANT) */
	485	for (i = 0x4; i < 0x94; i += 0x18) {
	486	clrbits_le32(WEIM_BASE_ADDR + i,
	487	WEIM_GCR2_MUX16_BYP_GRANT_MASK);
	488	}
	489
	490	mxc_set_clock(0, 33, MXC_NFC_CLK);
	491	enable_nfc_clk(1);
	492	}
	493
	494	int board_early_init_f(void)
	495	{
	496	setup_iomux_uart();
	497	setup_iomux_fec();
39cb4f3c MV	498	setup_iomux_nand();
	499	setup_iomux_video();
	500
	501	m53_set_clock();
	502
	503	mxc_set_sata_internal_clock();
	504
	505	/* NAND clock @ 33MHz */
	506	m53_set_nand();
	507
	508	return 0;
	509	}
	510
	511	int board_init(void)
	512	{
	513	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
	514
	515	return 0;
	516	}
	517
	518	int checkboard(void)
	519	{
	520	puts("Board: Menlosystems M53Menlo\n");
	521
	522	return 0;
	523	}
	524
	525	/*
	526	* NAND SPL
	527	*/
	528	#ifdef CONFIG_SPL_BUILD
	529	void spl_board_init(void)
	530	{
	531	setup_iomux_nand();
	532	m53_set_clock();
	533	m53_set_nand();
	534	}
	535
	536	u32 spl_boot_device(void)
	537	{
	538	return BOOT_DEVICE_NAND;
	539	}
	540	#endif