[people/ms/u-boot.git] / board / micronas / vct / vct.c

/*
 * (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
 *
 * Copyright (C) 2006 Micronas GmbH
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <netdev.h>
#include <asm/mipsregs.h>
#include "vct.h"

#if defined(CONFIG_VCT_PREMIUM)
#define BOARD_NAME	"PremiumD"
#elif defined(CONFIG_VCT_PLATINUM)
#define BOARD_NAME	"PlatinumD"
#elif defined(CONFIG_VCT_PLATINUMAVC)
#define BOARD_NAME	"PlatinumAVC"
#else
#error "vct: No board variant defined!"
#endif

#if defined(CONFIG_VCT_ONENAND)
#define BOARD_NAME_ADD	" OneNAND"
#else
#define BOARD_NAME_ADD	" NOR"
#endif

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f(void)
{
	/*
	 * First initialize the PIN mulitplexing
	 */
	vct_pin_mux_initialize();

	/*
	 * Init the EBI very early so that FLASH can be accessed
	 */
	ebi_initialize();

	return 0;
}

void _machine_restart(void)
{
	reg_write(DCGU_EN_WDT_RESET(DCGU_BASE), DCGU_MAGIC_WDT);
	reg_write(WDT_TORR(WDT_BASE), 0x00);
	reg_write(WDT_CR(WDT_BASE), 0x1D);

	/*
	 * Now wait for the watchdog to trigger the reset
	 */
	udelay(1000000);
}

/*
 * SDRAM is already configured by the bootstrap code, only return the
 * auto-detected size here
 */
int initdram(void)
{
	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
			    CONFIG_SYS_MBYTES_SDRAM << 20);

	return 0;
}

int checkboard(void)
{
	char buf[64];
	int i = getenv_f("serial#", buf, sizeof(buf));
	u32 config0 = read_c0_prid();

	if ((config0 & 0xff0000) == PRID_COMP_LEGACY
	    && (config0 & 0xff00) == PRID_IMP_LX4280) {
		puts("Board: MDED \n");
		printf("CPU:   LX4280 id: 0x%02x, rev: 0x%02x\n",
		       (config0 >> 8) & 0xFF, config0 & 0xFF);
	} else if ((config0 & 0xff0000) == PRID_COMP_MIPS
		   && (config0 & 0xff00) == PRID_IMP_VGC) {
		u32 jedec_id = *((u32 *) 0xBEBC71A0);
		if ((((jedec_id) >> 12) & 0xFF) == 0x40) {
			puts("Board: VGCA \n");
		} else if ((((jedec_id) >> 12) & 0xFF) == 0x48
			   || (((jedec_id) >> 12) & 0xFF) == 0x49) {
			puts("Board: VGCB \n");
		}
		printf("CPU:   MIPS 4K id: 0x%02x, rev: 0x%02x\n",
		       (config0 >> 8) & 0xFF, config0 & 0xFF);
	} else if (config0 == 0x19378) {
		printf("CPU:   MIPS 24K id: 0x%02x, rev: 0x%02x\n",
		       (config0 >> 8) & 0xFF, config0 & 0xFF);
	} else {
		printf("Unsupported cpu %d, proc_id=0x%x\n", config0 >> 24,
		       config0);
	}

	printf("Board: Micronas VCT " BOARD_NAME BOARD_NAME_ADD);
	if (i > 0) {
		puts(", serial# ");
		puts(buf);
	}
	putc('\n');

	return 0;
}

int board_eth_init(bd_t *bis)
{
	int rc = 0;
#ifdef CONFIG_SMC911X
	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
#endif
	return rc;
}
Commit	Line	Data
ae691e57 SR	1	/*
	2	* (C) Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
	3	*
	4	* Copyright (C) 2006 Micronas GmbH
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
ae691e57 SR	7	*/
	8
	9	#include <common.h>
	10	#include <command.h>
736fead8	11	#include <netdev.h>
ae691e57 SR	12	#include <asm/mipsregs.h>
	13	#include "vct.h"
	14
	15	#if defined(CONFIG_VCT_PREMIUM)
	16	#define BOARD_NAME "PremiumD"
	17	#elif defined(CONFIG_VCT_PLATINUM)
	18	#define BOARD_NAME "PlatinumD"
	19	#elif defined(CONFIG_VCT_PLATINUMAVC)
	20	#define BOARD_NAME "PlatinumAVC"
	21	#else
	22	#error "vct: No board variant defined!"
	23	#endif
	24
	25	#if defined(CONFIG_VCT_ONENAND)
	26	#define BOARD_NAME_ADD " OneNAND"
	27	#else
	28	#define BOARD_NAME_ADD " NOR"
	29	#endif
	30
088454cd SG	31	DECLARE_GLOBAL_DATA_PTR;
088454cd SG	32
ae691e57 SR	33	int board_early_init_f(void)
	34	{
	35	/*
	36	* First initialize the PIN mulitplexing
	37	*/
	38	vct_pin_mux_initialize();
	39
	40	/*
	41	* Init the EBI very early so that FLASH can be accessed
	42	*/
	43	ebi_initialize();
	44
	45	return 0;
	46	}
	47
	48	void _machine_restart(void)
	49	{
	50	reg_write(DCGU_EN_WDT_RESET(DCGU_BASE), DCGU_MAGIC_WDT);
	51	reg_write(WDT_TORR(WDT_BASE), 0x00);
	52	reg_write(WDT_CR(WDT_BASE), 0x1D);
	53
	54	/*
	55	* Now wait for the watchdog to trigger the reset
	56	*/
	57	udelay(1000000);
	58	}
	59
	60	/*
	61	* SDRAM is already configured by the bootstrap code, only return the
	62	* auto-detected size here
	63	*/
088454cd	64	int initdram(void)
ae691e57	65	{
088454cd	66	gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
ae691e57	67	CONFIG_SYS_MBYTES_SDRAM << 20);
088454cd SG	68
088454cd SG	69	return 0;
ae691e57 SR	70	}
	71
	72	int checkboard(void)
	73	{
f0c0b3a9 WD	74	char buf[64];
f0c0b3a9 WD	75	int i = getenv_f("serial#", buf, sizeof(buf));
ae691e57	76	u32 config0 = read_c0_prid();
ae691e57 SR	77
	78	if ((config0 & 0xff0000) == PRID_COMP_LEGACY
	79	&& (config0 & 0xff00) == PRID_IMP_LX4280) {
	80	puts("Board: MDED \n");
	81	printf("CPU: LX4280 id: 0x%02x, rev: 0x%02x\n",
	82	(config0 >> 8) & 0xFF, config0 & 0xFF);
	83	} else if ((config0 & 0xff0000) == PRID_COMP_MIPS
	84	&& (config0 & 0xff00) == PRID_IMP_VGC) {
	85	u32 jedec_id = ((u32 ) 0xBEBC71A0);
	86	if ((((jedec_id) >> 12) & 0xFF) == 0x40) {
	87	puts("Board: VGCA \n");
	88	} else if ((((jedec_id) >> 12) & 0xFF) == 0x48
	89	\|\| (((jedec_id) >> 12) & 0xFF) == 0x49) {
	90	puts("Board: VGCB \n");
	91	}
	92	printf("CPU: MIPS 4K id: 0x%02x, rev: 0x%02x\n",
	93	(config0 >> 8) & 0xFF, config0 & 0xFF);
	94	} else if (config0 == 0x19378) {
	95	printf("CPU: MIPS 24K id: 0x%02x, rev: 0x%02x\n",
	96	(config0 >> 8) & 0xFF, config0 & 0xFF);
	97	} else {
	98	printf("Unsupported cpu %d, proc_id=0x%x\n", config0 >> 24,
	99	config0);
	100	}
	101
	102	printf("Board: Micronas VCT " BOARD_NAME BOARD_NAME_ADD);
f0c0b3a9	103	if (i > 0) {
ae691e57	104	puts(", serial# ");
f0c0b3a9	105	puts(buf);
ae691e57 SR	106	}
	107	putc('\n');
	108
	109	return 0;
	110	}
736fead8 BW	111
	112	int board_eth_init(bd_t *bis)
	113	{
	114	int rc = 0;
	115	#ifdef CONFIG_SMC911X
	116	rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
	117	#endif
	118	return rc;
	119	}