[thirdparty/u-boot.git] / board / mntre / imx8mq_reform2 / spl.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright 2018 NXP
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <hang.h>
#include <image.h>
#include <init.h>
#include <log.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
#include <asm/io.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mq_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clock.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/gpio.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/sections.h>
#include <fsl_esdhc_imx.h>
#include <mmc.h>
#include <linux/delay.h>
#include <power/pmic.h>
#include <spl.h>

DECLARE_GLOBAL_DATA_PTR;

extern struct dram_timing_info dram_timing_ch2;

static void spl_dram_init(void)
{
	ddr_init(&dram_timing_ch2);
}

#define I2C_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
static struct i2c_pads_info i2c_pad_info1 = {
	.scl = {
		.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
		.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
		.gp = IMX_GPIO_NR(5, 14),
	},
	.sda = {
		.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
		.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
		.gp = IMX_GPIO_NR(5, 15),
	},
};

#define USDHC2_VSEL	IMX_GPIO_NR(1, 8)
#define USDHC2_CD_GPIO	IMX_GPIO_NR(2, 12)
#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC1_BASE_ADDR:
		ret = 1;
		break;
	case USDHC2_BASE_ADDR:
		ret = !gpio_get_value(USDHC2_CD_GPIO);
		return ret;
	}

	return 1;
}

#define USDHC_PAD_CTRL	(PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
			 PAD_CTL_FSEL2)
#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)

static iomux_v3_cfg_t const usdhc1_pads[] = {
	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
};

static iomux_v3_cfg_t const usdhc2_pads[] = {
	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
	IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91),
};

static struct fsl_esdhc_cfg usdhc_cfg[2] = {
	{USDHC1_BASE_ADDR, 0, 8},
	{USDHC2_BASE_ADDR, 0, 4},
};

int board_mmc_init(struct bd_info *bis)
{
	int i, ret;
	/*
	 * According to the board_mmc_init() the following map is done:
	 * (U-Boot device node)    (Physical Port)
	 * mmc0                    USDHC1
	 * mmc1                    USDHC2
	 */
	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
		switch (i) {
		case 0:
			init_clk_usdhc(0);
			usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
			imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
							 ARRAY_SIZE(usdhc1_pads));
			gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
			gpio_direction_output(USDHC1_PWR_GPIO, 0);
			udelay(500);
			gpio_direction_output(USDHC1_PWR_GPIO, 1);
			break;
		case 1:
			init_clk_usdhc(1);
			usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
			imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
							 ARRAY_SIZE(usdhc2_pads));
			gpio_request(USDHC2_VSEL, "usdhc2_vsel");
			gpio_direction_output(USDHC2_VSEL, 0);
			break;
		default:
			printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
			return -EINVAL;
		}

		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		if (ret)
			return ret;
	}

	return 0;
}

#define I2C1_PCA9546_RESET	IMX_GPIO_NR(1, 4)
#define ARM_DRAM_VSEL		IMX_GPIO_NR(3, 24)
#define DRAM_1P1_VSEL		IMX_GPIO_NR(2, 11)
#define SOC_GPU_VPU_VSEL	IMX_GPIO_NR(2, 20)

#define I2C_MUX_ADDR		0x70
#define I2C_FAN53555_ADDR	0x60

static iomux_v3_cfg_t const power_pads[] = {
	IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46),
};

int power_init_board(void)
{
	uint8_t val;

	imx_iomux_v3_setup_multiple_pads(power_pads,
					 ARRAY_SIZE(usdhc2_pads));

	/* Release I2C multiplexer reset */
	gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
	gpio_direction_output(I2C1_PCA9546_RESET, 1);

	/* Select VSEL0 on voltage regulators */
	gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
	gpio_direction_output(ARM_DRAM_VSEL, 0);
	gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
	gpio_direction_output(DRAM_1P1_VSEL, 0);
	gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
	gpio_direction_output(SOC_GPU_VPU_VSEL, 0);

	/* Set mux to target ARM/DRAM regulator */
	i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
	/* .6 + .40 = 1.00 */
	val = 0x80 + 40;
	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);

	/* Set mux to target DRAM regulator */
	i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
	/* .6 + .50 = 1.10 */
	val = 0x80 + 50;
	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);

	/* Set mux to target SoC/GPU/VPU regulator */
	i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
	/*  .6 + .30 = .90 */
	val = 0x80 + 30;
	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);

	/* Set mux to target peripherals */
	i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);

	return 0;
}

void spl_board_init(void)
{
	puts("Normal Boot\n");
}

#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
	/* Just empty function now - can't decide what to choose */
	debug("%s: %s\n", __func__, name);

	return 0;
}
#endif

void board_init_f(ulong dummy)
{
	int ret;

	/* Clear global data */
	memset((void *)gd, 0, sizeof(gd_t));

	arch_cpu_init();

	init_uart_clk(0);

	board_early_init_f();

	timer_init();

	preloader_console_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	ret = spl_init();
	if (ret) {
		debug("spl_init() failed: %d\n", ret);
		hang();
	}

	enable_tzc380();

	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);

	power_init_board();

	/* DDR initialization */
	spl_dram_init();

	board_init_r(NULL, 0);
}
Commit	Line	Data
ebe2e0c3 PW	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright 2018 NXP
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
d678a59d	8	#include <common.h>
ebe2e0c3 PW	9	#include <hang.h>
	10	#include <image.h>
	11	#include <init.h>
	12	#include <log.h>
	13	#include <asm/global_data.h>
	14	#include <asm/io.h>
	15	#include <errno.h>
	16	#include <asm/io.h>
	17	#include <asm/arch/ddr.h>
	18	#include <asm/arch/imx8mq_pins.h>
	19	#include <asm/arch/sys_proto.h>
	20	#include <asm/arch/clock.h>
	21	#include <asm/mach-imx/iomux-v3.h>
	22	#include <asm/mach-imx/gpio.h>
	23	#include <asm/mach-imx/mxc_i2c.h>
506df9dc	24	#include <asm/sections.h>
ebe2e0c3 PW	25	#include <fsl_esdhc_imx.h>
	26	#include <mmc.h>
	27	#include <linux/delay.h>
	28	#include <power/pmic.h>
	29	#include <spl.h>
	30
	31	DECLARE_GLOBAL_DATA_PTR;
	32
	33	extern struct dram_timing_info dram_timing_ch2;
	34
	35	static void spl_dram_init(void)
	36	{
	37	ddr_init(&dram_timing_ch2);
	38	}
	39
	40	#define I2C_PAD_CTRL (PAD_CTL_DSE6 \| PAD_CTL_HYS \| PAD_CTL_PUE)
	41	#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
	42	static struct i2c_pads_info i2c_pad_info1 = {
	43	.scl = {
	44	.i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL \| PC,
	45	.gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 \| PC,
	46	.gp = IMX_GPIO_NR(5, 14),
	47	},
	48	.sda = {
	49	.i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA \| PC,
	50	.gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 \| PC,
	51	.gp = IMX_GPIO_NR(5, 15),
	52	},
	53	};
	54
	55	#define USDHC2_VSEL IMX_GPIO_NR(1, 8)
	56	#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
	57	#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
	58
	59	int board_mmc_getcd(struct mmc *mmc)
	60	{
	61	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
	62	int ret = 0;
	63
	64	switch (cfg->esdhc_base) {
	65	case USDHC1_BASE_ADDR:
	66	ret = 1;
	67	break;
	68	case USDHC2_BASE_ADDR:
	69	ret = !gpio_get_value(USDHC2_CD_GPIO);
	70	return ret;
	71	}
	72
	73	return 1;
	74	}
	75
	76	#define USDHC_PAD_CTRL (PAD_CTL_DSE6 \| PAD_CTL_HYS \| PAD_CTL_PUE \| \
	77	PAD_CTL_FSEL2)
	78	#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE \| PAD_CTL_DSE1)
	79
	80	static iomux_v3_cfg_t const usdhc1_pads[] = {
	81	IMX8MQ_PAD_SD1_CLK__USDHC1_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	82	IMX8MQ_PAD_SD1_CMD__USDHC1_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	83	IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	84	IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	85	IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	86	IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	87	IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
	88	IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
89	IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
90	IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
91	IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 \| MUX_PAD_CTRL(NO_PAD_CTRL),
92	};
93
94	static iomux_v3_cfg_t const usdhc2_pads[] = {
95	IMX8MQ_PAD_SD2_CLK__USDHC2_CLK \| MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
96	IMX8MQ_PAD_SD2_CMD__USDHC2_CMD \| MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
97	IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 \| MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
98	IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 \| MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
99	IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 \| MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
100	IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 \| MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
101	IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 \| MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
102	IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 \| MUX_PAD_CTRL(0x91),
103	};
104
105	static struct fsl_esdhc_cfg usdhc_cfg[2] = {
106	{USDHC1_BASE_ADDR, 0, 8},
107	{USDHC2_BASE_ADDR, 0, 4},
108	};
109
110	int board_mmc_init(struct bd_info *bis)
111	{
112	int i, ret;
113	/*
114	* According to the board_mmc_init() the following map is done:
115	* (U-Boot device node) (Physical Port)
116	* mmc0 USDHC1
117	* mmc1 USDHC2
118	*/
119	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
120	switch (i) {
121	case 0:
122	init_clk_usdhc(0);
123	usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
124	imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
125	ARRAY_SIZE(usdhc1_pads));
126	gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
127	gpio_direction_output(USDHC1_PWR_GPIO, 0);
128	udelay(500);
129	gpio_direction_output(USDHC1_PWR_GPIO, 1);
130	break;
131	case 1:
132	init_clk_usdhc(1);
133	usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
134	imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
135	ARRAY_SIZE(usdhc2_pads));
136	gpio_request(USDHC2_VSEL, "usdhc2_vsel");
137	gpio_direction_output(USDHC2_VSEL, 0);
138	break;
139	default:
140	printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
141	return -EINVAL;
142	}
143
144	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
145	if (ret)
146	return ret;
147	}
148
149	return 0;
150	}
151
152	#define I2C1_PCA9546_RESET IMX_GPIO_NR(1, 4)
153	#define ARM_DRAM_VSEL IMX_GPIO_NR(3, 24)
154	#define DRAM_1P1_VSEL IMX_GPIO_NR(2, 11)
155	#define SOC_GPU_VPU_VSEL IMX_GPIO_NR(2, 20)
156
157	#define I2C_MUX_ADDR 0x70
158	#define I2C_FAN53555_ADDR 0x60
159
160	static iomux_v3_cfg_t const power_pads[] = {
161	IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 \| MUX_PAD_CTRL(0x46),
162	};
163
164	int power_init_board(void)
165	{
166	uint8_t val;
167
168	imx_iomux_v3_setup_multiple_pads(power_pads,
169	ARRAY_SIZE(usdhc2_pads));
170
171	/* Release I2C multiplexer reset */
172	gpio_request(I2C1_PCA9546_RESET, "pca9546_reset");
173	gpio_direction_output(I2C1_PCA9546_RESET, 1);
174
175	/* Select VSEL0 on voltage regulators */
176	gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel");
177	gpio_direction_output(ARM_DRAM_VSEL, 0);
178	gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel");
179	gpio_direction_output(DRAM_1P1_VSEL, 0);
180	gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel");
181	gpio_direction_output(SOC_GPU_VPU_VSEL, 0);
182
183	/* Set mux to target ARM/DRAM regulator */
184	i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0);
185	/* .6 + .40 = 1.00 */
186	val = 0x80 + 40;
187	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
188	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
189
190	/* Set mux to target DRAM regulator */
191	i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0);
192	/* .6 + .50 = 1.10 */
193	val = 0x80 + 50;
194	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
195	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
196
197	/* Set mux to target SoC/GPU/VPU regulator */
198	i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0);
199	/* .6 + .30 = .90 */
200	val = 0x80 + 30;
201	i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1);
202	i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1);
203
204	/* Set mux to target peripherals */
205	i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0);
206
207	return 0;
208	}
209
210	void spl_board_init(void)
211	{
212	puts("Normal Boot\n");
213	}
214
215	#ifdef CONFIG_SPL_LOAD_FIT
216	int board_fit_config_name_match(const char *name)
217	{
218	/* Just empty function now - can't decide what to choose */
219	debug("%s: %s\n", __func__, name);
220
221	return 0;
222	}
223	#endif
224
225	void board_init_f(ulong dummy)
226	{
227	int ret;
228
229	/* Clear global data */
230	memset((void *)gd, 0, sizeof(gd_t));
231
232	arch_cpu_init();
233
234	init_uart_clk(0);
235
236	board_early_init_f();
237
238	timer_init();
239
240	preloader_console_init();
241
242	/* Clear the BSS. */
243	memset(__bss_start, 0, __bss_end - __bss_start);
244
245	ret = spl_init();
246	if (ret) {
247	debug("spl_init() failed: %d\n", ret);
248	hang();
249	}
250
251	enable_tzc380();
252
253	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
254
255	power_init_board();
256
257	/* DDR initialization */
258	spl_dram_init();
259
260	board_init_r(NULL, 0);
261	}