projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 029faf3e SR |
1 | /* |
| 2 | * (C) Copyright 2009-2010 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | */ | |
| 23 | ||
| 24 | #include <ppc_asm.tmpl> | |
| 25 | #include <config.h> | |
| 26 | #include <asm/mmu.h> | |
| 27 | ||
| 28 | /* | |
| 29 | * TLB TABLE | |
| 30 | * | |
| 31 | * This table is used by the cpu boot code to setup the initial tlb | |
| 32 | * entries. Rather than make broad assumptions in the cpu source tree, | |
| 33 | * this table lets each board set things up however they like. | |
| 34 | * | |
| 35 | * Pointer to the table is returned in r1 | |
| 36 | * | |
| 37 | */ | |
| 38 | ||
| 39 | .section .bootpg,"ax" | |
| 40 | ||
| 41 | .globl tlbtab | |
| 42 | tlbtab: | |
| 43 | tlbtab_start | |
| 44 | ||
| 45 | /* | |
| 46 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to | |
| 47 | * use the speed up boot process. It is patched after relocation to | |
| 48 | * enable SA_I. | |
| 49 | */ | |
| 50 | tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, | |
| 51 | 4, AC_RWX | SA_G) /* TLB 0 */ | |
| 52 | ||
| 53 | /* | |
| 54 | * TLB entries for SDRAM are not needed on this platform. | |
| 55 | * They are dynamically generated in the SPD DDR(2) detection | |
| 56 | * routine. | |
| 57 | */ | |
| 58 | ||
| 59 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, | |
| 60 | AC_RWX | SA_I) | |
| 61 | ||
| 62 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, | |
| 63 | AC_RW | SA_IG) | |
| 64 | ||
| 65 | tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, | |
| 66 | CONFIG_SYS_ACE_BASE_PHYS_L, CONFIG_SYS_ACE_BASE_PHYS_H, | |
| 67 | AC_RW | SA_IG) | |
| 68 | ||
| 69 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, | |
| 70 | AC_RW | SA_IG) | |
| 71 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, | |
| 72 | AC_RW | SA_IG) | |
| 73 | tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, | |
| 74 | AC_RW | SA_IG) | |
| 75 | ||
| 76 | tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, | |
| 77 | AC_RW | SA_IG) | |
| 78 | tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, | |
| 79 | AC_RW | SA_IG) | |
| 80 | tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, | |
| 81 | AC_RW | SA_IG) | |
| 82 | tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, | |
| 83 | AC_RW | SA_IG) | |
| 84 | tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, | |
| 85 | AC_RW | SA_IG) | |
| 86 | tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, | |
| 87 | AC_RW | SA_IG) | |
| 88 | tlbtab_end |