[people/ms/u-boot.git] / board / motionpro / motionpro.c

/*
 * (C) Copyright 2003-2007
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * modified for Promess PRO - by Andy Joseph, andy@promessdev.com
 * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
 * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
 * Also changed the refresh for 100Mhz operation
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <mpc5xxx.h>
#include <miiphy.h>
#include <libfdt.h>

#if defined(CONFIG_STATUS_LED)
#include <status_led.h>
#endif /* CONFIG_STATUS_LED */

/* Kollmorgen DPR initialization data */
struct init_elem {
	unsigned long addr;
	unsigned len;
	char *data;
	} init_seq[] = {
		{0x500003F2, 2, "\x86\x00"},		/* HW parameter */
		{0x500003F0, 2, "\x00\x00"},
		{0x500003EC, 4, "\x00\x80\xc1\x52"},	/* Magic word */
	};

/*
 * Initialize Kollmorgen DPR
 */
static void kollmorgen_init(void)
{
	unsigned i, j;
	vu_char *p;

	for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) {
		p = (vu_char *)init_seq[i].addr;
		for (j = 0; j < init_seq[i].len; ++j)
			*(p + j) = *(init_seq[i].data + j);
	}

	printf("DPR:   Kollmorgen DPR initialized\n");
}


/*
 * Early board initalization.
 */
int board_early_init_r(void)
{
	/* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */
	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25);
	*(vu_long *)MPC5XXX_ADDECR |= (1 << 16);

	/* Initialize Kollmorgen DPR */
	kollmorgen_init();

	return 0;
}


/*
 * Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(),
 * PHY goes into FX mode.  To take it out of the FX mode and switch into
 * desired TX operation, one needs to clear the FX_SEL bit of Mode Control
 * Register.
 */
void reset_phy(void)
{
	unsigned short mode_control;

	miiphy_read("FEC ETHERNET", CONFIG_PHY_ADDR, 0x15, &mode_control);
	miiphy_write("FEC ETHERNET", CONFIG_PHY_ADDR, 0x15,
			mode_control & 0xfffe);
	return;
}

#ifndef CONFIG_SYS_RAMBOOT
/*
 * Helper function to initialize SDRAM controller.
 */
static void sdram_start(int hi_addr)
{
	long hi_addr_bit = hi_addr ? 0x01000000 : 0;

	/* unlock mode register */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
						hi_addr_bit;

	/* precharge all banks */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
						hi_addr_bit;

	/* auto refresh */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
						hi_addr_bit;

	/* auto refresh, second time */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
						hi_addr_bit;

	/* set mode register */
	*(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;

	/* normal operation */
	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
}
#endif /* !CONFIG_SYS_RAMBOOT */


/*
 * Initalize SDRAM - configure SDRAM controller, detect memory size.
 */
phys_size_t initdram(int board_type)
{
	ulong dramsize = 0;
#ifndef CONFIG_SYS_RAMBOOT
	ulong test1, test2;

	/* According to AN3221 (MPC5200B SDRAM Initialization and
	 * Configuration), the SDelay register must be written a value of
	 * 0x00000004 as the first step of the SDRAM contorller configuration.
	 */
	*(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;

	/* configure SDRAM start/end for detection */
	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */

	/* setup config registers */
	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;

	sdram_start(0);
	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	sdram_start(1);
	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
	if (test1 > test2) {
		sdram_start(0);
		dramsize = test1;
	} else {
		dramsize = test2;
	}

	/* memory smaller than 1MB is impossible */
	if (dramsize < (1 << 20))
		dramsize = 0;

	/* set SDRAM CS0 size according to the amount of RAM found */
	if (dramsize > 0) {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
			__builtin_ffs(dramsize >> 20) - 1;
	} else {
		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
	}

	/* let SDRAM CS1 start right after CS0 and disable it */
	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;

#else /* !CONFIG_SYS_RAMBOOT */
	/* retrieve size of memory connected to SDRAM CS0 */
	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
	if (dramsize >= 0x13)
		dramsize = (1 << (dramsize - 0x13)) << 20;
	else
		dramsize = 0;
#endif /* CONFIG_SYS_RAMBOOT */

	/* return total ram size */
	return dramsize;
}


int checkboard(void)
{
	uchar rev = *(vu_char *)CPLD_REV_REGISTER;
	printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
	return 0;
}


#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
	ft_cpu_setup(blob, bd);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */


#if defined(CONFIG_STATUS_LED)
void __led_init(led_id_t regaddr, int state)
{
	*((vu_long *) regaddr) |= ENABLE_GPIO_OUT;

	if (state == STATUS_LED_ON)
		*((vu_long *) regaddr) |= LED_ON;
	else
		*((vu_long *) regaddr) &= ~LED_ON;
}

void __led_set(led_id_t regaddr, int state)
{
	if (state == STATUS_LED_ON)
		*((vu_long *) regaddr) |= LED_ON;
	else
		*((vu_long *) regaddr) &= ~LED_ON;
}

void __led_toggle(led_id_t regaddr)
{
	*((vu_long *) regaddr) ^= LED_ON;
}
#endif /* CONFIG_STATUS_LED */
Commit	Line	Data
53d4a498 BS	1	/*
	2	* (C) Copyright 2003-2007
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* modified for Promess PRO - by Andy Joseph, andy@promessdev.com
	6	* modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com
	7	* modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3
	8	* Also changed the refresh for 100Mhz operation
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#include <common.h>
	30	#include <mpc5xxx.h>
c00125e0	31	#include <miiphy.h>
cf2817a8	32	#include <libfdt.h>
53d4a498	33
a11c0b85 BS	34	#if defined(CONFIG_STATUS_LED)
	35	#include <status_led.h>
	36	#endif /* CONFIG_STATUS_LED */
	37
53d4a498 BS	38	/* Kollmorgen DPR initialization data */
	39	struct init_elem {
	40	unsigned long addr;
	41	unsigned len;
	42	char *data;
	43	} init_seq[] = {
	44	{0x500003F2, 2, "\x86\x00"}, /* HW parameter */
	45	{0x500003F0, 2, "\x00\x00"},
	46	{0x500003EC, 4, "\x00\x80\xc1\x52"}, /* Magic word */
	47	};
	48
	49	/*
	50	* Initialize Kollmorgen DPR
	51	*/
	52	static void kollmorgen_init(void)
	53	{
	54	unsigned i, j;
	55	vu_char *p;
	56
	57	for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) {
	58	p = (vu_char *)init_seq[i].addr;
	59	for (j = 0; j < init_seq[i].len; ++j)
	60	(p + j) = (init_seq[i].data + j);
	61	}
	62
	63	printf("DPR: Kollmorgen DPR initialized\n");
	64	}
	65
	66
	67	/*
	68	* Early board initalization.
	69	*/
	70	int board_early_init_r(void)
	71	{
	72	/* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */
	73	(vu_long )MPC5XXX_ADDECR &= ~(1 << 25);
	74	(vu_long )MPC5XXX_ADDECR \|= (1 << 16);
	75
	76	/* Initialize Kollmorgen DPR */
	77	kollmorgen_init();
	78
	79	return 0;
	80	}
	81
	82
c00125e0 BS	83	/*
	84	* Additional PHY intialization. After being reset in mpc5xxx_fec_init_phy(),
	85	* PHY goes into FX mode. To take it out of the FX mode and switch into
	86	* desired TX operation, one needs to clear the FX_SEL bit of Mode Control
	87	* Register.
	88	*/
	89	void reset_phy(void)
	90	{
	91	unsigned short mode_control;
	92
	93	miiphy_read("FEC ETHERNET", CONFIG_PHY_ADDR, 0x15, &mode_control);
	94	miiphy_write("FEC ETHERNET", CONFIG_PHY_ADDR, 0x15,
	95	mode_control & 0xfffe);
	96	return;
	97	}
	98
6d0f6bcf	99	#ifndef CONFIG_SYS_RAMBOOT
53d4a498 BS	100	/*
	101	* Helper function to initialize SDRAM controller.
	102	*/
7049288f	103	static void sdram_start(int hi_addr)
53d4a498 BS	104	{
	105	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
	106
	107	/* unlock mode register */
	108	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000000 \|
	109	hi_addr_bit;
	110
	111	/* precharge all banks */
	112	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000002 \|
	113	hi_addr_bit;
	114
	115	/* auto refresh */
	116	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \|
	117	hi_addr_bit;
	118
	119	/* auto refresh, second time */
	120	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| 0x80000004 \|
	121	hi_addr_bit;
	122
	123	/* set mode register */
	124	(vu_long )MPC5XXX_SDRAM_MODE = SDRAM_MODE;
	125
	126	/* normal operation */
	127	(vu_long )MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL \| hi_addr_bit;
	128	}
6d0f6bcf	129	#endif /* !CONFIG_SYS_RAMBOOT */
53d4a498 BS	130
	131
	132	/*
	133	* Initalize SDRAM - configure SDRAM controller, detect memory size.
	134	*/
9973e3c6	135	phys_size_t initdram(int board_type)
53d4a498 BS	136	{
53d4a498 BS	137	ulong dramsize = 0;
6d0f6bcf	138	#ifndef CONFIG_SYS_RAMBOOT
53d4a498 BS	139	ulong test1, test2;
53d4a498 BS	140
eff50190 BS	141	/* According to AN3221 (MPC5200B SDRAM Initialization and
	142	* Configuration), the SDelay register must be written a value of
	143	* 0x00000004 as the first step of the SDRAM contorller configuration.
	144	*/
	145	(vu_long )MPC5XXX_SDRAM_SDELAY = 0x04;
	146
53d4a498 BS	147	/* configure SDRAM start/end for detection */
	148	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */
	149	(vu_long )MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */
	150
	151	/* setup config registers */
	152	(vu_long )MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
	153	(vu_long )MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
	154
	155	sdram_start(0);
6d0f6bcf	156	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
53d4a498	157	sdram_start(1);
6d0f6bcf	158	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
53d4a498 BS	159	if (test1 > test2) {
	160	sdram_start(0);
	161	dramsize = test1;
	162	} else {
	163	dramsize = test2;
	164	}
	165
	166	/* memory smaller than 1MB is impossible */
	167	if (dramsize < (1 << 20))
	168	dramsize = 0;
	169
	170	/* set SDRAM CS0 size according to the amount of RAM found */
74357114	171	if (dramsize > 0) {
53d4a498 BS	172	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0x13 +
53d4a498 BS	173	__builtin_ffs(dramsize >> 20) - 1;
74357114	174	} else {
53d4a498	175	(vu_long )MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
74357114	176	}
53d4a498 BS	177
	178	/* let SDRAM CS1 start right after CS0 and disable it */
	179	(vu_long ) MPC5XXX_SDRAM_CS1CFG = dramsize;
	180
6d0f6bcf	181	#else /* !CONFIG_SYS_RAMBOOT */
53d4a498 BS	182	/* retrieve size of memory connected to SDRAM CS0 */
	183	dramsize = (vu_long )MPC5XXX_SDRAM_CS0CFG & 0xFF;
	184	if (dramsize >= 0x13)
	185	dramsize = (1 << (dramsize - 0x13)) << 20;
	186	else
	187	dramsize = 0;
6d0f6bcf	188	#endif /* CONFIG_SYS_RAMBOOT */
53d4a498 BS	189
	190	/* return total ram size */
	191	return dramsize;
	192	}
	193
	194
7049288f	195	int checkboard(void)
53d4a498	196	{
c75e6396 BS	197	uchar rev = (vu_char )CPLD_REV_REGISTER;
c75e6396 BS	198	printf("Board: Promess Motion-PRO board (CPLD rev. 0x%02x)\n", rev);
53d4a498 BS	199	return 0;
53d4a498 BS	200	}
1f1369c3 BS	201
1f1369c3 BS	202
cf2817a8	203	#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1f1369c3 BS	204	void ft_board_setup(void blob, bd_t bd)
	205	{
	206	ft_cpu_setup(blob, bd);
	207	}
cf2817a8	208	#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
a11c0b85 BS	209
	210
	211	#if defined(CONFIG_STATUS_LED)
7049288f	212	void __led_init(led_id_t regaddr, int state)
a11c0b85 BS	213	{
	214	((vu_long ) regaddr) \|= ENABLE_GPIO_OUT;
	215
	216	if (state == STATUS_LED_ON)
	217	((vu_long ) regaddr) \|= LED_ON;
	218	else
	219	((vu_long ) regaddr) &= ~LED_ON;
	220	}
	221
7049288f	222	void __led_set(led_id_t regaddr, int state)
a11c0b85 BS	223	{
	224	if (state == STATUS_LED_ON)
	225	((vu_long ) regaddr) \|= LED_ON;
	226	else
	227	((vu_long ) regaddr) &= ~LED_ON;
	228	}
	229
7049288f	230	void __led_toggle(led_id_t regaddr)
a11c0b85 BS	231	{
	232	((vu_long ) regaddr) ^= LED_ON;
	233	}
	234	#endif /* CONFIG_STATUS_LED */