[people/ms/u-boot.git] / board / mpc8360emds / pci.c

/*
 * Copyright (C) 2006 Freescale Semiconductor, Inc.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 */

/*
 * PCI Configuration space access support for MPC83xx PCI Bridge
 */
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
#include <pci.h>
#include <i2c.h>
#if defined(CONFIG_OF_FLAT_TREE)
#include <ft_build.h>
#endif

#include <asm/fsl_i2c.h>

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_PCI)
#define PCI_FUNCTION_CONFIG   0x44
#define PCI_FUNCTION_CFG_LOCK 0x20

/*
 * Initialize PCI Devices, report devices found
 */
#ifndef CONFIG_PCI_PNP
static struct pci_config_table pci_mpc83xxemds_config_table[] = {
	{
	 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	 pci_cfgfunc_config_device,
	 {PCI_ENET0_IOADDR,
	  PCI_ENET0_MEMADDR,
	  PCI_COMMON_MEMORY | PCI_COMMAND_MASTER}
	 },
	{}
}
#endif
static struct pci_controller hose[] = {
	{
#ifndef CONFIG_PCI_PNP
	      config_table:pci_mpc83xxemds_config_table,
#endif
	 },
};

/**********************************************************************
 * pci_init_board()
 *********************************************************************/
void pci_init_board(void)
#ifdef CONFIG_PCISLAVE
{
	u16 reg16;
	volatile immap_t *immr;
	volatile law83xx_t *pci_law;
	volatile pot83xx_t *pci_pot;
	volatile pcictrl83xx_t *pci_ctrl;
	volatile pciconf83xx_t *pci_conf;

	immr = (immap_t *) CFG_IMMR;
	pci_law = immr->sysconf.pcilaw;
	pci_pot = immr->ios.pot;
	pci_ctrl = immr->pci_ctrl;
	pci_conf = immr->pci_conf;
	/*
	 * Configure PCI Inbound Translation Windows
	 */
	pci_ctrl[0].pitar0 = 0x0;
	pci_ctrl[0].pibar0 = 0x0;
	pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
	    PIWAR_WTT_SNOOP | PIWAR_IWS_4K;

	pci_ctrl[0].pitar1 = 0x0;
	pci_ctrl[0].pibar1 = 0x0;
	pci_ctrl[0].piebar1 = 0x0;
	pci_ctrl[0].piwar1 &= ~PIWAR_EN;

	pci_ctrl[0].pitar2 = 0x0;
	pci_ctrl[0].pibar2 = 0x0;
	pci_ctrl[0].piebar2 = 0x0;
	pci_ctrl[0].piwar2 &= ~PIWAR_EN;

	hose[0].first_busno = 0;
	hose[0].last_busno = 0xff;
	pci_setup_indirect(&hose[0],
			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
	reg16 = 0xff;

	pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
				  PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
				   PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
				   PCI_STATUS, 0xffff);
	pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
				   PCI_LATENCY_TIMER, 0x80);

	/*
	 * Unlock configuration lock in PCI function configuration register.
	 */
	pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
				  PCI_FUNCTION_CONFIG, &reg16);
	reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
	pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
				   PCI_FUNCTION_CONFIG, reg16);

	printf("Enabled PCI 32bit Agent Mode\n");
}
#else
{
	volatile immap_t *immr;
	volatile clk83xx_t *clk;
	volatile law83xx_t *pci_law;
	volatile pot83xx_t *pci_pot;
	volatile pcictrl83xx_t *pci_ctrl;
	volatile pciconf83xx_t *pci_conf;

	u8 val8, orig_i2c_bus;
	u16 reg16;
	u32 val32;
	u32 dev;

	immr = (immap_t *) CFG_IMMR;
	clk = (clk83xx_t *) & immr->clk;
	pci_law = immr->sysconf.pcilaw;
	pci_pot = immr->ios.pot;
	pci_ctrl = immr->pci_ctrl;
	pci_conf = immr->pci_conf;
	/*
	 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
	 */
	val32 = clk->occr;
	udelay(2000);
#if defined(PCI_66M)
	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
	printf("PCI clock is 66MHz\n");
#elif defined(PCI_33M)
	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
	    OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
	printf("PCI clock is 33MHz\n");
#else
	clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
	printf("PCI clock is 66MHz\n");
#endif
	udelay(2000);

	/*
	 * Configure PCI Local Access Windows
	 */
	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;

	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;

	/*
	 * Configure PCI Outbound Translation Windows
	 */

	/* PCI mem space - prefetch */
	pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[0].pocmr =
	    POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);

	/* PCI mmio - non-prefetch mem space */
	pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);

	/* PCI IO space */
	pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
	pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
	pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);

	/*
	 * Configure PCI Inbound Translation Windows
	 */
	pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
	pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
	pci_ctrl[0].piebar1 = 0x0;
	pci_ctrl[0].piwar1 =
	    PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
	    PIWAR_IWS_2G;

	/*
	 * Assign PIB PMC slot to desired PCI bus
	 */

	/* Switch temporarily to I2C bus #2 */
	orig_i2c_bus = i2c_get_bus_num();
 	i2c_set_bus_num(1);

	val8 = 0;
	i2c_write(0x23, 0x6, 1, &val8, 1);
	i2c_write(0x23, 0x7, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x23, 0x2, 1, &val8, 1);
	i2c_write(0x23, 0x3, 1, &val8, 1);

	val8 = 0;
	i2c_write(0x26, 0x6, 1, &val8, 1);
	val8 = 0x34;
	i2c_write(0x26, 0x7, 1, &val8, 1);

	val8 = 0xf3;		/*PMC1, PMC2, PMC3 slot to PCI bus */
	i2c_write(0x26, 0x2, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x26, 0x3, 1, &val8, 1);

	val8 = 0;
	i2c_write(0x27, 0x6, 1, &val8, 1);
	i2c_write(0x27, 0x7, 1, &val8, 1);
	val8 = 0xff;
	i2c_write(0x27, 0x2, 1, &val8, 1);
	val8 = 0xef;
	i2c_write(0x27, 0x3, 1, &val8, 1);
	asm("eieio");

	/* Reset to original I2C bus */
	i2c_set_bus_num(orig_i2c_bus);

	/*
	 * Release PCI RST Output signal
	 */
	udelay(2000);
	pci_ctrl[0].gcr = 1;
	udelay(2000);

	hose[0].first_busno = 0;
	hose[0].last_busno = 0xff;

	/* PCI memory prefetch space */
	pci_set_region(hose[0].regions + 0,
		       CFG_PCI_MEM_BASE,
		       CFG_PCI_MEM_PHYS,
		       CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);

	/* PCI memory space */
	pci_set_region(hose[0].regions + 1,
		       CFG_PCI_MMIO_BASE,
		       CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM);

	/* PCI IO space */
	pci_set_region(hose[0].regions + 2,
		       CFG_PCI_IO_BASE,
		       CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);

	/* System memory space */
	pci_set_region(hose[0].regions + 3,
		       CFG_PCI_SLV_MEM_LOCAL,
		       CFG_PCI_SLV_MEM_BUS,
		       CFG_PCI_SLV_MEM_SIZE,
		       PCI_REGION_MEM | PCI_REGION_MEMORY);

	hose[0].region_count = 4;

	pci_setup_indirect(&hose[0],
			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));

	pci_register_hose(hose);

	/*
	 * Write command register
	 */
	reg16 = 0xff;
	dev = PCI_BDF(0, 0, 0);
	pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, &reg16);
	reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
	pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);

	/*
	 * Clear non-reserved bits in status register.
	 */
	pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
	pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
	pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);

	printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n");

	/*
	 * Hose scan.
	 */
	hose->last_busno = pci_hose_scan(hose);
}
#endif				/* CONFIG_PCISLAVE */

#ifdef CONFIG_OF_FLAT_TREE
void
ft_pci_setup(void *blob, bd_t *bd)
{
       	u32 *p;
       	int len;

       	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
       	if (p != NULL) {
		p[0] = hose[0].first_busno;
		p[1] = hose[0].last_busno;
       	}
}
#endif				/* CONFIG_OF_FLAT_TREE */
#endif				/* CONFIG_PCI */
Commit	Line	Data
5f820439 DL	1	/*
	2	* Copyright (C) 2006 Freescale Semiconductor, Inc.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*/
	12
	13	/*
	14	* PCI Configuration space access support for MPC83xx PCI Bridge
	15	*/
	16	#include <asm/mmu.h>
	17	#include <asm/io.h>
	18	#include <common.h>
	19	#include <pci.h>
	20	#include <i2c.h>
781e026c KP	21	#if defined(CONFIG_OF_FLAT_TREE)
	22	#include <ft_build.h>
	23	#endif
5f820439	24
be5e6181	25	#include <asm/fsl_i2c.h>
5f820439 DL	26
	27	DECLARE_GLOBAL_DATA_PTR;
	28
	29	#if defined(CONFIG_PCI)
	30	#define PCI_FUNCTION_CONFIG 0x44
	31	#define PCI_FUNCTION_CFG_LOCK 0x20
	32
	33	/*
	34	* Initialize PCI Devices, report devices found
	35	*/
	36	#ifndef CONFIG_PCI_PNP
	37	static struct pci_config_table pci_mpc83xxemds_config_table[] = {
	38	{
	39	PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
	40	pci_cfgfunc_config_device,
	41	{PCI_ENET0_IOADDR,
	42	PCI_ENET0_MEMADDR,
	43	PCI_COMMON_MEMORY \| PCI_COMMAND_MASTER}
	44	},
	45	{}
	46	}
	47	#endif
	48	static struct pci_controller hose[] = {
	49	{
	50	#ifndef CONFIG_PCI_PNP
	51	config_table:pci_mpc83xxemds_config_table,
	52	#endif
	53	},
	54	};
	55
	56	/**********************************************************************
	57	* pci_init_board()
	58	*********************************************************************/
	59	void pci_init_board(void)
	60	#ifdef CONFIG_PCISLAVE
	61	{
	62	u16 reg16;
	63	volatile immap_t *immr;
	64	volatile law83xx_t *pci_law;
	65	volatile pot83xx_t *pci_pot;
	66	volatile pcictrl83xx_t *pci_ctrl;
	67	volatile pciconf83xx_t *pci_conf;
	68
d239d74b	69	immr = (immap_t *) CFG_IMMR;
5f820439 DL	70	pci_law = immr->sysconf.pcilaw;
	71	pci_pot = immr->ios.pot;
	72	pci_ctrl = immr->pci_ctrl;
	73	pci_conf = immr->pci_conf;
	74	/*
	75	* Configure PCI Inbound Translation Windows
	76	*/
	77	pci_ctrl[0].pitar0 = 0x0;
	78	pci_ctrl[0].pibar0 = 0x0;
	79	pci_ctrl[0].piwar0 = PIWAR_EN \| PIWAR_RTT_SNOOP \|
	80	PIWAR_WTT_SNOOP \| PIWAR_IWS_4K;
	81
	82	pci_ctrl[0].pitar1 = 0x0;
	83	pci_ctrl[0].pibar1 = 0x0;
	84	pci_ctrl[0].piebar1 = 0x0;
	85	pci_ctrl[0].piwar1 &= ~PIWAR_EN;
	86
	87	pci_ctrl[0].pitar2 = 0x0;
	88	pci_ctrl[0].pibar2 = 0x0;
	89	pci_ctrl[0].piebar2 = 0x0;
	90	pci_ctrl[0].piwar2 &= ~PIWAR_EN;
	91
	92	hose[0].first_busno = 0;
	93	hose[0].last_busno = 0xff;
	94	pci_setup_indirect(&hose[0],
d239d74b	95	(CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
5f820439 DL	96	reg16 = 0xff;
	97
	98	pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
	99	PCI_COMMAND, &reg16);
	100	reg16 \|= PCI_COMMAND_SERR \| PCI_COMMAND_MEMORY;
	101	pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
	102	PCI_COMMAND, reg16);
	103
	104	/*
	105	* Clear non-reserved bits in status register.
	106	*/
	107	pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
	108	PCI_STATUS, 0xffff);
	109	pci_hose_write_config_byte(&hose[0], PCI_BDF(0, 0, 0),
	110	PCI_LATENCY_TIMER, 0x80);
	111
	112	/*
	113	* Unlock configuration lock in PCI function configuration register.
	114	*/
	115	pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
	116	PCI_FUNCTION_CONFIG, &reg16);
	117	reg16 &= ~(PCI_FUNCTION_CFG_LOCK);
	118	pci_hose_write_config_word(&hose[0], PCI_BDF(0, 0, 0),
	119	PCI_FUNCTION_CONFIG, reg16);
	120
	121	printf("Enabled PCI 32bit Agent Mode\n");
	122	}
	123	#else
	124	{
	125	volatile immap_t *immr;
	126	volatile clk83xx_t *clk;
	127	volatile law83xx_t *pci_law;
	128	volatile pot83xx_t *pci_pot;
	129	volatile pcictrl83xx_t *pci_ctrl;
	130	volatile pciconf83xx_t *pci_conf;
	131
	132	u8 val8, orig_i2c_bus;
	133	u16 reg16;
	134	u32 val32;
	135	u32 dev;
	136
d239d74b	137	immr = (immap_t *) CFG_IMMR;
5f820439 DL	138	clk = (clk83xx_t *) & immr->clk;
	139	pci_law = immr->sysconf.pcilaw;
	140	pci_pot = immr->ios.pot;
	141	pci_ctrl = immr->pci_ctrl;
	142	pci_conf = immr->pci_conf;
	143	/*
	144	* Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
	145	*/
	146	val32 = clk->occr;
	147	udelay(2000);
	148	#if defined(PCI_66M)
	149	clk->occr = OCCR_PCICOE0 \| OCCR_PCICOE1 \| OCCR_PCICOE2;
	150	printf("PCI clock is 66MHz\n");
	151	#elif defined(PCI_33M)
	152	clk->occr = OCCR_PCICOE0 \| OCCR_PCICOE1 \| OCCR_PCICOE2 \|
	153	OCCR_PCICD0 \| OCCR_PCICD1 \| OCCR_PCICD2 \| OCCR_PCICR;
	154	printf("PCI clock is 33MHz\n");
	155	#else
	156	clk->occr = OCCR_PCICOE0 \| OCCR_PCICOE1 \| OCCR_PCICOE2;
	157	printf("PCI clock is 66MHz\n");
	158	#endif
	159	udelay(2000);
	160
	161	/*
	162	* Configure PCI Local Access Windows
	163	*/
	164	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
	165	pci_law[0].ar = LAWAR_EN \| LAWAR_SIZE_512M;
	166
	167	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
	168	pci_law[1].ar = LAWAR_EN \| LAWAR_SIZE_1M;
	169
	170	/*
	171	* Configure PCI Outbound Translation Windows
	172	*/
	173
	174	/* PCI mem space - prefetch */
	175	pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
	176	pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
	177	pci_pot[0].pocmr =
	178	POCMR_EN \| POCMR_SE \| (POCMR_CM_256M & POCMR_CM_MASK);
	179
	180	/* PCI mmio - non-prefetch mem space */
	181	pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
	182	pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
	183	pci_pot[1].pocmr = POCMR_EN \| (POCMR_CM_256M & POCMR_CM_MASK);
	184
	185	/* PCI IO space */
	186	pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
	187	pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
	188	pci_pot[2].pocmr = POCMR_EN \| POCMR_IO \| (POCMR_CM_1M & POCMR_CM_MASK);
	189
	190	/*
	191	* Configure PCI Inbound Translation Windows
	192	*/
	193	pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
	194	pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
	195	pci_ctrl[0].piebar1 = 0x0;
	196	pci_ctrl[0].piwar1 =
	197	PIWAR_EN \| PIWAR_PF \| PIWAR_RTT_SNOOP \| PIWAR_WTT_SNOOP \|
	198	PIWAR_IWS_2G;
	199
	200	/*
	201	* Assign PIB PMC slot to desired PCI bus
202	*/
203
9ca880a2 TT	204	/* Switch temporarily to I2C bus #2 */
9ca880a2 TT	205	orig_i2c_bus = i2c_get_bus_num();
be5e6181	206	i2c_set_bus_num(1);
5f820439 DL	207
	208	val8 = 0;
	209	i2c_write(0x23, 0x6, 1, &val8, 1);
	210	i2c_write(0x23, 0x7, 1, &val8, 1);
	211	val8 = 0xff;
	212	i2c_write(0x23, 0x2, 1, &val8, 1);
	213	i2c_write(0x23, 0x3, 1, &val8, 1);
	214
	215	val8 = 0;
	216	i2c_write(0x26, 0x6, 1, &val8, 1);
	217	val8 = 0x34;
	218	i2c_write(0x26, 0x7, 1, &val8, 1);
	219
	220	val8 = 0xf3; /PMC1, PMC2, PMC3 slot to PCI bus /
	221	i2c_write(0x26, 0x2, 1, &val8, 1);
	222	val8 = 0xff;
	223	i2c_write(0x26, 0x3, 1, &val8, 1);
	224
	225	val8 = 0;
	226	i2c_write(0x27, 0x6, 1, &val8, 1);
	227	i2c_write(0x27, 0x7, 1, &val8, 1);
	228	val8 = 0xff;
	229	i2c_write(0x27, 0x2, 1, &val8, 1);
	230	val8 = 0xef;
	231	i2c_write(0x27, 0x3, 1, &val8, 1);
	232	asm("eieio");
	233
9ca880a2	234	/* Reset to original I2C bus */
be5e6181	235	i2c_set_bus_num(orig_i2c_bus);
bf0b542d	236
5f820439 DL	237	/*
	238	* Release PCI RST Output signal
	239	*/
	240	udelay(2000);
	241	pci_ctrl[0].gcr = 1;
	242	udelay(2000);
	243
	244	hose[0].first_busno = 0;
	245	hose[0].last_busno = 0xff;
	246
	247	/* PCI memory prefetch space */
	248	pci_set_region(hose[0].regions + 0,
	249	CFG_PCI_MEM_BASE,
	250	CFG_PCI_MEM_PHYS,
	251	CFG_PCI_MEM_SIZE, PCI_REGION_MEM \| PCI_REGION_PREFETCH);
	252
	253	/* PCI memory space */
	254	pci_set_region(hose[0].regions + 1,
	255	CFG_PCI_MMIO_BASE,
	256	CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM);
	257
	258	/* PCI IO space */
	259	pci_set_region(hose[0].regions + 2,
	260	CFG_PCI_IO_BASE,
	261	CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
	262
	263	/* System memory space */
	264	pci_set_region(hose[0].regions + 3,
	265	CFG_PCI_SLV_MEM_LOCAL,
	266	CFG_PCI_SLV_MEM_BUS,
	267	CFG_PCI_SLV_MEM_SIZE,
	268	PCI_REGION_MEM \| PCI_REGION_MEMORY);
	269
	270	hose[0].region_count = 4;
	271
	272	pci_setup_indirect(&hose[0],
d239d74b	273	(CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
5f820439 DL	274
	275	pci_register_hose(hose);
	276
	277	/*
	278	* Write command register
	279	*/
	280	reg16 = 0xff;
	281	dev = PCI_BDF(0, 0, 0);
	282	pci_hose_read_config_word(&hose[0], dev, PCI_COMMAND, &reg16);
	283	reg16 \|= PCI_COMMAND_SERR \| PCI_COMMAND_MASTER \| PCI_COMMAND_MEMORY;
	284	pci_hose_write_config_word(&hose[0], dev, PCI_COMMAND, reg16);
	285
	286	/*
	287	* Clear non-reserved bits in status register.
	288	*/
	289	pci_hose_write_config_word(&hose[0], dev, PCI_STATUS, 0xffff);
	290	pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
	291	pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
	292
	293	printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n");
	294
	295	/*
	296	* Hose scan.
	297	*/
	298	hose->last_busno = pci_hose_scan(hose);
	299	}
	300	#endif /* CONFIG_PCISLAVE */
bf0b542d KP	301
	302	#ifdef CONFIG_OF_FLAT_TREE
	303	void
	304	ft_pci_setup(void blob, bd_t bd)
	305	{
	306	u32 *p;
	307	int len;
	308
	309	p = (u32 *)ft_get_prop(blob, "/" OF_SOC "/pci@8500/bus-range", &len);
	310	if (p != NULL) {
	311	p[0] = hose[0].first_busno;
	312	p[1] = hose[0].last_busno;
	313	}
	314	}
	315	#endif /* CONFIG_OF_FLAT_TREE */
5f820439	316	#endif /* CONFIG_PCI */