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7d393aed WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | * | |
24 | * TODO: clean-up | |
25 | */ | |
26 | ||
27 | #include <common.h> | |
28 | #include "pip405.h" | |
29 | #include <asm/processor.h> | |
30 | #include <i2c.h> | |
31 | #include "../common/isa.h" | |
32 | #include "../common/common_util.h" | |
33 | ||
d87080b7 WD |
34 | DECLARE_GLOBAL_DATA_PTR; |
35 | ||
7d393aed WD |
36 | #undef SDRAM_DEBUG |
37 | ||
38 | #define FALSE 0 | |
39 | #define TRUE 1 | |
40 | ||
41 | /* stdlib.h causes some compatibility problems; should fixe these! -- wd */ | |
42 | #ifndef __ldiv_t_defined | |
43 | typedef struct { | |
44 | long int quot; /* Quotient */ | |
45 | long int rem; /* Remainder */ | |
46 | } ldiv_t; | |
47 | extern ldiv_t ldiv (long int __numer, long int __denom); | |
48 | ||
49 | # define __ldiv_t_defined 1 | |
50 | #endif | |
51 | ||
52 | ||
53 | typedef enum { | |
54 | SDRAM_NO_ERR, | |
55 | SDRAM_SPD_COMM_ERR, | |
56 | SDRAM_SPD_CHKSUM_ERR, | |
57 | SDRAM_UNSUPPORTED_ERR, | |
58 | SDRAM_UNKNOWN_ERR | |
59 | } SDRAM_ERR; | |
60 | ||
61 | typedef struct { | |
62 | const unsigned char mode; | |
63 | const unsigned char row; | |
64 | const unsigned char col; | |
65 | const unsigned char bank; | |
66 | } SDRAM_SETUP; | |
67 | ||
68 | static const SDRAM_SETUP sdram_setup_table[] = { | |
69 | {1, 11, 9, 2}, | |
70 | {1, 11, 10, 2}, | |
71 | {2, 12, 9, 4}, | |
72 | {2, 12, 10, 4}, | |
73 | {3, 13, 9, 4}, | |
74 | {3, 13, 10, 4}, | |
75 | {3, 13, 11, 4}, | |
76 | {4, 12, 8, 2}, | |
77 | {4, 12, 8, 4}, | |
78 | {5, 11, 8, 2}, | |
79 | {5, 11, 8, 4}, | |
80 | {6, 13, 8, 2}, | |
81 | {6, 13, 8, 4}, | |
82 | {7, 13, 9, 2}, | |
83 | {7, 13, 10, 2}, | |
84 | {0, 0, 0, 0} | |
85 | }; | |
86 | ||
87 | static const unsigned char cal_indextable[] = { | |
88 | 9, 23, 25 | |
89 | }; | |
90 | ||
91 | ||
92 | /* | |
93 | * translate ns.ns/10 coding of SPD timing values | |
94 | * into 10 ps unit values | |
95 | */ | |
96 | ||
97 | unsigned short NS10to10PS (unsigned char spd_byte, unsigned char spd_version) | |
98 | { | |
99 | unsigned short ns, ns10; | |
100 | ||
101 | /* isolate upper nibble */ | |
102 | ns = (spd_byte >> 4) & 0x0F; | |
103 | /* isolate lower nibble */ | |
104 | ns10 = (spd_byte & 0x0F); | |
105 | ||
106 | return (ns * 100 + ns10 * 10); | |
107 | } | |
108 | ||
109 | /* | |
110 | * translate ns.ns/4 coding of SPD timing values | |
111 | * into 10 ps unit values | |
112 | */ | |
113 | ||
114 | unsigned short NS4to10PS (unsigned char spd_byte, unsigned char spd_version) | |
115 | { | |
116 | unsigned short ns, ns4; | |
117 | ||
118 | /* isolate upper 6 bits */ | |
119 | ns = (spd_byte >> 2) & 0x3F; | |
120 | /* isloate lower 2 bits */ | |
121 | ns4 = (spd_byte & 0x03); | |
122 | ||
123 | return (ns * 100 + ns4 * 25); | |
124 | } | |
125 | ||
126 | /* | |
127 | * translate ns coding of SPD timing values | |
128 | * into 10 ps unit values | |
129 | */ | |
130 | ||
131 | unsigned short NSto10PS (unsigned char spd_byte) | |
132 | { | |
133 | return (spd_byte * 100); | |
134 | } | |
135 | ||
136 | void SDRAM_err (const char *s) | |
137 | { | |
138 | #ifndef SDRAM_DEBUG | |
7d393aed WD |
139 | (void) get_clocks (); |
140 | gd->baudrate = 9600; | |
141 | serial_init (); | |
142 | #endif | |
143 | serial_puts ("\n"); | |
144 | serial_puts (s); | |
145 | serial_puts ("\n enable SDRAM_DEBUG for more info\n"); | |
146 | for (;;); | |
147 | } | |
148 | ||
149 | ||
150 | #ifdef SDRAM_DEBUG | |
151 | ||
152 | void write_hex (unsigned char i) | |
153 | { | |
154 | char cc; | |
155 | ||
156 | cc = i >> 4; | |
157 | cc &= 0xf; | |
158 | if (cc > 9) | |
159 | serial_putc (cc + 55); | |
160 | else | |
161 | serial_putc (cc + 48); | |
162 | cc = i & 0xf; | |
163 | if (cc > 9) | |
164 | serial_putc (cc + 55); | |
165 | else | |
166 | serial_putc (cc + 48); | |
167 | } | |
168 | ||
169 | void write_4hex (unsigned long val) | |
170 | { | |
171 | write_hex ((unsigned char) (val >> 24)); | |
172 | write_hex ((unsigned char) (val >> 16)); | |
173 | write_hex ((unsigned char) (val >> 8)); | |
174 | write_hex ((unsigned char) val); | |
175 | } | |
176 | ||
177 | #endif | |
178 | ||
c837dcb1 | 179 | int board_early_init_f (void) |
7d393aed WD |
180 | { |
181 | unsigned char dataout[1]; | |
182 | unsigned char datain[128]; | |
77ddac94 | 183 | unsigned long sdram_size = 0; |
7d393aed WD |
184 | SDRAM_SETUP *t = (SDRAM_SETUP *) sdram_setup_table; |
185 | unsigned long memclk; | |
186 | unsigned long tmemclk = 0; | |
187 | unsigned long tmp, bank, baseaddr, bank_size; | |
188 | unsigned short i; | |
189 | unsigned char rows, cols, banks, sdram_banks, density; | |
190 | unsigned char supported_cal, trp_clocks, trcd_clocks, tras_clocks, | |
191 | trc_clocks, tctp_clocks; | |
192 | unsigned char cal_index, cal_val, spd_version, spd_chksum; | |
193 | unsigned char buf[8]; | |
7205e407 WD |
194 | /* set up the config port */ |
195 | mtdcr (ebccfga, pb7ap); | |
196 | mtdcr (ebccfgd, CONFIG_PORT_AP); | |
197 | mtdcr (ebccfga, pb7cr); | |
198 | mtdcr (ebccfgd, CONFIG_PORT_CR); | |
7d393aed WD |
199 | |
200 | memclk = get_bus_freq (tmemclk); | |
201 | tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ | |
202 | ||
203 | #ifdef SDRAM_DEBUG | |
204 | (void) get_clocks (); | |
205 | gd->baudrate = 9600; | |
206 | serial_init (); | |
207 | serial_puts ("\nstart SDRAM Setup\n"); | |
208 | #endif | |
209 | ||
210 | /* Read Serial Presence Detect Information */ | |
6d0f6bcf | 211 | i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); |
7d393aed WD |
212 | dataout[0] = 0; |
213 | for (i = 0; i < 128; i++) | |
214 | datain[i] = 127; | |
215 | i2c_read(SPD_EEPROM_ADDRESS,0,1,datain,128); | |
216 | #ifdef SDRAM_DEBUG | |
217 | serial_puts ("\ni2c_read returns "); | |
218 | write_hex (i); | |
219 | serial_puts ("\n"); | |
220 | #endif | |
221 | ||
222 | #ifdef SDRAM_DEBUG | |
223 | for (i = 0; i < 128; i++) { | |
224 | write_hex (datain[i]); | |
225 | serial_puts (" "); | |
226 | if (((i + 1) % 16) == 0) | |
227 | serial_puts ("\n"); | |
228 | } | |
229 | serial_puts ("\n"); | |
230 | #endif | |
231 | spd_chksum = 0; | |
232 | for (i = 0; i < 63; i++) { | |
233 | spd_chksum += datain[i]; | |
234 | } /* endfor */ | |
235 | if (datain[63] != spd_chksum) { | |
236 | #ifdef SDRAM_DEBUG | |
237 | serial_puts ("SPD chksum: 0x"); | |
238 | write_hex (datain[63]); | |
239 | serial_puts (" != calc. chksum: 0x"); | |
240 | write_hex (spd_chksum); | |
241 | serial_puts ("\n"); | |
242 | #endif | |
243 | SDRAM_err ("SPD checksum Error"); | |
244 | } | |
245 | /* SPD seems to be ok, use it */ | |
246 | ||
247 | /* get SPD version */ | |
248 | spd_version = datain[62]; | |
249 | ||
250 | /* do some sanity checks on the kind of RAM */ | |
251 | if ((datain[0] < 0x80) || /* less than 128 valid bytes in SPD */ | |
252 | (datain[2] != 0x04) || /* if not SDRAM */ | |
253 | (!((datain[6] == 0x40) || (datain[6] == 0x48))) || /* or not (64 Bit or 72 Bit) */ | |
254 | (datain[7] != 0x00) || (datain[8] != 0x01) || /* or not LVTTL signal levels */ | |
255 | (datain[126] == 0x66)) /* or a 66Mhz modules */ | |
256 | SDRAM_err ("unsupported SDRAM"); | |
257 | #ifdef SDRAM_DEBUG | |
258 | serial_puts ("SDRAM sanity ok\n"); | |
259 | #endif | |
260 | ||
261 | /* get number of rows/cols/banks out of byte 3+4+5 */ | |
262 | rows = datain[3]; | |
263 | cols = datain[4]; | |
264 | banks = datain[5]; | |
265 | ||
266 | /* get number of SDRAM banks out of byte 17 and | |
267 | supported CAS latencies out of byte 18 */ | |
268 | sdram_banks = datain[17]; | |
269 | supported_cal = datain[18] & ~0x81; | |
270 | ||
271 | while (t->mode != 0) { | |
272 | if ((t->row == rows) && (t->col == cols) | |
273 | && (t->bank == sdram_banks)) | |
274 | break; | |
275 | t++; | |
276 | } /* endwhile */ | |
277 | ||
278 | #ifdef SDRAM_DEBUG | |
279 | serial_puts ("rows: "); | |
280 | write_hex (rows); | |
281 | serial_puts (" cols: "); | |
282 | write_hex (cols); | |
283 | serial_puts (" banks: "); | |
284 | write_hex (banks); | |
285 | serial_puts (" mode: "); | |
286 | write_hex (t->mode); | |
287 | serial_puts ("\n"); | |
288 | #endif | |
289 | if (t->mode == 0) | |
290 | SDRAM_err ("unsupported SDRAM"); | |
291 | /* get tRP, tRCD, tRAS and density from byte 27+29+30+31 */ | |
292 | #ifdef SDRAM_DEBUG | |
293 | serial_puts ("tRP: "); | |
294 | write_hex (datain[27]); | |
295 | serial_puts ("\ntRCD: "); | |
296 | write_hex (datain[29]); | |
297 | serial_puts ("\ntRAS: "); | |
298 | write_hex (datain[30]); | |
299 | serial_puts ("\n"); | |
300 | #endif | |
301 | ||
302 | trp_clocks = (NSto10PS (datain[27]) + (tmemclk - 1)) / tmemclk; | |
303 | trcd_clocks = (NSto10PS (datain[29]) + (tmemclk - 1)) / tmemclk; | |
304 | tras_clocks = (NSto10PS (datain[30]) + (tmemclk - 1)) / tmemclk; | |
305 | density = datain[31]; | |
306 | ||
307 | /* trc_clocks is sum of trp_clocks + tras_clocks */ | |
308 | trc_clocks = trp_clocks + tras_clocks; | |
309 | /* ctp = ((trp + tras) - trp - trcd) => tras - trcd */ | |
310 | tctp_clocks = | |
311 | ((NSto10PS (datain[30]) - NSto10PS (datain[29])) + | |
312 | (tmemclk - 1)) / tmemclk; | |
313 | ||
314 | #ifdef SDRAM_DEBUG | |
315 | serial_puts ("c_RP: "); | |
316 | write_hex (trp_clocks); | |
317 | serial_puts ("\nc_RCD: "); | |
318 | write_hex (trcd_clocks); | |
319 | serial_puts ("\nc_RAS: "); | |
320 | write_hex (tras_clocks); | |
321 | serial_puts ("\nc_RC: (RP+RAS): "); | |
322 | write_hex (trc_clocks); | |
323 | serial_puts ("\nc_CTP: ((RP+RAS)-RP-RCD): "); | |
324 | write_hex (tctp_clocks); | |
325 | serial_puts ("\nt_CTP: RAS - RCD: "); | |
326 | write_hex ((unsigned | |
327 | char) ((NSto10PS (datain[30]) - | |
328 | NSto10PS (datain[29])) >> 8)); | |
329 | write_hex ((unsigned char) (NSto10PS (datain[30]) - NSto10PS (datain[29]))); | |
330 | serial_puts ("\ntmemclk: "); | |
331 | write_hex ((unsigned char) (tmemclk >> 8)); | |
332 | write_hex ((unsigned char) (tmemclk)); | |
333 | serial_puts ("\n"); | |
334 | #endif | |
335 | ||
336 | ||
337 | cal_val = 255; | |
338 | for (i = 6, cal_index = 0; (i > 0) && (cal_index < 3); i--) { | |
339 | /* is this CAS latency supported ? */ | |
340 | if ((supported_cal >> i) & 0x01) { | |
341 | buf[0] = datain[cal_indextable[cal_index]]; | |
342 | if (cal_index < 2) { | |
343 | if (NS10to10PS (buf[0], spd_version) <= tmemclk) | |
344 | cal_val = i; | |
345 | } else { | |
346 | /* SPD bytes 25+26 have another format */ | |
347 | if (NS4to10PS (buf[0], spd_version) <= tmemclk) | |
348 | cal_val = i; | |
349 | } /* endif */ | |
350 | cal_index++; | |
351 | } /* endif */ | |
352 | } /* endfor */ | |
353 | #ifdef SDRAM_DEBUG | |
354 | serial_puts ("CAL: "); | |
355 | write_hex (cal_val + 1); | |
356 | serial_puts ("\n"); | |
357 | #endif | |
358 | ||
359 | if (cal_val == 255) | |
360 | SDRAM_err ("unsupported SDRAM"); | |
361 | ||
362 | /* get SDRAM timing register */ | |
363 | mtdcr (memcfga, mem_sdtr1); | |
364 | tmp = mfdcr (memcfgd) & ~0x018FC01F; | |
365 | /* insert CASL value */ | |
366 | /* tmp |= ((unsigned long)cal_val) << 23; */ | |
367 | tmp |= ((unsigned long) cal_val) << 23; | |
368 | /* insert PTA value */ | |
369 | tmp |= ((unsigned long) (trp_clocks - 1)) << 18; | |
370 | /* insert CTP value */ | |
371 | /* tmp |= ((unsigned long)(trc_clocks - trp_clocks - trcd_clocks - 1)) << 16; */ | |
372 | tmp |= ((unsigned long) (trc_clocks - trp_clocks - trcd_clocks)) << 16; | |
373 | /* insert LDF (always 01) */ | |
374 | tmp |= ((unsigned long) 0x01) << 14; | |
375 | /* insert RFTA value */ | |
376 | tmp |= ((unsigned long) (trc_clocks - 4)) << 2; | |
377 | /* insert RCD value */ | |
378 | tmp |= ((unsigned long) (trcd_clocks - 1)) << 0; | |
379 | ||
380 | #ifdef SDRAM_DEBUG | |
381 | serial_puts ("sdtr: "); | |
382 | write_4hex (tmp); | |
383 | serial_puts ("\n"); | |
384 | #endif | |
385 | ||
386 | /* write SDRAM timing register */ | |
387 | mtdcr (memcfga, mem_sdtr1); | |
388 | mtdcr (memcfgd, tmp); | |
6d0f6bcf | 389 | baseaddr = CONFIG_SYS_SDRAM_BASE; |
7d393aed WD |
390 | bank_size = (((unsigned long) density) << 22) / 2; |
391 | /* insert AM value */ | |
392 | tmp = ((unsigned long) t->mode - 1) << 13; | |
393 | /* insert SZ value; */ | |
394 | switch (bank_size) { | |
395 | case 0x00400000: | |
396 | tmp |= ((unsigned long) 0x00) << 17; | |
397 | break; | |
398 | case 0x00800000: | |
399 | tmp |= ((unsigned long) 0x01) << 17; | |
400 | break; | |
401 | case 0x01000000: | |
402 | tmp |= ((unsigned long) 0x02) << 17; | |
403 | break; | |
404 | case 0x02000000: | |
405 | tmp |= ((unsigned long) 0x03) << 17; | |
406 | break; | |
407 | case 0x04000000: | |
408 | tmp |= ((unsigned long) 0x04) << 17; | |
409 | break; | |
410 | case 0x08000000: | |
411 | tmp |= ((unsigned long) 0x05) << 17; | |
412 | break; | |
413 | case 0x10000000: | |
414 | tmp |= ((unsigned long) 0x06) << 17; | |
415 | break; | |
416 | default: | |
417 | SDRAM_err ("unsupported SDRAM"); | |
418 | } /* endswitch */ | |
419 | /* get SDRAM bank 0 register */ | |
420 | mtdcr (memcfga, mem_mb0cf); | |
421 | bank = mfdcr (memcfgd) & ~0xFFCEE001; | |
422 | bank |= (baseaddr | tmp | 0x01); | |
423 | #ifdef SDRAM_DEBUG | |
424 | serial_puts ("bank0: baseaddr: "); | |
425 | write_4hex (baseaddr); | |
426 | serial_puts (" banksize: "); | |
427 | write_4hex (bank_size); | |
428 | serial_puts (" mb0cf: "); | |
429 | write_4hex (bank); | |
430 | serial_puts ("\n"); | |
431 | #endif | |
432 | baseaddr += bank_size; | |
433 | sdram_size += bank_size; | |
434 | ||
435 | /* write SDRAM bank 0 register */ | |
436 | mtdcr (memcfga, mem_mb0cf); | |
437 | mtdcr (memcfgd, bank); | |
438 | ||
439 | /* get SDRAM bank 1 register */ | |
440 | mtdcr (memcfga, mem_mb1cf); | |
441 | bank = mfdcr (memcfgd) & ~0xFFCEE001; | |
442 | sdram_size = 0; | |
443 | ||
444 | #ifdef SDRAM_DEBUG | |
445 | serial_puts ("bank1: baseaddr: "); | |
446 | write_4hex (baseaddr); | |
447 | serial_puts (" banksize: "); | |
448 | write_4hex (bank_size); | |
449 | #endif | |
450 | if (banks == 2) { | |
451 | bank |= (baseaddr | tmp | 0x01); | |
452 | baseaddr += bank_size; | |
453 | sdram_size += bank_size; | |
454 | } /* endif */ | |
455 | #ifdef SDRAM_DEBUG | |
456 | serial_puts (" mb1cf: "); | |
457 | write_4hex (bank); | |
458 | serial_puts ("\n"); | |
459 | #endif | |
460 | /* write SDRAM bank 1 register */ | |
461 | mtdcr (memcfga, mem_mb1cf); | |
462 | mtdcr (memcfgd, bank); | |
463 | ||
464 | /* get SDRAM bank 2 register */ | |
465 | mtdcr (memcfga, mem_mb2cf); | |
466 | bank = mfdcr (memcfgd) & ~0xFFCEE001; | |
467 | ||
468 | bank |= (baseaddr | tmp | 0x01); | |
469 | ||
470 | #ifdef SDRAM_DEBUG | |
471 | serial_puts ("bank2: baseaddr: "); | |
472 | write_4hex (baseaddr); | |
473 | serial_puts (" banksize: "); | |
474 | write_4hex (bank_size); | |
475 | serial_puts (" mb2cf: "); | |
476 | write_4hex (bank); | |
477 | serial_puts ("\n"); | |
478 | #endif | |
479 | ||
480 | baseaddr += bank_size; | |
481 | sdram_size += bank_size; | |
482 | ||
483 | /* write SDRAM bank 2 register */ | |
484 | mtdcr (memcfga, mem_mb2cf); | |
485 | mtdcr (memcfgd, bank); | |
486 | ||
487 | /* get SDRAM bank 3 register */ | |
488 | mtdcr (memcfga, mem_mb3cf); | |
489 | bank = mfdcr (memcfgd) & ~0xFFCEE001; | |
490 | ||
491 | #ifdef SDRAM_DEBUG | |
492 | serial_puts ("bank3: baseaddr: "); | |
493 | write_4hex (baseaddr); | |
494 | serial_puts (" banksize: "); | |
495 | write_4hex (bank_size); | |
496 | #endif | |
497 | ||
498 | if (banks == 2) { | |
499 | bank |= (baseaddr | tmp | 0x01); | |
500 | baseaddr += bank_size; | |
501 | sdram_size += bank_size; | |
502 | } | |
503 | /* endif */ | |
504 | #ifdef SDRAM_DEBUG | |
505 | serial_puts (" mb3cf: "); | |
506 | write_4hex (bank); | |
507 | serial_puts ("\n"); | |
508 | #endif | |
509 | ||
510 | /* write SDRAM bank 3 register */ | |
511 | mtdcr (memcfga, mem_mb3cf); | |
512 | mtdcr (memcfgd, bank); | |
513 | ||
514 | ||
515 | /* get SDRAM refresh interval register */ | |
516 | mtdcr (memcfga, mem_rtr); | |
517 | tmp = mfdcr (memcfgd) & ~0x3FF80000; | |
518 | ||
519 | if (tmemclk < NSto10PS (16)) | |
520 | tmp |= 0x05F00000; | |
521 | else | |
522 | tmp |= 0x03F80000; | |
523 | ||
524 | /* write SDRAM refresh interval register */ | |
525 | mtdcr (memcfga, mem_rtr); | |
526 | mtdcr (memcfgd, tmp); | |
527 | ||
528 | /* enable SDRAM controller with no ECC, 32-bit SDRAM width, 16 byte burst */ | |
529 | mtdcr (memcfga, mem_mcopt1); | |
530 | tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80E00000; | |
531 | mtdcr (memcfga, mem_mcopt1); | |
532 | mtdcr (memcfgd, tmp); | |
533 | ||
534 | ||
7d393aed WD |
535 | /*-------------------------------------------------------------------------+ |
536 | | Interrupt controller setup for the PIP405 board. | |
537 | | Note: IRQ 0-15 405GP internally generated; active high; level sensitive | |
538 | | IRQ 16 405GP internally generated; active low; level sensitive | |
539 | | IRQ 17-24 RESERVED | |
540 | | IRQ 25 (EXT IRQ 0) SouthBridg; active low; level sensitive | |
541 | | IRQ 26 (EXT IRQ 1) NMI: active low; level sensitive | |
542 | | IRQ 27 (EXT IRQ 2) SMI: active Low; level sensitive | |
543 | | IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive | |
544 | | IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive | |
545 | | IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive | |
546 | | IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive | |
547 | | Note for PIP405 board: | |
548 | | An interrupt taken for the SouthBridge (IRQ 25) indicates that | |
549 | | the Interrupt Controller in the South Bridge has caused the | |
550 | | interrupt. The IC must be read to determine which device | |
551 | | caused the interrupt. | |
552 | | | |
553 | +-------------------------------------------------------------------------*/ | |
554 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ | |
555 | mtdcr (uicer, 0x00000000); /* disable all ints */ | |
556 | mtdcr (uiccr, 0x00000000); /* set all to be non-critical (for now) */ | |
557 | mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ | |
558 | mtdcr (uictr, 0x10000000); /* set int trigger levels */ | |
559 | mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */ | |
560 | mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ | |
561 | ||
562 | return 0; | |
563 | } | |
564 | ||
565 | ||
566 | /* ------------------------------------------------------------------------- */ | |
567 | ||
568 | /* | |
569 | * Check Board Identity: | |
570 | */ | |
571 | ||
572 | int checkboard (void) | |
573 | { | |
77ddac94 | 574 | char s[50]; |
7d393aed WD |
575 | unsigned char bc; |
576 | int i; | |
577 | backup_t *b = (backup_t *) s; | |
578 | ||
579 | puts ("Board: "); | |
580 | ||
77ddac94 WD |
581 | i = getenv_r ("serial#", (char *)s, 32); |
582 | if ((i == 0) || strncmp ((char *)s, "PIP405", 6)) { | |
7d393aed WD |
583 | get_backup_values (b); |
584 | if (strncmp (b->signature, "MPL\0", 4) != 0) { | |
585 | puts ("### No HW ID - assuming PIP405"); | |
586 | } else { | |
587 | b->serial_name[6] = 0; | |
588 | printf ("%s SN: %s", b->serial_name, | |
589 | &b->serial_name[7]); | |
590 | } | |
591 | } else { | |
592 | s[6] = 0; | |
593 | printf ("%s SN: %s", s, &s[7]); | |
594 | } | |
595 | bc = in8 (CONFIG_PORT_ADDR); | |
596 | printf (" Boot Config: 0x%x\n", bc); | |
597 | return (0); | |
598 | } | |
599 | ||
600 | ||
601 | /* ------------------------------------------------------------------------- */ | |
602 | /* ------------------------------------------------------------------------- */ | |
603 | /* | |
604 | initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of | |
605 | the necessary info for SDRAM controller configuration | |
606 | */ | |
607 | /* ------------------------------------------------------------------------- */ | |
608 | /* ------------------------------------------------------------------------- */ | |
609 | static int test_dram (unsigned long ramsize); | |
610 | ||
9973e3c6 | 611 | phys_size_t initdram (int board_type) |
7d393aed | 612 | { |
7d393aed WD |
613 | unsigned long bank_reg[4], tmp, bank_size; |
614 | int i, ds; | |
615 | unsigned long TotalSize; | |
616 | ||
617 | ds = 0; | |
618 | /* since the DRAM controller is allready set up, | |
619 | * calculate the size with the bank registers | |
620 | */ | |
621 | mtdcr (memcfga, mem_mb0cf); | |
622 | bank_reg[0] = mfdcr (memcfgd); | |
623 | mtdcr (memcfga, mem_mb1cf); | |
624 | bank_reg[1] = mfdcr (memcfgd); | |
625 | mtdcr (memcfga, mem_mb2cf); | |
626 | bank_reg[2] = mfdcr (memcfgd); | |
627 | mtdcr (memcfga, mem_mb3cf); | |
628 | bank_reg[3] = mfdcr (memcfgd); | |
629 | TotalSize = 0; | |
630 | for (i = 0; i < 4; i++) { | |
631 | if ((bank_reg[i] & 0x1) == 0x1) { | |
632 | tmp = (bank_reg[i] >> 17) & 0x7; | |
633 | bank_size = 4 << tmp; | |
634 | TotalSize += bank_size; | |
635 | } else | |
636 | ds = 1; | |
637 | } | |
638 | if (ds == 1) | |
639 | printf ("single-sided DIMM "); | |
640 | else | |
641 | printf ("double-sided DIMM "); | |
642 | test_dram (TotalSize * 1024 * 1024); | |
643 | /* bank 2 (SDRAM Clock 2) is not usable if 133MHz SDRAM IF */ | |
644 | (void) get_clocks(); | |
645 | if (gd->cpu_clk > 220000000) | |
646 | TotalSize /= 2; | |
647 | return (TotalSize * 1024 * 1024); | |
648 | } | |
649 | ||
650 | /* ------------------------------------------------------------------------- */ | |
651 | ||
652 | ||
653 | static int test_dram (unsigned long ramsize) | |
654 | { | |
655 | /* not yet implemented */ | |
656 | return (1); | |
657 | } | |
658 | ||
659 | ||
7205e407 WD |
660 | extern flash_info_t flash_info[]; /* info for FLASH chips */ |
661 | ||
7d393aed WD |
662 | int misc_init_r (void) |
663 | { | |
7205e407 WD |
664 | /* adjust flash start and size as well as the offset */ |
665 | gd->bd->bi_flashstart=0-flash_info[0].size; | |
6d0f6bcf | 666 | gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN; |
7205e407 WD |
667 | gd->bd->bi_flashoffset=0; |
668 | ||
669 | /* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */ | |
670 | if (mfdcr(strap) & PSR_ROM_LOC) | |
671 | mtspr(ccr0, (mfspr(ccr0) & ~0x80)); | |
672 | ||
7d393aed WD |
673 | return (0); |
674 | } | |
675 | ||
676 | /*************************************************************************** | |
677 | * some helping routines | |
678 | */ | |
679 | ||
680 | int overwrite_console (void) | |
681 | { | |
682 | return (in8 (CONFIG_PORT_ADDR) & 0x1); /* return TRUE if console should be overwritten */ | |
683 | } | |
684 | ||
685 | ||
7d393aed WD |
686 | extern int isa_init (void); |
687 | ||
688 | ||
689 | void print_pip405_rev (void) | |
690 | { | |
691 | unsigned char part, vers, cfg; | |
692 | ||
693 | part = in8 (PLD_PART_REG); | |
694 | vers = in8 (PLD_VERS_REG); | |
695 | cfg = in8 (PLD_BOARD_CFG_REG); | |
696 | printf ("Rev: PIP405-%d Rev %c PLD%d %d PLD%d %d\n", | |
697 | 16 - ((cfg >> 4) & 0xf), (cfg & 0xf) + 'A', part & 0xf, | |
698 | vers & 0xf, (part >> 4) & 0xf, (vers >> 4) & 0xf); | |
699 | } | |
700 | ||
701 | extern void check_env(void); | |
702 | ||
703 | ||
704 | int last_stage_init (void) | |
705 | { | |
706 | print_pip405_rev (); | |
707 | isa_init (); | |
708 | show_stdio_dev (); | |
709 | check_env(); | |
710 | return 0; | |
711 | } | |
712 | ||
713 | /************************************************************************ | |
714 | * Print PIP405 Info | |
715 | ************************************************************************/ | |
716 | void print_pip405_info (void) | |
717 | { | |
718 | unsigned char part, vers, cfg, ledu, sysman, flashcom, can, serpwr, | |
719 | compwr, nicvga, scsirst; | |
720 | ||
721 | part = in8 (PLD_PART_REG); | |
722 | vers = in8 (PLD_VERS_REG); | |
723 | cfg = in8 (PLD_BOARD_CFG_REG); | |
724 | ledu = in8 (PLD_LED_USER_REG); | |
725 | sysman = in8 (PLD_SYS_MAN_REG); | |
726 | flashcom = in8 (PLD_FLASH_COM_REG); | |
727 | can = in8 (PLD_CAN_REG); | |
728 | serpwr = in8 (PLD_SER_PWR_REG); | |
729 | compwr = in8 (PLD_COM_PWR_REG); | |
730 | nicvga = in8 (PLD_NIC_VGA_REG); | |
731 | scsirst = in8 (PLD_SCSI_RST_REG); | |
732 | printf ("PLD Part %d version %d\n", | |
733 | part & 0xf, vers & 0xf); | |
734 | printf ("PLD Part %d version %d\n", | |
735 | (part >> 4) & 0xf, (vers >> 4) & 0xf); | |
736 | printf ("Board Revision %c\n", (cfg & 0xf) + 'A'); | |
737 | printf ("Population Options %d %d %d %d\n", | |
738 | (cfg >> 4) & 0x1, (cfg >> 5) & 0x1, | |
739 | (cfg >> 6) & 0x1, (cfg >> 7) & 0x1); | |
740 | printf ("User LED0 %s User LED1 %s\n", | |
741 | ((ledu & 0x1) == 0x1) ? "on" : "off", | |
742 | ((ledu & 0x2) == 0x2) ? "on" : "off"); | |
743 | printf ("Additionally Options %d %d\n", | |
744 | (ledu >> 2) & 0x1, (ledu >> 3) & 0x1); | |
745 | printf ("User Config Switch %d %d %d %d\n", | |
746 | (ledu >> 4) & 0x1, (ledu >> 5) & 0x1, | |
747 | (ledu >> 6) & 0x1, (ledu >> 7) & 0x1); | |
748 | switch (sysman & 0x3) { | |
749 | case 0: | |
750 | printf ("PCI Clocks are running\n"); | |
751 | break; | |
752 | case 1: | |
753 | printf ("PCI Clocks are stopped in POS State\n"); | |
754 | break; | |
755 | case 2: | |
756 | printf ("PCI Clocks are stopped when PCI_STP# is asserted\n"); | |
757 | break; | |
758 | case 3: | |
759 | printf ("PCI Clocks are stopped\n"); | |
760 | break; | |
761 | } | |
762 | switch ((sysman >> 2) & 0x3) { | |
763 | case 0: | |
764 | printf ("Main Clocks are running\n"); | |
765 | break; | |
766 | case 1: | |
767 | printf ("Main Clocks are stopped in POS State\n"); | |
768 | break; | |
769 | case 2: | |
770 | case 3: | |
771 | printf ("PCI Clocks are stopped\n"); | |
772 | break; | |
773 | } | |
774 | printf ("INIT asserts %sINT2# (SMI)\n", | |
775 | ((sysman & 0x10) == 0x10) ? "" : "not "); | |
776 | printf ("INIT asserts %sINT1# (NMI)\n", | |
777 | ((sysman & 0x20) == 0x20) ? "" : "not "); | |
778 | printf ("INIT occured %d\n", (sysman >> 6) & 0x1); | |
779 | printf ("SER1 is routed to %s\n", | |
780 | ((flashcom & 0x1) == 0x1) ? "RS485" : "RS232"); | |
781 | printf ("COM2 is routed to %s\n", | |
782 | ((flashcom & 0x2) == 0x2) ? "RS485" : "RS232"); | |
783 | printf ("RS485 is configured as %s duplex\n", | |
784 | ((flashcom & 0x4) == 0x4) ? "full" : "half"); | |
785 | printf ("RS485 is connected to %s\n", | |
786 | ((flashcom & 0x8) == 0x8) ? "COM1" : "COM2"); | |
787 | printf ("SER1 uses handshakes %s\n", | |
788 | ((flashcom & 0x10) == 0x10) ? "DTR/DSR" : "RTS/CTS"); | |
789 | printf ("Bootflash is %swriteprotected\n", | |
790 | ((flashcom & 0x20) == 0x20) ? "not " : ""); | |
791 | printf ("Bootflash VPP is %s\n", | |
792 | ((flashcom & 0x40) == 0x40) ? "on" : "off"); | |
793 | printf ("Bootsector is %swriteprotected\n", | |
794 | ((flashcom & 0x80) == 0x80) ? "not " : ""); | |
795 | switch ((can) & 0x3) { | |
796 | case 0: | |
797 | printf ("CAN Controller is on address 0x1000..0x10FF\n"); | |
798 | break; | |
799 | case 1: | |
800 | printf ("CAN Controller is on address 0x8000..0x80FF\n"); | |
801 | break; | |
802 | case 2: | |
803 | printf ("CAN Controller is on address 0xE000..0xE0FF\n"); | |
804 | break; | |
805 | case 3: | |
806 | printf ("CAN Controller is disabled\n"); | |
807 | break; | |
808 | } | |
809 | switch ((can >> 2) & 0x3) { | |
810 | case 0: | |
811 | printf ("CAN Controller Reset is ISA Reset\n"); | |
812 | break; | |
813 | case 1: | |
814 | printf ("CAN Controller Reset is ISA Reset and POS State\n"); | |
815 | break; | |
816 | case 2: | |
817 | case 3: | |
818 | printf ("CAN Controller is in reset\n"); | |
819 | break; | |
820 | } | |
821 | if (((can >> 4) < 3) || ((can >> 4) == 8) || ((can >> 4) == 13)) | |
822 | printf ("CAN Interrupt is disabled\n"); | |
823 | else | |
824 | printf ("CAN Interrupt is ISA INT%d\n", (can >> 4) & 0xf); | |
825 | switch (serpwr & 0x3) { | |
826 | case 0: | |
827 | printf ("SER0 Drivers are enabled\n"); | |
828 | break; | |
829 | case 1: | |
830 | printf ("SER0 Drivers are disabled in the POS state\n"); | |
831 | break; | |
832 | case 2: | |
833 | case 3: | |
834 | printf ("SER0 Drivers are disabled\n"); | |
835 | break; | |
836 | } | |
837 | switch ((serpwr >> 2) & 0x3) { | |
838 | case 0: | |
839 | printf ("SER1 Drivers are enabled\n"); | |
840 | break; | |
841 | case 1: | |
842 | printf ("SER1 Drivers are disabled in the POS state\n"); | |
843 | break; | |
844 | case 2: | |
845 | case 3: | |
846 | printf ("SER1 Drivers are disabled\n"); | |
847 | break; | |
848 | } | |
849 | switch (compwr & 0x3) { | |
850 | case 0: | |
851 | printf ("COM1 Drivers are enabled\n"); | |
852 | break; | |
853 | case 1: | |
854 | printf ("COM1 Drivers are disabled in the POS state\n"); | |
855 | break; | |
856 | case 2: | |
857 | case 3: | |
858 | printf ("COM1 Drivers are disabled\n"); | |
859 | break; | |
860 | } | |
861 | switch ((compwr >> 2) & 0x3) { | |
862 | case 0: | |
863 | printf ("COM2 Drivers are enabled\n"); | |
864 | break; | |
865 | case 1: | |
866 | printf ("COM2 Drivers are disabled in the POS state\n"); | |
867 | break; | |
868 | case 2: | |
869 | case 3: | |
870 | printf ("COM2 Drivers are disabled\n"); | |
871 | break; | |
872 | } | |
873 | switch ((nicvga) & 0x3) { | |
874 | case 0: | |
875 | printf ("PHY is running\n"); | |
876 | break; | |
877 | case 1: | |
878 | printf ("PHY is in Power save mode in POS state\n"); | |
879 | break; | |
880 | case 2: | |
881 | case 3: | |
882 | printf ("PHY is in Power save mode\n"); | |
883 | break; | |
884 | } | |
885 | switch ((nicvga >> 2) & 0x3) { | |
886 | case 0: | |
887 | printf ("VGA is running\n"); | |
888 | break; | |
889 | case 1: | |
890 | printf ("VGA is in Power save mode in POS state\n"); | |
891 | break; | |
892 | case 2: | |
893 | case 3: | |
894 | printf ("VGA is in Power save mode\n"); | |
895 | break; | |
896 | } | |
897 | printf ("PHY is %sreseted\n", ((nicvga & 0x10) == 0x10) ? "" : "not "); | |
898 | printf ("VGA is %sreseted\n", ((nicvga & 0x20) == 0x20) ? "" : "not "); | |
899 | printf ("Reserved Configuration is %d %d\n", (nicvga >> 6) & 0x1, | |
900 | (nicvga >> 7) & 0x1); | |
901 | switch ((scsirst) & 0x3) { | |
902 | case 0: | |
903 | printf ("SCSI Controller is running\n"); | |
904 | break; | |
905 | case 1: | |
906 | printf ("SCSI Controller is in Power save mode in POS state\n"); | |
907 | break; | |
908 | case 2: | |
909 | case 3: | |
910 | printf ("SCSI Controller is in Power save mode\n"); | |
911 | break; | |
912 | } | |
913 | printf ("SCSI termination is %s\n", | |
914 | ((scsirst & 0x4) == 0x4) ? "disabled" : "enabled"); | |
915 | printf ("SCSI Controller is %sreseted\n", | |
916 | ((scsirst & 0x10) == 0x10) ? "" : "not "); | |
917 | printf ("IDE disks are %sreseted\n", | |
918 | ((scsirst & 0x20) == 0x20) ? "" : "not "); | |
919 | printf ("ISA Bus is %sreseted\n", | |
920 | ((scsirst & 0x40) == 0x40) ? "" : "not "); | |
921 | printf ("Super IO is %sreseted\n", | |
922 | ((scsirst & 0x80) == 0x80) ? "" : "not "); | |
923 | } | |
924 | ||
925 | void user_led0 (unsigned char on) | |
926 | { | |
927 | if (on == TRUE) | |
928 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x1)); | |
929 | else | |
930 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfe)); | |
931 | } | |
932 | ||
933 | void user_led1 (unsigned char on) | |
934 | { | |
935 | if (on == TRUE) | |
936 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) | 0x2)); | |
937 | else | |
938 | out8 (PLD_LED_USER_REG, (in8 (PLD_LED_USER_REG) & 0xfd)); | |
939 | } | |
940 | ||
941 | void ide_set_reset (int idereset) | |
942 | { | |
943 | /* if reset = 1 IDE reset will be asserted */ | |
944 | unsigned char resreg; | |
945 | ||
946 | resreg = in8 (PLD_SCSI_RST_REG); | |
947 | if (idereset == 1) | |
948 | resreg |= 0x20; | |
949 | else { | |
950 | udelay(10000); | |
951 | resreg &= 0xdf; | |
952 | } | |
953 | out8 (PLD_SCSI_RST_REG, resreg); | |
954 | } |