projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| c8f3402a MW |
1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* | |
| 3 | * Based on vendor support provided by AVNET Embedded | |
| 4 | * | |
| 5 | * Copyright (C) 2021 AVNET Embedded, MSC Technologies GmbH | |
| 6 | * Copyright 2021 General Electric Company | |
| 7 | * Copyright 2021 Collabora Ltd. | |
| 8 | */ | |
| 9 | ||
| d678a59d | 10 | #include <common.h> |
| c8f3402a MW |
11 | #include <errno.h> |
| 12 | #include <miiphy.h> | |
| 13 | #include <netdev.h> | |
| 14 | #include <asm/arch/clock.h> | |
| 15 | #include <asm/arch/imx8mp_pins.h> | |
| 16 | #include <asm/arch/sys_proto.h> | |
| 17 | #include <asm/mach-imx/gpio.h> | |
| 18 | #include <asm/mach-imx/iomux-v3.h> | |
| 19 | #include <asm-generic/gpio.h> | |
| 20 | #include <linux/delay.h> | |
| 21 | ||
| 22 | DECLARE_GLOBAL_DATA_PTR; | |
| 23 | ||
| 24 | static void setup_fec(void) | |
| 25 | { | |
| 26 | struct iomuxc_gpr_base_regs *gpr = | |
| 27 | (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; | |
| 28 | ||
| 29 | /* Enable RGMII TX clk output */ | |
| 30 | setbits_le32(&gpr->gpr[1], BIT(22)); | |
| 31 | } | |
| 32 | ||
| c8f3402a MW |
33 | int board_phy_config(struct phy_device *phydev) |
| 34 | { | |
| 35 | if (phydev->drv->config) | |
| 36 | phydev->drv->config(phydev); | |
| 37 | return 0; | |
| 38 | } | |
| 39 | ||
| 40 | int board_init(void) | |
| 41 | { | |
| 42 | setup_fec(); | |
| 43 | ||
| c8f3402a MW |
44 | return 0; |
| 45 | } |