[thirdparty/u-boot.git] / board / mscc / common / spi.c

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (c) 2018 Microsemi Coprporation
 */

#include <common.h>
#include <asm/io.h>
#include <spi.h>
#include <linux/bitops.h>

void external_cs_manage(struct udevice *dev, bool enable)
{
	u32 cs = spi_chip_select(dev);
	/* IF_SI0_OWNER, select the owner of the SI interface
	 * Encoding: 0: SI Slave
	 *	     1: SI Boot Master
	 *	     2: SI Master Controller
	 */
	if (!enable) {
		writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
		       ICPU_SW_MODE_SW_SPI_CS(BIT(cs)),
		       BASE_CFG + ICPU_SW_MODE);
		clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
				ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
				ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
	} else {
		writel(0, BASE_CFG + ICPU_SW_MODE);
		clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
				ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
				ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
	}
}
Commit	Line	Data
c75c9083 HV	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Copyright (c) 2018 Microsemi Coprporation
	4	*/
	5
d678a59d	6	#include <common.h>
c75c9083 HV	7	#include <asm/io.h>
c75c9083 HV	8	#include <spi.h>
cd93d625	9	#include <linux/bitops.h>
c75c9083 HV	10
	11	void external_cs_manage(struct udevice *dev, bool enable)
	12	{
	13	u32 cs = spi_chip_select(dev);
	14	/* IF_SI0_OWNER, select the owner of the SI interface
	15	* Encoding: 0: SI Slave
	16	* 1: SI Boot Master
	17	* 2: SI Master Controller
	18	*/
	19	if (!enable) {
	20	writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE \|
	21	ICPU_SW_MODE_SW_SPI_CS(BIT(cs)),
	22	BASE_CFG + ICPU_SW_MODE);
	23	clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
	24	ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
	25	ICPU_GENERAL_CTRL_IF_SI_OWNER(2));
	26	} else {
	27	writel(0, BASE_CFG + ICPU_SW_MODE);
	28	clrsetbits_le32(BASE_CFG + ICPU_GENERAL_CTRL,
	29	ICPU_GENERAL_CTRL_IF_SI_OWNER_M,
	30	ICPU_GENERAL_CTRL_IF_SI_OWNER(1));
	31	}
	32	}