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adf22b66 HS |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <mpc8260.h> | |
26 | #include <ioports.h> | |
27 | ||
28 | #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) | |
29 | #include <libfdt.h> | |
30 | #endif | |
31 | ||
32 | /* | |
33 | * I/O Port configuration table | |
34 | * | |
35 | * if conf is 1, then that port pin will be configured at boot time | |
36 | * according to the five values podr/pdir/ppar/psor/pdat for that entry | |
37 | */ | |
38 | const iop_conf_t iop_conf_tab[4][32] = { | |
39 | ||
40 | /* Port A */ | |
41 | { /* conf ppar psor pdir podr pdat */ | |
42 | /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */ | |
43 | /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */ | |
44 | /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ | |
45 | /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ | |
46 | /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ | |
47 | /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ | |
48 | /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* ETH_PWRDWN */ | |
49 | /* PA24 */ { 1, 0, 0, 1, 0, 1 }, /* ETH_RESET */ | |
50 | /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ | |
51 | /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ | |
52 | /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ | |
53 | /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ | |
54 | /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ | |
55 | /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ | |
56 | /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ | |
57 | /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ | |
58 | /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ | |
59 | /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ | |
60 | /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ | |
61 | /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* ETH_SLEEP */ | |
62 | /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ | |
63 | /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* MDIO */ | |
64 | /* PA9 */ { 1, 0, 0, 1, 0, 0 }, /* MDC */ | |
65 | /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ | |
66 | /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ | |
67 | /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ | |
68 | /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ | |
69 | /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ | |
70 | /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ | |
71 | /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ | |
72 | /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ | |
73 | /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ | |
74 | }, | |
75 | ||
76 | /* Port B */ | |
77 | { /* conf ppar psor pdir podr pdat */ | |
78 | /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */ | |
79 | /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */ | |
80 | /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */ | |
81 | /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ | |
82 | /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */ | |
83 | /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */ | |
84 | /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */ | |
85 | /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */ | |
86 | /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */ | |
87 | /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */ | |
88 | /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */ | |
89 | /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */ | |
90 | /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */ | |
91 | /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */ | |
92 | /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
93 | /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
94 | /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ | |
95 | /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RxD */ | |
96 | /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
97 | /* PB12 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */ | |
98 | /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
99 | /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
100 | /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
101 | /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TxD */ | |
102 | /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
103 | /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
104 | /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
105 | /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
106 | /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
107 | /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
108 | /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
109 | /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ | |
110 | }, | |
111 | ||
112 | /* Port C */ | |
113 | { /* conf ppar psor pdir podr pdat */ | |
114 | /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ | |
115 | /* PC30 */ { 1, 1, 1, 1, 0, 0 }, /* Timer1 OUT */ | |
116 | /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ | |
117 | /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ | |
118 | /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ | |
119 | /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ | |
120 | /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ | |
121 | /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ | |
122 | /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ | |
123 | /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ | |
124 | /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC RxCLK 11 */ | |
125 | /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC TxCLK 12 */ | |
126 | /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ | |
127 | /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */ | |
128 | /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ | |
129 | /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ | |
130 | /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ | |
131 | /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ | |
132 | /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ | |
133 | /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* TX OUTPUT SLEW1 */ | |
134 | /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* TX OUTPUT SLEW0 */ | |
135 | /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ | |
136 | /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* SPA_TX_EN */ | |
137 | /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ | |
138 | /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ | |
139 | /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ | |
140 | /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ | |
141 | /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ | |
142 | /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ | |
143 | /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ | |
144 | /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ | |
145 | /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ | |
146 | }, | |
147 | ||
148 | /* Port D */ | |
149 | { /* conf ppar psor pdir podr pdat */ | |
150 | /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ | |
151 | /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ | |
152 | /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ | |
153 | /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ | |
154 | /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ | |
155 | /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ | |
156 | /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ | |
157 | /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ | |
158 | /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ | |
159 | /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */ | |
160 | /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */ | |
161 | /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ | |
162 | /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ | |
163 | /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ | |
164 | /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ | |
165 | /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ | |
0b7c5639 HS |
166 | #if defined(CONFIG_HARD_I2C) |
167 | /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */ | |
168 | /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */ | |
169 | #else | |
170 | /* PD15 */ { 1, 0, 0, 0, 1, 1 }, /* PD15 */ | |
171 | /* PD14 */ { 1, 0, 0, 1, 1, 1 }, /* PD14 */ | |
172 | #endif | |
adf22b66 HS |
173 | /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ |
174 | /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ | |
175 | /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ | |
176 | /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ | |
177 | /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ | |
178 | /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ | |
179 | /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ | |
180 | /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ | |
181 | /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ | |
182 | /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ | |
183 | /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
184 | /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
185 | /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ | |
186 | /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ | |
187 | } | |
188 | }; | |
189 | ||
190 | /* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx | |
191 | * | |
192 | * This routine performs standard 8260 initialization sequence | |
193 | * and calculates the available memory size. It may be called | |
194 | * several times to try different SDRAM configurations on both | |
195 | * 60x and local buses. | |
196 | */ | |
197 | static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, | |
198 | ulong orx, volatile uchar * base) | |
199 | { | |
200 | volatile uchar c = 0xff; | |
201 | volatile uint *sdmr_ptr; | |
202 | volatile uint *orx_ptr; | |
203 | ulong maxsize, size; | |
204 | int i; | |
205 | ||
206 | /* We must be able to test a location outsize the maximum legal size | |
207 | * to find out THAT we are outside; but this address still has to be | |
208 | * mapped by the controller. That means, that the initial mapping has | |
209 | * to be (at least) twice as large as the maximum expected size. | |
210 | */ | |
211 | maxsize = (1 + (~orx | 0x7fff))/* / 2*/; | |
212 | ||
213 | sdmr_ptr = &memctl->memc_psdmr; | |
214 | orx_ptr = &memctl->memc_or1; | |
215 | ||
216 | *orx_ptr = orx; | |
217 | ||
218 | /* | |
219 | * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): | |
220 | * | |
221 | * "At system reset, initialization software must set up the | |
222 | * programmable parameters in the memory controller banks registers | |
223 | * (ORx, BRx, P/LSDMR). After all memory parameters are configured, | |
224 | * system software should execute the following initialization sequence | |
225 | * for each SDRAM device. | |
226 | * | |
227 | * 1. Issue a PRECHARGE-ALL-BANKS command | |
228 | * 2. Issue eight CBR REFRESH commands | |
229 | * 3. Issue a MODE-SET command to initialize the mode register | |
230 | * | |
231 | * The initial commands are executed by setting P/LSDMR[OP] and | |
232 | * accessing the SDRAM with a single-byte transaction." | |
233 | * | |
234 | * The appropriate BRx/ORx registers have already been set when we | |
6d0f6bcf | 235 | * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE. |
adf22b66 HS |
236 | */ |
237 | ||
238 | *sdmr_ptr = sdmr | PSDMR_OP_PREA; | |
239 | *base = c; | |
240 | ||
241 | *sdmr_ptr = sdmr | PSDMR_OP_CBRR; | |
242 | for (i = 0; i < 8; i++) | |
243 | *base = c; | |
244 | ||
245 | *sdmr_ptr = sdmr | PSDMR_OP_MRW; | |
6d0f6bcf | 246 | *(base + CONFIG_SYS_MRS_OFFS) = c; /* setting MR on address lines */ |
adf22b66 HS |
247 | |
248 | *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; | |
249 | *base = c; | |
250 | ||
251 | size = get_ram_size ((long *)base, maxsize); | |
252 | *orx_ptr = orx | ~(size - 1); | |
253 | ||
254 | return (size); | |
255 | } | |
256 | ||
257 | phys_size_t initdram (int board_type) | |
258 | { | |
6d0f6bcf | 259 | volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; |
adf22b66 | 260 | volatile memctl8260_t *memctl = &immap->im_memctl; |
adf22b66 | 261 | long psize; |
6d0f6bcf | 262 | #ifndef CONFIG_SYS_RAMBOOT |
a55d074d HS |
263 | long sizelittle, sizebig; |
264 | #endif | |
adf22b66 | 265 | |
6d0f6bcf JCPV |
266 | memctl->memc_psrt = CONFIG_SYS_PSRT; |
267 | memctl->memc_mptpr = CONFIG_SYS_MPTPR; | |
adf22b66 | 268 | |
6d0f6bcf | 269 | #ifndef CONFIG_SYS_RAMBOOT |
adf22b66 HS |
270 | /* 60x SDRAM setup: |
271 | */ | |
6d0f6bcf JCPV |
272 | sizelittle = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE, |
273 | (uchar *) CONFIG_SYS_SDRAM_BASE); | |
274 | sizebig = try_init (memctl, CONFIG_SYS_PSDMR_BIG, CONFIG_SYS_OR1_BIG, | |
275 | (uchar *) CONFIG_SYS_SDRAM_BASE); | |
a55d074d HS |
276 | if (sizelittle < sizebig) { |
277 | psize = sizebig; | |
278 | } else { | |
6d0f6bcf JCPV |
279 | psize = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE, |
280 | (uchar *) CONFIG_SYS_SDRAM_BASE); | |
a55d074d | 281 | } |
6d0f6bcf | 282 | #endif /* CONFIG_SYS_RAMBOOT */ |
adf22b66 HS |
283 | |
284 | icache_enable (); | |
285 | ||
286 | return (psize); | |
287 | } | |
288 | ||
289 | int checkboard (void) | |
290 | { | |
291 | puts ("Board: MUAS3001\n"); | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
296 | /* | |
297 | * Early board initalization. | |
298 | */ | |
299 | int board_early_init_r (void) | |
300 | { | |
301 | return 0; | |
302 | } | |
303 | ||
304 | #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) | |
305 | /* | |
306 | * update "memory" property in the blob | |
307 | */ | |
308 | void ft_blob_update (void *blob, bd_t *bd) | |
309 | { | |
310 | int ret, nodeoffset = 0; | |
311 | ulong memory_data[2] = {0}; | |
312 | ulong flash_data[4] = {0}; | |
313 | ulong freq = 0; | |
314 | ulong speed = 0; | |
315 | ||
316 | memory_data[0] = cpu_to_be32 (bd->bi_memstart); | |
317 | memory_data[1] = cpu_to_be32 (bd->bi_memsize); | |
318 | ||
319 | nodeoffset = fdt_path_offset (blob, "/memory"); | |
320 | if (nodeoffset >= 0) { | |
321 | ret = fdt_setprop (blob, nodeoffset, "reg", memory_data, | |
322 | sizeof(memory_data)); | |
323 | if (ret < 0) | |
324 | printf ("ft_blob_update): cannot set /memory/reg " | |
325 | "property err:%s\n", fdt_strerror (ret)); | |
326 | } else { | |
327 | /* memory node is required in dts */ | |
328 | printf ("ft_blob_update(): cannot find /memory node " | |
329 | "err:%s\n", fdt_strerror(nodeoffset)); | |
330 | } | |
331 | /* update Flash addr, size */ | |
6d0f6bcf JCPV |
332 | flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE); |
333 | flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE); | |
adf22b66 HS |
334 | nodeoffset = fdt_path_offset (blob, "/localbus"); |
335 | if (nodeoffset >= 0) { | |
336 | ret = fdt_setprop (blob, nodeoffset, "ranges", flash_data, | |
337 | sizeof (flash_data)); | |
338 | if (ret < 0) | |
339 | printf ("ft_blob_update): cannot set /localbus/ranges " | |
340 | "property err:%s\n", fdt_strerror(ret)); | |
341 | } else { | |
342 | /* memory node is required in dts */ | |
343 | printf ("ft_blob_update(): cannot find /localbus node " | |
344 | "err:%s\n", fdt_strerror (nodeoffset)); | |
345 | } | |
346 | /* MAC Adresse */ | |
347 | nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet"); | |
348 | if (nodeoffset >= 0) { | |
349 | ret = fdt_setprop (blob, nodeoffset, "mac-address", bd->bi_enetaddr, | |
350 | sizeof (uchar) * 6); | |
351 | if (ret < 0) | |
352 | printf ("ft_blob_update): cannot set /soc/cpm/ethernet/mac-address " | |
353 | "property err:%s\n", fdt_strerror (ret)); | |
354 | } else { | |
355 | /* memory node is required in dts */ | |
356 | printf ("ft_blob_update(): cannot find /soc/cpm/ethernet node " | |
357 | "err:%s\n", fdt_strerror (nodeoffset)); | |
358 | } | |
359 | ||
360 | /* brg clock */ | |
361 | nodeoffset = fdt_path_offset (blob, "/soc/cpm/brg"); | |
362 | if (nodeoffset >= 0) { | |
363 | freq = cpu_to_be32 (bd->bi_brgfreq); | |
364 | ret = fdt_setprop (blob, nodeoffset, "clock-frequency", &freq, | |
365 | sizeof (unsigned long)); | |
366 | if (ret < 0) | |
367 | printf ("ft_blob_update): cannot set /soc/cpm/brg/clock-frequency " | |
368 | "property err:%s\n", fdt_strerror (ret)); | |
369 | } else { | |
370 | /* memory node is required in dts */ | |
371 | printf ("ft_blob_update(): cannot find /soc/cpm/brg/clock-frequency node " | |
372 | "err:%s\n", fdt_strerror (nodeoffset)); | |
373 | } | |
374 | ||
375 | /* baudrate */ | |
376 | nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial"); | |
377 | if (nodeoffset >= 0) { | |
378 | speed = cpu_to_be32 (bd->bi_baudrate); | |
379 | ret = fdt_setprop (blob, nodeoffset, "current-speed", &speed, | |
380 | sizeof (unsigned long)); | |
381 | if (ret < 0) | |
382 | printf ("ft_blob_update): cannot set /soc/cpm/serial/current-speed " | |
383 | "property err:%s\n", fdt_strerror (ret)); | |
384 | } else { | |
385 | /* baudrate is required in dts */ | |
386 | printf ("ft_blob_update(): cannot find /soc/cpm/smc2/current-speed node " | |
387 | "err:%s\n", fdt_strerror (nodeoffset)); | |
388 | } | |
389 | } | |
390 | ||
391 | void ft_board_setup (void *blob, bd_t *bd) | |
392 | { | |
393 | ft_cpu_setup (blob, bd); | |
394 | ft_blob_update (blob, bd); | |
395 | } | |
396 | #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ |