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CommitLineData
3f82b1d3
TW
1/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8#include <common.h>
9#include <ns16550.h>
c5b34a29 10#include <linux/compiler.h>
3f82b1d3 11#include <asm/io.h>
b4ba2be8 12#include <asm/arch/clock.h>
6d6c0bae 13#ifdef CONFIG_LCD
1b24a50b 14#include <asm/arch/display.h>
6d6c0bae 15#endif
c0720afb 16#include <asm/arch/funcmux.h>
3f82b1d3 17#include <asm/arch/pinmux.h>
8723626d 18#include <asm/arch/pmu.h>
6d6c0bae 19#ifdef CONFIG_PWM_TEGRA
e1ae0d1f 20#include <asm/arch/pwm.h>
6d6c0bae 21#endif
150c2493 22#include <asm/arch/tegra.h>
150c2493
TW
23#include <asm/arch-tegra/board.h>
24#include <asm/arch-tegra/clk_rst.h>
25#include <asm/arch-tegra/pmc.h>
26#include <asm/arch-tegra/sys_proto.h>
27#include <asm/arch-tegra/uart.h>
28#include <asm/arch-tegra/warmboot.h>
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29#ifdef CONFIG_TEGRA_CLOCK_SCALING
30#include <asm/arch/emc.h>
31#endif
32#ifdef CONFIG_USB_EHCI_TEGRA
7ae18f37 33#include <asm/arch-tegra/usb.h>
16297cfb 34#include <usb.h>
6d6c0bae 35#endif
c9aa831e 36#ifdef CONFIG_TEGRA_MMC
190be1f9 37#include <asm/arch-tegra/tegra_mmc.h>
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38#include <asm/arch-tegra/mmc.h>
39#endif
cb445fb4 40#include <i2c.h>
6d6c0bae 41#include <spi.h>
c5b34a29 42#include "emc.h"
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43
44DECLARE_GLOBAL_DATA_PTR;
45
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46const struct tegra_sysinfo sysinfo = {
47 CONFIG_TEGRA_BOARD_STRING
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48};
49
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SW
50void __pinmux_init(void)
51{
52}
53
54void pinmux_init(void) __attribute__((weak, alias("__pinmux_init")));
55
f10393e5
SG
56void __pin_mux_usb(void)
57{
58}
59
60void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb")));
61
e0284948
SW
62void __pin_mux_spi(void)
63{
64}
65
66void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
67
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68void __gpio_early_init_uart(void)
69{
70}
71
72void gpio_early_init_uart(void)
73__attribute__((weak, alias("__gpio_early_init_uart")));
74
dcd12518 75#if defined(CONFIG_TEGRA_NAND)
c0720afb
LS
76void __pin_mux_nand(void)
77{
78 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
79}
80
81void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
dcd12518 82#endif
c0720afb 83
716d9439
MD
84void __pin_mux_display(void)
85{
86}
87
88void pin_mux_display(void) __attribute__((weak, alias("__pin_mux_display")));
89
5aff021c
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90/*
91 * Routine: power_det_init
92 * Description: turn off power detects
93 */
94static void power_det_init(void)
95{
00a2749d 96#if defined(CONFIG_TEGRA20)
29f3e3f2 97 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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98
99 /* turn off power detects */
100 writel(0, &pmc->pmc_pwr_det_latch);
101 writel(0, &pmc->pmc_pwr_det);
102#endif
103}
104
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105/*
106 * Routine: board_init
107 * Description: Early hardware init.
108 */
109int board_init(void)
110{
c5b34a29
JZ
111 __maybe_unused int err;
112
a04eba99 113 /* Do clocks and UART first so that printf() works */
4ed59e70
SG
114 clock_init();
115 clock_verify();
116
78f47b73 117#ifdef CONFIG_FDT_SPI
e0284948 118 pin_mux_spi();
9112ef8d 119 spi_init();
e1ae0d1f 120#endif
b19f5749 121
e1ae0d1f
SG
122#ifdef CONFIG_PWM_TEGRA
123 if (pwm_init(gd->fdt_blob))
124 debug("%s: Failed to init pwm\n", __func__);
1b24a50b
SG
125#endif
126#ifdef CONFIG_LCD
716d9439 127 pin_mux_display();
1b24a50b 128 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
9112ef8d 129#endif
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130 /* boot param addr */
131 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
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132
133 power_det_init();
134
1f2ba722 135#ifdef CONFIG_SYS_I2C_TEGRA
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136#ifndef CONFIG_SYS_I2C_INIT_BOARD
137#error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards"
138#endif
139 i2c_init_board();
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140# ifdef CONFIG_TEGRA_PMU
141 if (pmu_set_nominal())
142 debug("Failed to select nominal voltages\n");
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143# ifdef CONFIG_TEGRA_CLOCK_SCALING
144 err = board_emc_init();
145 if (err)
146 debug("Memory controller init failed: %d\n", err);
147# endif
148# endif /* CONFIG_TEGRA_PMU */
1f2ba722 149#endif /* CONFIG_SYS_I2C_TEGRA */
3f82b1d3 150
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151#ifdef CONFIG_USB_EHCI_TEGRA
152 pin_mux_usb();
16297cfb 153 usb_process_devicetree(gd->fdt_blob);
f10393e5 154#endif
16297cfb 155
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156#ifdef CONFIG_LCD
157 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
158#endif
f10393e5 159
c0720afb
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160#ifdef CONFIG_TEGRA_NAND
161 pin_mux_nand();
162#endif
163
29f3e3f2 164#ifdef CONFIG_TEGRA_LP0
a49716aa
AM
165 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
166 warmboot_save_sdram_params();
167
67ac5797
SG
168 /* prepare the WB code to LP0 location */
169 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
170#endif
171
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172 return 0;
173}
21ef6a10 174
3e00dbdf 175#ifdef CONFIG_BOARD_EARLY_INIT_F
cb7a1cf3
TR
176static void __gpio_early_init(void)
177{
178}
179
180void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
181
3e00dbdf
SG
182int board_early_init_f(void)
183{
6d6c0bae 184 pinmux_init();
f46a9456 185 board_init_uart_f();
3e00dbdf
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186
187 /* Initialize periph GPIOs */
cb7a1cf3 188 gpio_early_init();
a04eba99 189 gpio_early_init_uart();
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190#ifdef CONFIG_LCD
191 tegra_lcd_early_init(gd->fdt_blob);
192#endif
0cd10c7a 193
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194 return 0;
195}
196#endif /* EARLY_INIT */
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197
198int board_late_init(void)
199{
200#ifdef CONFIG_LCD
201 /* Make sure we finish initing the LCD */
202 tegra_lcd_check_next_stage(gd->fdt_blob, 1);
203#endif
204 return 0;
205}
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206
207#if defined(CONFIG_TEGRA_MMC)
208void __pin_mux_mmc(void)
209{
210}
211
212void pin_mux_mmc(void) __attribute__((weak, alias("__pin_mux_mmc")));
213
214/* this is a weak define that we are overriding */
215int board_mmc_init(bd_t *bd)
216{
217 debug("%s called\n", __func__);
218
219 /* Enable muxes, etc. for SDMMC controllers */
220 pin_mux_mmc();
221
222 debug("%s: init MMC\n", __func__);
223 tegra_mmc_init();
224
225 return 0;
226}
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TW
227
228void pad_init_mmc(struct mmc_host *host)
229{
230#if defined(CONFIG_TEGRA30)
231 enum periph_id id = host->mmc_id;
232 u32 val;
233
234 debug("%s: sdmmc address = %08x, id = %d\n", __func__,
235 (unsigned int)host->reg, id);
236
237 /* Set the pad drive strength for SDMMC1 or 3 only */
238 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
239 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
240 __func__);
241 return;
242 }
243
244 val = readl(&host->reg->sdmemcmppadctl);
245 val &= 0xFFFFFFF0;
246 val |= MEMCOMP_PADCTRL_VREF;
247 writel(val, &host->reg->sdmemcmppadctl);
248
249 val = readl(&host->reg->autocalcfg);
250 val &= 0xFFFF0000;
251 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
252 writel(val, &host->reg->autocalcfg);
253#endif /* T30 */
254}
255#endif /* MMC */