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CommitLineData
3f82b1d3
TW
1/*
2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8#include <common.h>
9#include <ns16550.h>
c5b34a29 10#include <linux/compiler.h>
3f82b1d3 11#include <asm/io.h>
b4ba2be8 12#include <asm/arch/clock.h>
6d6c0bae 13#ifdef CONFIG_LCD
1b24a50b 14#include <asm/arch/display.h>
6d6c0bae 15#endif
c0720afb 16#include <asm/arch/funcmux.h>
3f82b1d3 17#include <asm/arch/pinmux.h>
8723626d 18#include <asm/arch/pmu.h>
6d6c0bae 19#ifdef CONFIG_PWM_TEGRA
e1ae0d1f 20#include <asm/arch/pwm.h>
6d6c0bae 21#endif
150c2493 22#include <asm/arch/tegra.h>
150c2493
TW
23#include <asm/arch-tegra/board.h>
24#include <asm/arch-tegra/clk_rst.h>
25#include <asm/arch-tegra/pmc.h>
26#include <asm/arch-tegra/sys_proto.h>
27#include <asm/arch-tegra/uart.h>
28#include <asm/arch-tegra/warmboot.h>
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TW
29#ifdef CONFIG_TEGRA_CLOCK_SCALING
30#include <asm/arch/emc.h>
31#endif
32#ifdef CONFIG_USB_EHCI_TEGRA
7ae18f37 33#include <asm/arch-tegra/usb.h>
7e44d932 34#include <asm/arch/usb.h>
16297cfb 35#include <usb.h>
6d6c0bae 36#endif
c9aa831e 37#ifdef CONFIG_TEGRA_MMC
190be1f9 38#include <asm/arch-tegra/tegra_mmc.h>
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39#include <asm/arch-tegra/mmc.h>
40#endif
cb445fb4 41#include <i2c.h>
6d6c0bae 42#include <spi.h>
c5b34a29 43#include "emc.h"
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44
45DECLARE_GLOBAL_DATA_PTR;
46
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47const struct tegra_sysinfo sysinfo = {
48 CONFIG_TEGRA_BOARD_STRING
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49};
50
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SG
51void __pin_mux_usb(void)
52{
53}
54
55void pin_mux_usb(void) __attribute__((weak, alias("__pin_mux_usb")));
56
e0284948
SW
57void __pin_mux_spi(void)
58{
59}
60
61void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
62
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63void __gpio_early_init_uart(void)
64{
65}
66
67void gpio_early_init_uart(void)
68__attribute__((weak, alias("__gpio_early_init_uart")));
69
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LS
70void __pin_mux_nand(void)
71{
72 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
73}
74
75void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
76
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MD
77void __pin_mux_display(void)
78{
79}
80
81void pin_mux_display(void) __attribute__((weak, alias("__pin_mux_display")));
82
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83/*
84 * Routine: power_det_init
85 * Description: turn off power detects
86 */
87static void power_det_init(void)
88{
00a2749d 89#if defined(CONFIG_TEGRA20)
29f3e3f2 90 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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91
92 /* turn off power detects */
93 writel(0, &pmc->pmc_pwr_det_latch);
94 writel(0, &pmc->pmc_pwr_det);
95#endif
96}
97
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98/*
99 * Routine: board_init
100 * Description: Early hardware init.
101 */
102int board_init(void)
103{
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104 __maybe_unused int err;
105
a04eba99 106 /* Do clocks and UART first so that printf() works */
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107 clock_init();
108 clock_verify();
109
78f47b73 110#ifdef CONFIG_FDT_SPI
e0284948 111 pin_mux_spi();
9112ef8d 112 spi_init();
e1ae0d1f 113#endif
b19f5749 114
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SG
115#ifdef CONFIG_PWM_TEGRA
116 if (pwm_init(gd->fdt_blob))
117 debug("%s: Failed to init pwm\n", __func__);
1b24a50b
SG
118#endif
119#ifdef CONFIG_LCD
716d9439 120 pin_mux_display();
1b24a50b 121 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
9112ef8d 122#endif
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123 /* boot param addr */
124 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
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125
126 power_det_init();
127
1f2ba722 128#ifdef CONFIG_SYS_I2C_TEGRA
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SG
129#ifndef CONFIG_SYS_I2C_INIT_BOARD
130#error "You must define CONFIG_SYS_I2C_INIT_BOARD to use i2c on Nvidia boards"
131#endif
132 i2c_init_board();
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133# ifdef CONFIG_TEGRA_PMU
134 if (pmu_set_nominal())
135 debug("Failed to select nominal voltages\n");
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JZ
136# ifdef CONFIG_TEGRA_CLOCK_SCALING
137 err = board_emc_init();
138 if (err)
139 debug("Memory controller init failed: %d\n", err);
140# endif
141# endif /* CONFIG_TEGRA_PMU */
1f2ba722 142#endif /* CONFIG_SYS_I2C_TEGRA */
3f82b1d3 143
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144#ifdef CONFIG_USB_EHCI_TEGRA
145 pin_mux_usb();
16297cfb 146 usb_process_devicetree(gd->fdt_blob);
f10393e5 147#endif
16297cfb 148
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149#ifdef CONFIG_LCD
150 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
151#endif
f10393e5 152
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153#ifdef CONFIG_TEGRA_NAND
154 pin_mux_nand();
155#endif
156
29f3e3f2 157#ifdef CONFIG_TEGRA_LP0
a49716aa
AM
158 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
159 warmboot_save_sdram_params();
160
67ac5797
SG
161 /* prepare the WB code to LP0 location */
162 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
163#endif
164
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165 return 0;
166}
21ef6a10 167
3e00dbdf 168#ifdef CONFIG_BOARD_EARLY_INIT_F
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TR
169static void __gpio_early_init(void)
170{
171}
172
173void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
174
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175int board_early_init_f(void)
176{
94829195 177#if !defined(CONFIG_TEGRA20)
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178 pinmux_init();
179#endif
f46a9456 180 board_init_uart_f();
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181
182 /* Initialize periph GPIOs */
cb7a1cf3 183 gpio_early_init();
a04eba99 184 gpio_early_init_uart();
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185#ifdef CONFIG_LCD
186 tegra_lcd_early_init(gd->fdt_blob);
187#endif
0cd10c7a 188
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189 return 0;
190}
191#endif /* EARLY_INIT */
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192
193int board_late_init(void)
194{
195#ifdef CONFIG_LCD
196 /* Make sure we finish initing the LCD */
197 tegra_lcd_check_next_stage(gd->fdt_blob, 1);
198#endif
199 return 0;
200}
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201
202#if defined(CONFIG_TEGRA_MMC)
203void __pin_mux_mmc(void)
204{
205}
206
207void pin_mux_mmc(void) __attribute__((weak, alias("__pin_mux_mmc")));
208
209/* this is a weak define that we are overriding */
210int board_mmc_init(bd_t *bd)
211{
212 debug("%s called\n", __func__);
213
214 /* Enable muxes, etc. for SDMMC controllers */
215 pin_mux_mmc();
216
217 debug("%s: init MMC\n", __func__);
218 tegra_mmc_init();
219
220 return 0;
221}
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TW
222
223void pad_init_mmc(struct mmc_host *host)
224{
225#if defined(CONFIG_TEGRA30)
226 enum periph_id id = host->mmc_id;
227 u32 val;
228
229 debug("%s: sdmmc address = %08x, id = %d\n", __func__,
230 (unsigned int)host->reg, id);
231
232 /* Set the pad drive strength for SDMMC1 or 3 only */
233 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
234 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
235 __func__);
236 return;
237 }
238
239 val = readl(&host->reg->sdmemcmppadctl);
240 val &= 0xFFFFFFF0;
241 val |= MEMCOMP_PADCTRL_VREF;
242 writel(val, &host->reg->sdmemcmppadctl);
243
244 val = readl(&host->reg->autocalcfg);
245 val &= 0xFFFF0000;
246 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
247 writel(val, &host->reg->autocalcfg);
248#endif /* T30 */
249}
250#endif /* MMC */