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8ed96046 WD |
1 | /* |
2 | * (C) Copyright 2004 | |
3 | * Texas Instruments, <www.ti.com> | |
4 | * Richard Woodruff <r-woodruff2@ti.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | #include <common.h> | |
25 | #include <asm/arch/omap2420.h> | |
26 | #include <asm/io.h> | |
27 | #include <asm/arch/bits.h> | |
28 | #include <asm/arch/mux.h> | |
29 | #include <asm/arch/sys_proto.h> | |
30 | #include <asm/arch/sys_info.h> | |
31 | #include <asm/arch/mem.h> | |
32 | #include <i2c.h> | |
33 | #include <asm/mach-types.h> | |
3fe00109 | 34 | #if defined(CONFIG_CMD_NAND) |
addb2e16 | 35 | #include <linux/mtd/nand_legacy.h> |
289f932c WD |
36 | extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE]; |
37 | #endif | |
38 | ||
d87080b7 WD |
39 | DECLARE_GLOBAL_DATA_PTR; |
40 | ||
41 | void wait_for_command_complete(unsigned int wd_base); | |
8ed96046 WD |
42 | |
43 | /******************************************************* | |
44 | * Routine: delay | |
45 | * Description: spinning delay to use before udelay works | |
46 | ******************************************************/ | |
47 | static inline void delay (unsigned long loops) | |
48 | { | |
289f932c WD |
49 | __asm__ volatile ("1:\n" "subs %0, %1, #1\n" |
50 | "bne 1b":"=r" (loops):"0" (loops)); | |
8ed96046 WD |
51 | } |
52 | ||
53 | /***************************************** | |
54 | * Routine: board_init | |
55 | * Description: Early hardware init. | |
56 | *****************************************/ | |
57 | int board_init (void) | |
58 | { | |
289f932c WD |
59 | gpmc_init(); /* in SRAM or SDRM, finish GPMC */ |
60 | ||
8ed96046 WD |
61 | gd->bd->bi_arch_number = MACH_TYPE_OMAP_H4; /* board id for linux */ |
62 | gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0+0x100); /* adress of boot parameters */ | |
63 | ||
64 | return 0; | |
65 | } | |
66 | ||
49a7581c WD |
67 | /********************************************************** |
68 | * Routine: try_unlock_sram() | |
69 | * Description: If chip is GP type, unlock the SRAM for | |
70 | * general use. | |
71 | ***********************************************************/ | |
72 | void try_unlock_sram(void) | |
73 | { | |
74 | /* if GP device unlock device SRAM for general use */ | |
75 | if (get_device_type() == GP_DEVICE) { | |
76 | __raw_writel(0xFF, A_REQINFOPERM0); | |
77 | __raw_writel(0xCFDE, A_READPERM0); | |
78 | __raw_writel(0xCFDE, A_WRITEPERM0); | |
79 | } | |
80 | } | |
81 | ||
8ed96046 WD |
82 | /********************************************************** |
83 | * Routine: s_init | |
84 | * Description: Does early system init of muxing and clocks. | |
289f932c | 85 | * - Called path is with sram stack. |
8ed96046 | 86 | **********************************************************/ |
289f932c | 87 | void s_init(void) |
8ed96046 | 88 | { |
289f932c WD |
89 | int in_sdram = running_in_sdram(); |
90 | ||
8ed96046 WD |
91 | watchdog_init(); |
92 | set_muxconf_regs(); | |
93 | delay(100); | |
c97a2aaf | 94 | try_unlock_sram(); |
8ed96046 | 95 | |
289f932c | 96 | if(!in_sdram) |
8ed96046 WD |
97 | prcm_init(); |
98 | ||
99 | peripheral_enable(); | |
100 | icache_enable(); | |
289f932c WD |
101 | if (!in_sdram) |
102 | sdrc_init(); | |
8ed96046 WD |
103 | } |
104 | ||
105 | /******************************************************* | |
106 | * Routine: misc_init_r | |
107 | * Description: Init ethernet (done here so udelay works) | |
108 | ********************************************************/ | |
109 | int misc_init_r (void) | |
110 | { | |
111 | ether_init(); /* better done here so timers are init'ed */ | |
112 | return(0); | |
113 | } | |
114 | ||
115 | /**************************************** | |
116 | * Routine: watchdog_init | |
117 | * Description: Shut down watch dogs | |
118 | *****************************************/ | |
119 | void watchdog_init(void) | |
120 | { | |
8ed96046 | 121 | /* There are 4 watch dogs. 1 secure, and 3 general purpose. |
fe7eb5d8 | 122 | * The ROM takes care of the secure one. Of the 3 GP ones, |
c97a2aaf WD |
123 | * 1 can reset us directly, the other 2 only generate MPU interrupts. |
124 | */ | |
8ed96046 WD |
125 | __raw_writel(WD_UNLOCK1 ,WD2_BASE+WSPR); |
126 | wait_for_command_complete(WD2_BASE); | |
127 | __raw_writel(WD_UNLOCK2 ,WD2_BASE+WSPR); | |
128 | ||
129 | #if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite*/ | |
130 | __raw_writel(WD_UNLOCK1 ,WD3_BASE+WSPR); | |
131 | wait_for_command_complete(WD3_BASE); | |
132 | __raw_writel(WD_UNLOCK2 ,WD3_BASE+WSPR); | |
133 | ||
134 | __raw_writel(WD_UNLOCK1 ,WD4_BASE+WSPR); | |
135 | wait_for_command_complete(WD4_BASE); | |
136 | __raw_writel(WD_UNLOCK2 ,WD4_BASE+WSPR); | |
137 | #endif | |
138 | } | |
139 | ||
140 | /****************************************************** | |
141 | * Routine: wait_for_command_complete | |
142 | * Description: Wait for posting to finish on watchdog | |
143 | ******************************************************/ | |
49a7581c | 144 | void wait_for_command_complete(unsigned int wd_base) |
8ed96046 WD |
145 | { |
146 | int pending = 1; | |
147 | do { | |
148 | pending = __raw_readl(wd_base+WWPS); | |
149 | } while (pending); | |
150 | } | |
151 | ||
152 | /******************************************************************* | |
153 | * Routine:ether_init | |
154 | * Description: take the Ethernet controller out of reset and wait | |
155 | * for the EEPROM load to complete. | |
156 | ******************************************************************/ | |
157 | void ether_init (void) | |
158 | { | |
159 | #ifdef CONFIG_DRIVER_LAN91C96 | |
160 | int cnt = 20; | |
161 | ||
289f932c WD |
162 | __raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */ |
163 | ||
8ed96046 WD |
164 | __raw_writew(0x0, LAN_RESET_REGISTER); |
165 | do { | |
166 | __raw_writew(0x1, LAN_RESET_REGISTER); | |
167 | udelay (100); | |
168 | if (cnt == 0) | |
169 | goto h4reset_err_out; | |
170 | --cnt; | |
171 | } while (__raw_readw(LAN_RESET_REGISTER) != 0x1); | |
172 | ||
173 | cnt = 20; | |
174 | ||
175 | do { | |
176 | __raw_writew(0x0, LAN_RESET_REGISTER); | |
177 | udelay (100); | |
178 | if (cnt == 0) | |
179 | goto h4reset_err_out; | |
180 | --cnt; | |
181 | } while (__raw_readw(LAN_RESET_REGISTER) != 0x0000); | |
182 | udelay (1000); | |
183 | ||
184 | *((volatile unsigned char *) ETH_CONTROL_REG) &= ~0x01; | |
185 | udelay (1000); | |
186 | ||
187 | h4reset_err_out: | |
188 | return; | |
189 | #endif | |
190 | } | |
191 | ||
192 | /********************************************** | |
193 | * Routine: dram_init | |
194 | * Description: sets uboots idea of sdram size | |
195 | **********************************************/ | |
196 | int dram_init (void) | |
197 | { | |
8ed96046 | 198 | unsigned int size0=0,size1=0; |
49a7581c | 199 | u32 mtype, btype, rev, cpu; |
289f932c WD |
200 | u8 chg_on = 0x5; /* enable charge of back up battery */ |
201 | u8 vmode_on = 0x8C; | |
202 | #define NOT_EARLY 0 | |
8ed96046 WD |
203 | |
204 | i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */ | |
205 | ||
206 | btype = get_board_type(); | |
207 | mtype = get_mem_type(); | |
49a7581c WD |
208 | rev = get_cpu_rev(); |
209 | cpu = get_cpu_type(); | |
8ed96046 WD |
210 | |
211 | display_board_info(btype); | |
289f932c WD |
212 | if (btype == BOARD_H4_MENELAUS){ |
213 | update_mux(btype,mtype); /* combo part on menelaus */ | |
214 | i2c_write(I2C_MENELAUS, 0x20, 1, &chg_on, 1); /*fix POR reset bug */ | |
215 | i2c_write(I2C_MENELAUS, 0x2, 1, &vmode_on, 1); /* VCORE change on VMODE */ | |
216 | } | |
8ed96046 WD |
217 | |
218 | if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) { | |
219 | do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */ | |
49a7581c WD |
220 | } |
221 | size0 = get_sdr_cs_size(SDRC_CS0_OSET); | |
222 | size1 = get_sdr_cs_size(SDRC_CS1_OSET); | |
8ed96046 WD |
223 | |
224 | gd->bd->bi_dram[0].start = PHYS_SDRAM_1; | |
225 | gd->bd->bi_dram[0].size = size0; | |
49a7581c WD |
226 | if(rev == CPU_2420_2422_ES1) /* ES1's 128MB remap granularity isn't worth doing */ |
227 | gd->bd->bi_dram[1].start = PHYS_SDRAM_2; | |
228 | else /* ES2 and above can remap at 32MB granularity */ | |
229 | gd->bd->bi_dram[1].start = PHYS_SDRAM_1+size0; | |
8ed96046 WD |
230 | gd->bd->bi_dram[1].size = size1; |
231 | ||
232 | return 0; | |
233 | } | |
234 | ||
235 | /********************************************************** | |
236 | * Routine: set_muxconf_regs | |
237 | * Description: Setting up the configuration Mux registers | |
238 | * specific to the hardware | |
239 | *********************************************************/ | |
240 | void set_muxconf_regs (void) | |
241 | { | |
242 | muxSetupSDRC(); | |
243 | muxSetupGPMC(); | |
244 | muxSetupUsb0(); | |
245 | muxSetupUart3(); | |
246 | muxSetupI2C1(); | |
247 | muxSetupUART1(); | |
248 | muxSetupLCD(); | |
249 | muxSetupCamera(); | |
250 | muxSetupMMCSD(); | |
251 | muxSetupTouchScreen(); | |
252 | muxSetupHDQ(); | |
253 | } | |
254 | ||
255 | /***************************************************************** | |
256 | * Routine: peripheral_enable | |
257 | * Description: Enable the clks & power for perifs (GPT2, UART1,...) | |
258 | ******************************************************************/ | |
259 | void peripheral_enable(void) | |
260 | { | |
261 | unsigned int v, if_clks=0, func_clks=0; | |
262 | ||
263 | /* Enable GP2 timer.*/ | |
264 | if_clks |= BIT4; | |
265 | func_clks |= BIT4; | |
266 | v = __raw_readl(CM_CLKSEL2_CORE) | 0x4; /* Sys_clk input OMAP2420_GPT2 */ | |
267 | __raw_writel(v, CM_CLKSEL2_CORE); | |
268 | __raw_writel(0x1, CM_CLKSEL_WKUP); | |
269 | ||
270 | #ifdef CFG_NS16550 | |
271 | /* Enable UART1 clock */ | |
272 | func_clks |= BIT21; | |
273 | if_clks |= BIT21; | |
274 | #endif | |
275 | v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */ | |
276 | __raw_writel(v,CM_ICLKEN1_CORE ); | |
277 | v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */ | |
278 | __raw_writel(v, CM_FCLKEN1_CORE); | |
279 | delay(1000); | |
280 | ||
281 | #ifndef KERNEL_UPDATED | |
282 | { | |
283 | #define V1 0xffffffff | |
284 | #define V2 0x00000007 | |
285 | ||
286 | __raw_writel(V1, CM_FCLKEN1_CORE); | |
287 | __raw_writel(V2, CM_FCLKEN2_CORE); | |
288 | __raw_writel(V1, CM_ICLKEN1_CORE); | |
289 | __raw_writel(V1, CM_ICLKEN2_CORE); | |
290 | } | |
291 | #endif | |
292 | } | |
293 | ||
294 | /**************************************** | |
295 | * Routine: muxSetupUsb0 (ostboot) | |
296 | * Description: Setup usb muxing | |
297 | *****************************************/ | |
298 | void muxSetupUsb0(void) | |
299 | { | |
300 | volatile uint8 *MuxConfigReg; | |
301 | volatile uint32 *otgCtrlReg; | |
302 | ||
303 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN; | |
304 | *MuxConfigReg &= (uint8)(~0x1F); | |
305 | ||
306 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP; | |
307 | *MuxConfigReg &= (uint8)(~0x1F); | |
308 | ||
309 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM; | |
310 | *MuxConfigReg &= (uint8)(~0x1F); | |
311 | ||
312 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV; | |
313 | *MuxConfigReg &= (uint8)(~0x1F); | |
314 | ||
315 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN; | |
316 | *MuxConfigReg &= (uint8)(~0x1F); | |
317 | ||
318 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0; | |
319 | *MuxConfigReg &= (uint8)(~0x1F); | |
320 | ||
321 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT; | |
322 | *MuxConfigReg &= (uint8)(~0x1F); | |
323 | ||
324 | /* setup for USB VBus detection */ | |
325 | otgCtrlReg = (volatile uint32 *)USB_OTG_CTRL; | |
326 | *otgCtrlReg |= 0x00040000; /* bit 18 */ | |
327 | } | |
328 | ||
329 | /**************************************** | |
330 | * Routine: muxSetupUart3 (ostboot) | |
331 | * Description: Setup uart3 muxing | |
332 | *****************************************/ | |
333 | void muxSetupUart3(void) | |
334 | { | |
335 | volatile uint8 *MuxConfigReg; | |
336 | ||
337 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_TX_IRTX; | |
338 | *MuxConfigReg &= (uint8)(~0x1F); | |
339 | ||
340 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_UART3_RX_IRRX; | |
341 | *MuxConfigReg &= (uint8)(~0x1F); | |
342 | } | |
343 | ||
344 | /**************************************** | |
345 | * Routine: muxSetupI2C1 (ostboot) | |
346 | * Description: Setup i2c muxing | |
347 | *****************************************/ | |
348 | void muxSetupI2C1(void) | |
349 | { | |
350 | volatile unsigned char *MuxConfigReg; | |
351 | ||
352 | /* I2C1 Clock pin configuration, PIN = M19 */ | |
353 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL; | |
082acfd4 | 354 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
355 | |
356 | /* I2C1 Data pin configuration, PIN = L15 */ | |
357 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA; | |
082acfd4 | 358 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
359 | |
360 | /* Pull-up required on data line */ | |
361 | /* external pull-up already present. */ | |
362 | /* *MuxConfigReg |= 0x18 ;*/ /* Mode = 0, PullTypeSel=PU, PullUDEnable=Enabled */ | |
363 | } | |
364 | ||
365 | /**************************************** | |
366 | * Routine: muxSetupUART1 (ostboot) | |
367 | * Description: Set up uart1 muxing | |
368 | *****************************************/ | |
369 | void muxSetupUART1(void) | |
370 | { | |
371 | volatile unsigned char *MuxConfigReg; | |
372 | ||
373 | /* UART1_CTS pin configuration, PIN = D21 */ | |
374 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS; | |
375 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ | |
376 | ||
377 | /* UART1_RTS pin configuration, PIN = H21 */ | |
378 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS; | |
379 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ | |
380 | ||
381 | /* UART1_TX pin configuration, PIN = L20 */ | |
382 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX; | |
383 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ | |
384 | ||
385 | /* UART1_RX pin configuration, PIN = T21 */ | |
386 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX; | |
387 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ | |
388 | } | |
389 | ||
390 | /**************************************** | |
391 | * Routine: muxSetupLCD (ostboot) | |
392 | * Description: Setup lcd muxing | |
393 | *****************************************/ | |
394 | void muxSetupLCD(void) | |
395 | { | |
396 | volatile unsigned char *MuxConfigReg; | |
397 | ||
398 | /* LCD_D0 pin configuration, PIN = Y7 */ | |
399 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0; | |
082acfd4 | 400 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
401 | |
402 | /* LCD_D1 pin configuration, PIN = P10 */ | |
403 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1; | |
082acfd4 | 404 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
405 | |
406 | /* LCD_D2 pin configuration, PIN = V8 */ | |
407 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2; | |
082acfd4 | 408 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
409 | |
410 | /* LCD_D3 pin configuration, PIN = Y8 */ | |
411 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3; | |
082acfd4 | 412 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
413 | |
414 | /* LCD_D4 pin configuration, PIN = W8 */ | |
415 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4; | |
082acfd4 | 416 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
417 | |
418 | /* LCD_D5 pin configuration, PIN = R10 */ | |
419 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5; | |
082acfd4 | 420 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
421 | |
422 | /* LCD_D6 pin configuration, PIN = Y9 */ | |
423 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6; | |
082acfd4 | 424 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
425 | |
426 | /* LCD_D7 pin configuration, PIN = V9 */ | |
427 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7; | |
082acfd4 | 428 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
429 | |
430 | /* LCD_D8 pin configuration, PIN = W9 */ | |
431 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8; | |
082acfd4 | 432 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
433 | |
434 | /* LCD_D9 pin configuration, PIN = P11 */ | |
435 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9; | |
082acfd4 | 436 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
437 | |
438 | /* LCD_D10 pin configuration, PIN = V10 */ | |
439 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10; | |
082acfd4 | 440 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
441 | |
442 | /* LCD_D11 pin configuration, PIN = Y10 */ | |
443 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11; | |
082acfd4 | 444 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
445 | |
446 | /* LCD_D12 pin configuration, PIN = W10 */ | |
447 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12; | |
082acfd4 | 448 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
449 | |
450 | /* LCD_D13 pin configuration, PIN = R11 */ | |
451 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13; | |
082acfd4 | 452 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
453 | |
454 | /* LCD_D14 pin configuration, PIN = V11 */ | |
455 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14; | |
082acfd4 | 456 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
457 | |
458 | /* LCD_D15 pin configuration, PIN = W11 */ | |
459 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15; | |
082acfd4 | 460 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
461 | |
462 | /* LCD_D16 pin configuration, PIN = P12 */ | |
463 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16; | |
082acfd4 | 464 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
465 | |
466 | /* LCD_D17 pin configuration, PIN = R12 */ | |
467 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17; | |
082acfd4 | 468 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
469 | |
470 | /* LCD_PCLK pin configuration, PIN = W6 */ | |
471 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK; | |
082acfd4 | 472 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
473 | |
474 | /* LCD_VSYNC pin configuration, PIN = V7 */ | |
475 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC; | |
082acfd4 | 476 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
477 | |
478 | /* LCD_HSYNC pin configuration, PIN = Y6 */ | |
479 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC; | |
082acfd4 | 480 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
481 | |
482 | /* LCD_ACBIAS pin configuration, PIN = W7 */ | |
483 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS; | |
082acfd4 | 484 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
485 | } |
486 | ||
487 | /**************************************** | |
488 | * Routine: muxSetupCamera (ostboot) | |
489 | * Description: Setup camera muxing | |
490 | *****************************************/ | |
491 | void muxSetupCamera(void) | |
492 | { | |
493 | volatile unsigned char *MuxConfigReg; | |
494 | ||
495 | /* CAMERA_RSTZ pin configuration, PIN = Y16 */ | |
496 | /* CAM_RST is connected through the I2C IO expander.*/ | |
497 | /* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/ | |
289f932c | 498 | /* *MuxConfigReg = 0x00 ; / * Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
499 | |
500 | /* CAMERA_XCLK pin configuration, PIN = U3 */ | |
501 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK; | |
082acfd4 | 502 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
503 | |
504 | /* CAMERA_LCLK pin configuration, PIN = V5 */ | |
505 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK; | |
082acfd4 | 506 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
507 | |
508 | /* CAMERA_VSYNC pin configuration, PIN = U2 */ | |
509 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS, | |
082acfd4 | 510 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
511 | |
512 | /* CAMERA_HSYNC pin configuration, PIN = T3 */ | |
513 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS, | |
082acfd4 | 514 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
515 | |
516 | /* CAMERA_DAT0 pin configuration, PIN = T4 */ | |
517 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0, | |
082acfd4 | 518 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
519 | |
520 | /* CAMERA_DAT1 pin configuration, PIN = V2 */ | |
521 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1, | |
082acfd4 | 522 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
523 | |
524 | /* CAMERA_DAT2 pin configuration, PIN = V3 */ | |
525 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2, | |
082acfd4 | 526 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
527 | |
528 | /* CAMERA_DAT3 pin configuration, PIN = U4 */ | |
529 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3, | |
082acfd4 | 530 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
531 | |
532 | /* CAMERA_DAT4 pin configuration, PIN = W2 */ | |
533 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4, | |
082acfd4 | 534 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
535 | |
536 | /* CAMERA_DAT5 pin configuration, PIN = V4 */ | |
537 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5, | |
082acfd4 | 538 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
539 | |
540 | /* CAMERA_DAT6 pin configuration, PIN = W3 */ | |
541 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6, | |
082acfd4 | 542 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
543 | |
544 | /* CAMERA_DAT7 pin configuration, PIN = Y2 */ | |
545 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7, | |
082acfd4 | 546 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
547 | |
548 | /* CAMERA_DAT8 pin configuration, PIN = Y4 */ | |
549 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8, | |
082acfd4 | 550 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
551 | |
552 | /* CAMERA_DAT9 pin configuration, PIN = V6 */ | |
553 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9, | |
082acfd4 | 554 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
555 | } |
556 | ||
557 | /**************************************** | |
558 | * Routine: muxSetupMMCSD (ostboot) | |
559 | * Description: set up MMC muxing | |
560 | *****************************************/ | |
561 | void muxSetupMMCSD(void) | |
562 | { | |
563 | volatile unsigned char *MuxConfigReg; | |
564 | ||
565 | /* SDMMC_CLKI pin configuration, PIN = H15 */ | |
566 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI, | |
082acfd4 | 567 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
568 | |
569 | /* SDMMC_CLKO pin configuration, PIN = G19 */ | |
570 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO, | |
082acfd4 | 571 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
572 | |
573 | /* SDMMC_CMD pin configuration, PIN = H18 */ | |
574 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD, | |
082acfd4 WD |
575 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
576 | /* External pull-ups are present. */ | |
577 | /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ | |
8ed96046 WD |
578 | |
579 | /* SDMMC_DAT0 pin configuration, PIN = F20 */ | |
580 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0, | |
082acfd4 WD |
581 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
582 | /* External pull-ups are present. */ | |
583 | /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ | |
8ed96046 WD |
584 | |
585 | /* SDMMC_DAT1 pin configuration, PIN = H14 */ | |
586 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1, | |
082acfd4 WD |
587 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
588 | /* External pull-ups are present. */ | |
589 | /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ | |
8ed96046 WD |
590 | |
591 | /* SDMMC_DAT2 pin configuration, PIN = E19 */ | |
592 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2, | |
082acfd4 WD |
593 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
594 | /* External pull-ups are present. */ | |
595 | /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ | |
8ed96046 WD |
596 | |
597 | /* SDMMC_DAT3 pin configuration, PIN = D19 */ | |
598 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3, | |
082acfd4 WD |
599 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
600 | /* External pull-ups are present. */ | |
601 | /* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */ | |
8ed96046 WD |
602 | |
603 | /* SDMMC_DDIR0 pin configuration, PIN = F19 */ | |
604 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0, | |
082acfd4 | 605 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
606 | |
607 | /* SDMMC_DDIR1 pin configuration, PIN = E20 */ | |
608 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1, | |
082acfd4 | 609 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
610 | |
611 | /* SDMMC_DDIR2 pin configuration, PIN = F18 */ | |
612 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2, | |
082acfd4 | 613 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
614 | |
615 | /* SDMMC_DDIR3 pin configuration, PIN = E18 */ | |
616 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3, | |
082acfd4 | 617 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
618 | |
619 | /* SDMMC_CDIR pin configuration, PIN = G18 */ | |
620 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR, | |
082acfd4 | 621 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
622 | |
623 | /* MMC_CD pin configuration, PIN = B3 ---2420IP ONLY---*/ | |
624 | /* MMC_CD for 2422IP=K1 */ | |
625 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14, | |
082acfd4 | 626 | *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */ |
8ed96046 WD |
627 | |
628 | /* MMC_WP pin configuration, PIN = B4 */ | |
629 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13, | |
082acfd4 | 630 | *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */ |
8ed96046 WD |
631 | } |
632 | ||
633 | /****************************************** | |
634 | * Routine: muxSetupTouchScreen (ostboot) | |
635 | * Description: Set up touch screen muxing | |
636 | *******************************************/ | |
637 | void muxSetupTouchScreen(void) | |
638 | { | |
639 | volatile unsigned char *MuxConfigReg; | |
640 | ||
641 | /* SPI1_CLK pin configuration, PIN = U18 */ | |
642 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK, | |
082acfd4 | 643 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
644 | |
645 | /* SPI1_MOSI pin configuration, PIN = V20 */ | |
646 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO, | |
082acfd4 | 647 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
648 | |
649 | /* SPI1_MISO pin configuration, PIN = T18 */ | |
650 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI, | |
082acfd4 | 651 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
652 | |
653 | /* SPI1_nCS0 pin configuration, PIN = U19 */ | |
654 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0, | |
082acfd4 | 655 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
656 | |
657 | /* PEN_IRQ pin configuration, PIN = P20 */ | |
658 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR, | |
082acfd4 | 659 | *MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */ |
8ed96046 WD |
660 | } |
661 | ||
662 | /**************************************** | |
663 | * Routine: muxSetupHDQ (ostboot) | |
664 | * Description: setup 1wire mux | |
665 | *****************************************/ | |
666 | void muxSetupHDQ(void) | |
667 | { | |
668 | volatile unsigned char *MuxConfigReg; | |
669 | ||
670 | /* HDQ_SIO pin configuration, PIN = N18 */ | |
671 | MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO, | |
082acfd4 | 672 | *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */ |
8ed96046 WD |
673 | } |
674 | ||
675 | /*************************************************************** | |
676 | * Routine: muxSetupGPMC (ostboot) | |
677 | * Description: Configures balls which cam up in protected mode | |
678 | ***************************************************************/ | |
679 | void muxSetupGPMC(void) | |
680 | { | |
681 | volatile uint8 *MuxConfigReg; | |
289f932c | 682 | volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C; |
8ed96046 WD |
683 | |
684 | /* gpmc_io_dir */ | |
685 | *MCR = 0x19000000; | |
686 | ||
687 | /* NOR FLASH CS0 */ | |
688 | /* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode - 0; Byte-3 Pull/up - N/A */ | |
689 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3, | |
690 | *MuxConfigReg = 0x00 ; | |
691 | ||
692 | /* signal - Gpmc_iodir; pin - n2; offset - 0x008C; mode - 1; Byte-3 Pull/up - N/A */ | |
693 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3, | |
694 | *MuxConfigReg = 0x01 ; | |
695 | ||
696 | /* MPDB(Multi Port Debug Port) CS1 */ | |
697 | /* signal - gpmc_ncs1; pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */ | |
698 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1, | |
699 | *MuxConfigReg = 0x00 ; | |
700 | ||
701 | /* signal - Gpmc_ncs2; pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */ | |
702 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2, | |
703 | *MuxConfigReg = 0x00 ; | |
8ed96046 WD |
704 | } |
705 | ||
706 | /**************************************************************** | |
707 | * Routine: muxSetupSDRC (ostboot) | |
708 | * Description: Configures balls which come up in protected mode | |
709 | ****************************************************************/ | |
710 | void muxSetupSDRC(void) | |
711 | { | |
712 | volatile uint8 *MuxConfigReg; | |
713 | ||
714 | /* signal - sdrc_ncs1; pin - C12; offset - 0x00A0; mode - 0; Byte-1 Pull/up - N/A */ | |
715 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE1, | |
716 | *MuxConfigReg = 0x00 ; | |
717 | ||
718 | /* signal - sdrc_a12; pin - D11; offset - 0x0030; mode - 0; Byte-2 Pull/up - N/A */ | |
719 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE2, | |
720 | *MuxConfigReg = 0x00 ; | |
721 | ||
722 | /* signal - sdrc_cke1; pin - B13; offset - 0x00A0; mode - 0; Byte-3 Pull/up - N/A */ | |
723 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_NCS0_BYTE3, | |
724 | *MuxConfigReg = 0x00; | |
725 | ||
726 | if (get_cpu_type() == CPU_2422) { | |
727 | MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_SDRC_A14_BYTE0, | |
728 | *MuxConfigReg = 0x1b; | |
729 | } | |
730 | } | |
731 | ||
732 | /***************************************************************************** | |
733 | * Routine: update_mux() | |
734 | * Description: Update balls which are different beween boards. All should be | |
735 | * updated to match functionaly. However, I'm only updating ones | |
736 | * which I'll be using for now. When power comes into play they | |
737 | * all need updating. | |
738 | *****************************************************************************/ | |
739 | void update_mux(u32 btype,u32 mtype) | |
740 | { | |
741 | u32 cpu, base = OMAP2420_CTRL_BASE; | |
742 | cpu = get_cpu_type(); | |
743 | ||
744 | if (btype == BOARD_H4_MENELAUS) { | |
745 | if (cpu == CPU_2420) { | |
746 | /* PIN = B3, GPIO.0->KBR5, mode 3, (pun?),-DO-*/ | |
747 | __raw_writeb(0x3, base+0x30); | |
748 | /* PIN = B13, GPIO.38->KBC6, mode 3, (pun?)-DO-*/ | |
749 | __raw_writeb(0x3, base+0xa3); | |
750 | /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/ | |
751 | /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/ | |
752 | /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/ | |
753 | /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/ | |
754 | /* PIN = M1 (HSUSBOTG) */ | |
755 | /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/ | |
756 | __raw_writeb(0x3, base+0x9d); | |
757 | /* PIN = U32, (WLAN_CLKREQ) */ | |
758 | /* PIN = Y11, WLAN */ | |
759 | /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */ | |
760 | __raw_writeb(0x3, base+0xe7); | |
761 | /* PIN = AA8, mDOC */ | |
762 | /* PIN = AA10, BT */ | |
763 | /* PIN = AA13, WLAN */ | |
764 | /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */ | |
765 | __raw_writeb(0x3, base+0x10e); | |
766 | /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */ | |
767 | __raw_writeb(0x3, base+0x110); | |
768 | /* PIN = J15 HHUSB */ | |
769 | /* PIN = H19 HSUSB */ | |
770 | /* PIN = W13, P13, R13, W16 ... */ | |
771 | /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */ | |
772 | __raw_writeb(0x3, base+0xde); | |
773 | /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */ | |
774 | __raw_writeb(0x0, base+0x12c); | |
775 | /* PIN = AA17->sys_clkreq mode 0 -DO- */ | |
776 | __raw_writeb(0x0, base+0x136); | |
777 | } else if (cpu == CPU_2422) { | |
778 | /* PIN = B3, GPIO.0->nc, mode 3, set above (pun?)*/ | |
779 | /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/ | |
780 | /* PIN = F1, GPIO.25->HSUSBxx mode 3, (for external HS USB)*/ | |
781 | /* PIN = H1, GPIO.26->HSUSBxx mode 3, (for external HS USB)*/ | |
782 | /* PIN = K1, GPMC_ncs6 mode 0, (on board nand access)*/ | |
783 | __raw_writeb(0x0, base+0x92); | |
784 | /* PIN = L2, GPMC_ncs67 mode 0, (for external HS USB)*/ | |
785 | /* PIN = M1 (HSUSBOTG) */ | |
786 | /* PIN = P1, GPIO.35->MEN_POK mode 3, (menelaus powerok)-DO-*/ | |
787 | __raw_writeb(0x3, base+0x10c); | |
788 | /* PIN = U32, (WLAN_CLKREQ) */ | |
789 | /* PIN = AA4, GPIO.15->KBC2, mode 3, -DO- */ | |
790 | __raw_writeb(0x3, base+0x30); | |
791 | /* PIN = AA8, mDOC */ | |
792 | /* PIN = AA10, BT */ | |
793 | /* PIN = AA12, WLAN */ | |
794 | /* PIN = M18 GPIO.96->MMC2_WP mode 3 -DO- */ | |
795 | __raw_writeb(0x3, base+0x10e); | |
796 | /* PIN = N19 GPIO.98->WLAN_INT mode 3 -DO- */ | |
797 | __raw_writeb(0x3, base+0x110); | |
798 | /* PIN = J15 HHUSB */ | |
799 | /* PIN = H19 HSUSB */ | |
800 | /* PIN = W13, P13, R13, W16 ... */ | |
801 | /* PIN = V12 GPIO.25->I2C_CAMEN mode 3 -DO- */ | |
802 | __raw_writeb(0x3, base+0xde); | |
803 | /* PIN = W19 sys_nirq->MENELAUS_INT mode 0 -DO- */ | |
804 | __raw_writeb(0x0, base+0x12c); | |
805 | /* PIN = AA17->sys_clkreq mode 0 -DO- */ | |
806 | __raw_writeb(0x0, base+0x136); | |
807 | } | |
808 | ||
809 | } else if (btype == BOARD_H4_SDP) { | |
810 | if (cpu == CPU_2420) { | |
811 | /* PIN = B3, GPIO.0->nc mode 3, set above (pun?)*/ | |
812 | /* PIN = B13, GPIO.cke1->nc, mode 0, set above, (pun?)*/ | |
813 | /* Pin = Y11 VLNQ */ | |
814 | /* Pin = AA4 VLNQ */ | |
815 | /* Pin = AA6 VLNQ */ | |
816 | /* Pin = AA8 VLNQ */ | |
817 | /* Pin = AA10 VLNQ */ | |
818 | /* Pin = AA12 VLNQ */ | |
819 | /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */ | |
820 | __raw_writeb(0x3, base+0x10e); | |
821 | /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */ | |
822 | __raw_writeb(0x3, base+0x110); | |
823 | /* PIN = J15 MDOC_nDMAREQ */ | |
824 | /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */ | |
825 | __raw_writeb(0x3, base+0x114); | |
826 | /* PIN = W13, V12, P13, R13, W19, W16 ... */ | |
827 | /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */ | |
828 | } else if (cpu == CPU_2422) { | |
829 | /* PIN = B3, GPIO.0->MMC_CD, mode 3, set above */ | |
830 | /* PIN = B13, GPIO.38->wlan_int, mode 3, (pun?)*/ | |
831 | /* Pin = Y11 VLNQ */ | |
832 | /* Pin = AA4 VLNQ */ | |
833 | /* Pin = AA6 VLNQ */ | |
834 | /* Pin = AA8 VLNQ */ | |
835 | /* Pin = AA10 VLNQ */ | |
836 | /* Pin = AA12 VLNQ */ | |
837 | /* PIN = M18 GPIO.96->KBR5 mode 3 -DO- */ | |
838 | __raw_writeb(0x3, base+0x10e); | |
839 | /* PIN = N19 GPIO.98->KBC6 mode 3 -DO- */ | |
840 | __raw_writeb(0x3, base+0x110); | |
841 | /* PIN = J15 MDOC_nDMAREQ */ | |
842 | /* PIN = H19 GPIO.100->KBC2 mode 3 -DO- */ | |
843 | __raw_writeb(0x3, base+0x114); | |
844 | /* PIN = W13, V12, P13, R13, W19, W16 ... */ | |
845 | /* PIN = AA17 sys_clkreq->bt_clk_req mode 0 */ | |
846 | } | |
847 | } | |
848 | } | |
289f932c | 849 | |
3fe00109 | 850 | #if defined(CONFIG_CMD_NAND) |
289f932c WD |
851 | void nand_init(void) |
852 | { | |
853 | extern flash_info_t flash_info[]; | |
854 | ||
855 | nand_probe(CFG_NAND_ADDR); | |
856 | if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) { | |
857 | print_size(nand_dev_desc[0].totlen, "\n"); | |
858 | } | |
859 | ||
860 | #ifdef CFG_JFFS2_MEM_NAND | |
861 | flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id; | |
862 | flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2; /* only read kernel single meg partition */ | |
863 | flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024; /* 1024 blocks in 16meg chip (use less for raw/copied partition) */ | |
864 | flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */ | |
865 | #endif | |
866 | } | |
867 | #endif |