[thirdparty/u-boot.git] / board / phytec / phycore_am335x_r2 / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * board.c
 *
 * Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards
 *
 * Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
 * Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
 * Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
 * Copyright (C) 2019 DENX Software Engineering GmbH
 */

#include <common.h>
#include <init.h>
#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/global_data.h>
#include <power/tps65910.h>
#include <jffs2/load_kernel.h>
#include <mtd_node.h>
#include <fdt_support.h>
#include "board.h"

DECLARE_GLOBAL_DATA_PTR;

#ifdef CONFIG_SPL_BUILD

static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;

/* DDR RAM defines */
#if defined(CONFIG_TARGET_PCM051)
#define DDR_CLK_MHZ		303 /* DDR_DPLL_MULT value */
#else
#define DDR_CLK_MHZ		400 /* DDR_DPLL_MULT value */
#endif

#define OSC	(V_OSCK / 1000000)
const struct dpll_params dpll_ddr = {
		DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};

const struct dpll_params *get_dpll_ddr_params(void)
{
	return &dpll_ddr;
}

const struct ctrl_ioregs ioregs = {
	.cm0ioctl		= 0x18B,
	.cm1ioctl		= 0x18B,
	.cm2ioctl		= 0x18B,
	.dt0ioctl		= 0x18B,
	.dt1ioctl		= 0x18B,
};

static const struct cmd_control ddr3_cmd_ctrl_data = {
	.cmd0csratio = 0x80,
	.cmd0iclkout = 0x0,

	.cmd1csratio = 0x80,
	.cmd1iclkout = 0x0,

	.cmd2csratio = 0x80,
	.cmd2iclkout = 0x0,
};

enum {
	PHYCORE_R2_MT41K128M16JT_256MB,
	PHYCORE_R2_MT41K256M16TW107IT_512MB,
	PHYCORE_R2_MT41K512M16HA125IT_1024MB,
	PHYCORE_R13_MT41K256M16HA125E_256MB,
};

struct am335x_sdram_timings {
	struct emif_regs ddr3_emif_reg_data;
	struct ddr_data ddr3_data;
};

static struct am335x_sdram_timings physom_timings[] = {
	[PHYCORE_R2_MT41K128M16JT_256MB] = {
		.ddr3_emif_reg_data = {
			.sdram_config = 0x61C052B2,
			.ref_ctrl = 0x00000C30,
			.sdram_tim1 = 0x0AAAD4DB,
			.sdram_tim2 = 0x26437FDA,
			.sdram_tim3 = 0x501F83FF,
			.zq_config = 0x50074BE4,
			.emif_ddr_phy_ctlr_1 = 0x7,
			.ocp_config = 0x003d3d3d,
		},
		.ddr3_data = {
			.datardsratio0 = 0x36,
			.datawdsratio0 = 0x38,
			.datafwsratio0 = 0x99,
			.datawrsratio0 = 0x73,
		},
	},
	[PHYCORE_R2_MT41K256M16TW107IT_512MB] = {
		.ddr3_emif_reg_data = {
			.sdram_config = 0x61C05332,
			.ref_ctrl = 0x00000C30,
			.sdram_tim1 = 0x0AAAD4DB,
			.sdram_tim2 = 0x266B7FDA,
			.sdram_tim3 = 0x501F867F,
			.zq_config = 0x50074BE4,
			.emif_ddr_phy_ctlr_1 = 0x7,
			.ocp_config = 0x003d3d3d,
		},
		.ddr3_data = {
			.datardsratio0 = 0x37,
			.datawdsratio0 = 0x38,
			.datafwsratio0 = 0x92,
			.datawrsratio0 = 0x72,
		},
	},
	[PHYCORE_R2_MT41K512M16HA125IT_1024MB] = {
		.ddr3_emif_reg_data = {
			.sdram_config = 0x61C053B2,
			.ref_ctrl = 0x00000C30,
			.sdram_tim1 = 0x0AAAD4DB,
			.sdram_tim2 = 0x268F7FDA,
			.sdram_tim3 = 0x501F88BF,
			.zq_config = 0x50074BE4,
			.emif_ddr_phy_ctlr_1 = 0x7,
			.ocp_config = 0x003d3d3d,
		},
		.ddr3_data = {
			.datardsratio0 = 0x38,
			.datawdsratio0 = 0x4d,
			.datafwsratio0 = 0x9d,
			.datawrsratio0 = 0x82,
		},
	},
	[PHYCORE_R13_MT41K256M16HA125E_256MB] = {
		.ddr3_emif_reg_data = {
			.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
			.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
			.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
			.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
			.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
			.zq_config = MT41K256M16HA125E_ZQ_CFG,
			.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY | PHY_EN_DYN_PWRDN,
		},
		.ddr3_data = {
			.datardsratio0 = MT41K256M16HA125E_RD_DQS,
			.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
			.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
			.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
		},
	},
};

void sdram_init(void)
{
#if defined(CONFIG_TARGET_PCM051)
	int ram_type_index = PHYCORE_R13_MT41K256M16HA125E_256MB;
#else
	/* Configure memory to maximum supported size for detection */
	int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;

	config_ddr(DDR_CLK_MHZ, &ioregs,
		   &physom_timings[ram_type_index].ddr3_data,
		   &ddr3_cmd_ctrl_data,
		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
		   0);

	/* Detect memory physically present */
	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
				    CFG_MAX_RAM_BANK_SIZE);

	/* Reconfigure memory for actual detected size */
	switch (gd->ram_size) {
	case SZ_1G:
		ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
		break;
	case SZ_512M:
		ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
		break;
	case SZ_256M:
	default:
		ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
		break;
	}
#endif
	config_ddr(DDR_CLK_MHZ, &ioregs,
		   &physom_timings[ram_type_index].ddr3_data,
		   &ddr3_cmd_ctrl_data,
		   &physom_timings[ram_type_index].ddr3_emif_reg_data,
		   0);
}

const struct dpll_params *get_dpll_mpu_params(void)
{
	int ind = get_sys_clk_index();
	int freq = am335x_get_efuse_mpu_max_freq(cdev);

	switch (freq) {
	case MPUPLL_M_1000:
		return &dpll_mpu_opp[ind][5];
	case MPUPLL_M_800:
		return &dpll_mpu_opp[ind][4];
	case MPUPLL_M_720:
		return &dpll_mpu_opp[ind][3];
	case MPUPLL_M_600:
		return &dpll_mpu_opp[ind][2];
	case MPUPLL_M_500:
		return &dpll_mpu_opp100;
	case MPUPLL_M_300:
		return &dpll_mpu_opp[ind][0];
	}

	return &dpll_mpu_opp[ind][0];
}

static void scale_vcores_generic(int freq)
{
	int sil_rev, mpu_vdd;

	/*
	 * We use a TPS65910 PMIC. For all  MPU frequencies we support we use a
	 * CORE voltage of 1.10V. For MPU voltage we need to switch based on
	 * the frequency we are running at.
	 */
	if (power_tps65910_init(0))
		return;

	/*
	 * Depending on MPU clock and PG we will need a different
	 * VDD to drive at that speed.
	 */
	sil_rev = readl(&cdev->deviceid) >> 28;
	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);

	/* Tell the TPS65910 to use i2c */
	tps65910_set_i2c_control();

	/* First update MPU voltage. */
	if (tps65910_voltage_update(MPU, mpu_vdd))
		return;

	/* Second, update the CORE voltage. */
	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
		return;
}

void scale_vcores(void)
{
	int freq;

	freq = am335x_get_efuse_mpu_max_freq(cdev);
	scale_vcores_generic(freq);
}

void set_uart_mux_conf(void)
{
	enable_uart0_pin_mux();
}

void set_mux_conf_regs(void)
{
	enable_i2c0_pin_mux();
	enable_board_pin_mux();
}
#endif

/*
 * Basic board specific setup.  Pinmux has been handled already.
 */
int board_init(void)
{
	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
	return 0;
}

#ifdef CONFIG_OF_BOARD_SETUP
int ft_board_setup(void *blob, struct bd_info *bd)
{
#ifdef CONFIG_FDT_FIXUP_PARTITIONS
	static const struct node_info nodes[] = {
		{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
	};

	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
#endif
	return 0;
}
#endif
Commit	Line	Data
6e171b66 NF	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* board.c
	4	*
	5	* Board functions for Phytec phyCORE-AM335x R2 (PCL060 / PCM060) based boards
	6	*
a94a4071	7	* Copyright (C) 2011, Texas Instruments, Incorporated - https://www.ti.com/
6e171b66 NF	8	* Copyright (C) 2013 Lars Poeschel, Lemonage Software GmbH
	9	* Copyright (C) 2015 Wadim Egorov, PHYTEC Messtechnik GmbH
	10	* Copyright (C) 2019 DENX Software Engineering GmbH
	11	*/
	12
d678a59d	13	#include <common.h>
9b4a205f	14	#include <init.h>
6e171b66 NF	15	#include <spl.h>
	16	#include <asm/arch/cpu.h>
	17	#include <asm/arch/ddr_defs.h>
	18	#include <asm/arch/clock.h>
	19	#include <asm/arch/sys_proto.h>
401d1c4f	20	#include <asm/global_data.h>
6e171b66 NF	21	#include <power/tps65910.h>
	22	#include <jffs2/load_kernel.h>
	23	#include <mtd_node.h>
	24	#include <fdt_support.h>
	25	#include "board.h"
	26
	27	DECLARE_GLOBAL_DATA_PTR;
	28
	29	#ifdef CONFIG_SPL_BUILD
	30
	31	static struct ctrl_dev cdev = (struct ctrl_dev )CTRL_DEVICE_BASE;
	32
	33	/* DDR RAM defines */
297c439b MK	34	#if defined(CONFIG_TARGET_PCM051)
	35	#define DDR_CLK_MHZ 303 /* DDR_DPLL_MULT value */
	36	#else
6e171b66	37	#define DDR_CLK_MHZ 400 /* DDR_DPLL_MULT value */
297c439b	38	#endif
6e171b66 NF	39
	40	#define OSC (V_OSCK / 1000000)
	41	const struct dpll_params dpll_ddr = {
	42	DDR_CLK_MHZ, OSC - 1, 1, -1, -1, -1, -1};
	43
	44	const struct dpll_params *get_dpll_ddr_params(void)
	45	{
	46	return &dpll_ddr;
	47	}
	48
	49	const struct ctrl_ioregs ioregs = {
	50	.cm0ioctl = 0x18B,
	51	.cm1ioctl = 0x18B,
	52	.cm2ioctl = 0x18B,
	53	.dt0ioctl = 0x18B,
	54	.dt1ioctl = 0x18B,
	55	};
	56
	57	static const struct cmd_control ddr3_cmd_ctrl_data = {
	58	.cmd0csratio = 0x80,
	59	.cmd0iclkout = 0x0,
	60
	61	.cmd1csratio = 0x80,
	62	.cmd1iclkout = 0x0,
	63
	64	.cmd2csratio = 0x80,
	65	.cmd2iclkout = 0x0,
	66	};
	67
	68	enum {
	69	PHYCORE_R2_MT41K128M16JT_256MB,
	70	PHYCORE_R2_MT41K256M16TW107IT_512MB,
	71	PHYCORE_R2_MT41K512M16HA125IT_1024MB,
297c439b	72	PHYCORE_R13_MT41K256M16HA125E_256MB,
6e171b66 NF	73	};
	74
	75	struct am335x_sdram_timings {
	76	struct emif_regs ddr3_emif_reg_data;
	77	struct ddr_data ddr3_data;
	78	};
	79
	80	static struct am335x_sdram_timings physom_timings[] = {
	81	[PHYCORE_R2_MT41K128M16JT_256MB] = {
	82	.ddr3_emif_reg_data = {
	83	.sdram_config = 0x61C052B2,
	84	.ref_ctrl = 0x00000C30,
	85	.sdram_tim1 = 0x0AAAD4DB,
	86	.sdram_tim2 = 0x26437FDA,
	87	.sdram_tim3 = 0x501F83FF,
	88	.zq_config = 0x50074BE4,
	89	.emif_ddr_phy_ctlr_1 = 0x7,
	90	.ocp_config = 0x003d3d3d,
	91	},
	92	.ddr3_data = {
	93	.datardsratio0 = 0x36,
	94	.datawdsratio0 = 0x38,
	95	.datafwsratio0 = 0x99,
	96	.datawrsratio0 = 0x73,
	97	},
	98	},
	99	[PHYCORE_R2_MT41K256M16TW107IT_512MB] = {
	100	.ddr3_emif_reg_data = {
	101	.sdram_config = 0x61C05332,
	102	.ref_ctrl = 0x00000C30,
	103	.sdram_tim1 = 0x0AAAD4DB,
	104	.sdram_tim2 = 0x266B7FDA,
	105	.sdram_tim3 = 0x501F867F,
	106	.zq_config = 0x50074BE4,
	107	.emif_ddr_phy_ctlr_1 = 0x7,
	108	.ocp_config = 0x003d3d3d,
	109	},
	110	.ddr3_data = {
	111	.datardsratio0 = 0x37,
	112	.datawdsratio0 = 0x38,
	113	.datafwsratio0 = 0x92,
	114	.datawrsratio0 = 0x72,
	115	},
	116	},
	117	[PHYCORE_R2_MT41K512M16HA125IT_1024MB] = {
	118	.ddr3_emif_reg_data = {
	119	.sdram_config = 0x61C053B2,
	120	.ref_ctrl = 0x00000C30,
	121	.sdram_tim1 = 0x0AAAD4DB,
	122	.sdram_tim2 = 0x268F7FDA,
	123	.sdram_tim3 = 0x501F88BF,
	124	.zq_config = 0x50074BE4,
	125	.emif_ddr_phy_ctlr_1 = 0x7,
	126	.ocp_config = 0x003d3d3d,
	127	},
	128	.ddr3_data = {
	129	.datardsratio0 = 0x38,
	130	.datawdsratio0 = 0x4d,
	131	.datafwsratio0 = 0x9d,
	132	.datawrsratio0 = 0x82,
	133	},
	134	},
297c439b MK	135	[PHYCORE_R13_MT41K256M16HA125E_256MB] = {
	136	.ddr3_emif_reg_data = {
	137	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
	138	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
	139	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
	140	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
	141	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
	142	.zq_config = MT41K256M16HA125E_ZQ_CFG,
	143	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY \| PHY_EN_DYN_PWRDN,
	144	},
	145	.ddr3_data = {
	146	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
	147	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
	148	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
	149	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
	150	},
	151	},
6e171b66 NF	152	};
	153
	154	void sdram_init(void)
	155	{
297c439b MK	156	#if defined(CONFIG_TARGET_PCM051)
	157	int ram_type_index = PHYCORE_R13_MT41K256M16HA125E_256MB;
	158	#else
6e171b66 NF	159	/* Configure memory to maximum supported size for detection */
	160	int ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
	161
	162	config_ddr(DDR_CLK_MHZ, &ioregs,
	163	&physom_timings[ram_type_index].ddr3_data,
	164	&ddr3_cmd_ctrl_data,
	165	&physom_timings[ram_type_index].ddr3_emif_reg_data,
	166	0);
	167
	168	/* Detect memory physically present */
aa6e94de	169	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
8a897c4f	170	CFG_MAX_RAM_BANK_SIZE);
6e171b66 NF	171
	172	/* Reconfigure memory for actual detected size */
	173	switch (gd->ram_size) {
	174	case SZ_1G:
	175	ram_type_index = PHYCORE_R2_MT41K512M16HA125IT_1024MB;
	176	break;
	177	case SZ_512M:
	178	ram_type_index = PHYCORE_R2_MT41K256M16TW107IT_512MB;
	179	break;
	180	case SZ_256M:
	181	default:
	182	ram_type_index = PHYCORE_R2_MT41K128M16JT_256MB;
	183	break;
	184	}
297c439b	185	#endif
6e171b66 NF	186	config_ddr(DDR_CLK_MHZ, &ioregs,
	187	&physom_timings[ram_type_index].ddr3_data,
	188	&ddr3_cmd_ctrl_data,
	189	&physom_timings[ram_type_index].ddr3_emif_reg_data,
	190	0);
	191	}
	192
	193	const struct dpll_params *get_dpll_mpu_params(void)
	194	{
	195	int ind = get_sys_clk_index();
	196	int freq = am335x_get_efuse_mpu_max_freq(cdev);
	197
	198	switch (freq) {
	199	case MPUPLL_M_1000:
	200	return &dpll_mpu_opp[ind][5];
	201	case MPUPLL_M_800:
	202	return &dpll_mpu_opp[ind][4];
	203	case MPUPLL_M_720:
	204	return &dpll_mpu_opp[ind][3];
	205	case MPUPLL_M_600:
	206	return &dpll_mpu_opp[ind][2];
	207	case MPUPLL_M_500:
	208	return &dpll_mpu_opp100;
	209	case MPUPLL_M_300:
	210	return &dpll_mpu_opp[ind][0];
	211	}
	212
	213	return &dpll_mpu_opp[ind][0];
	214	}
	215
	216	static void scale_vcores_generic(int freq)
	217	{
	218	int sil_rev, mpu_vdd;
	219
	220	/*
	221	* We use a TPS65910 PMIC. For all MPU frequencies we support we use a
	222	* CORE voltage of 1.10V. For MPU voltage we need to switch based on
	223	* the frequency we are running at.
	224	*/
	225	if (power_tps65910_init(0))
	226	return;
	227
	228	/*
	229	* Depending on MPU clock and PG we will need a different
	230	* VDD to drive at that speed.
	231	*/
	232	sil_rev = readl(&cdev->deviceid) >> 28;
	233	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq);
	234
	235	/* Tell the TPS65910 to use i2c */
	236	tps65910_set_i2c_control();
	237
	238	/* First update MPU voltage. */
	239	if (tps65910_voltage_update(MPU, mpu_vdd))
	240	return;
	241
	242	/* Second, update the CORE voltage. */
	243	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_0))
	244	return;
	245	}
	246
	247	void scale_vcores(void)
	248	{
	249	int freq;
250
251	freq = am335x_get_efuse_mpu_max_freq(cdev);
252	scale_vcores_generic(freq);
253	}
254
255	void set_uart_mux_conf(void)
256	{
257	enable_uart0_pin_mux();
258	}
259
260	void set_mux_conf_regs(void)
261	{
262	enable_i2c0_pin_mux();
263	enable_board_pin_mux();
264	}
265	#endif
266
267	/*
268	* Basic board specific setup. Pinmux has been handled already.
269	*/
270	int board_init(void)
271	{
aa6e94de	272	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
6e171b66 NF	273	return 0;
	274	}
	275
	276	#ifdef CONFIG_OF_BOARD_SETUP
b75d8dc5	277	int ft_board_setup(void blob, struct bd_info bd)
6e171b66 NF	278	{
	279	#ifdef CONFIG_FDT_FIXUP_PARTITIONS
	280	static const struct node_info nodes[] = {
	281	{ "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
	282	};
	283
	284	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
	285	#endif
	286	return 0;
	287	}
	288	#endif