[thirdparty/u-boot.git] / board / phytium / pomelo / pomelo.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2021
 * lixinde         <lixinde@phytium.com.cn>
 * weichangzheng   <weichangzheng@phytium.com.cn>
 */

#include <stdio.h>
#include <command.h>
#include <event.h>
#include <init.h>
#include <asm/armv8/mmu.h>
#include <asm/io.h>
#include <linux/arm-smccc.h>
#include <scsi.h>
#include <init.h>
#include <asm/u-boot.h>
#include "cpu.h"

DECLARE_GLOBAL_DATA_PTR;

int dram_init(void)
{
	debug("Phytium ddr init\n");
	ddr_init();

	gd->mem_clk = 0;
	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 0x7b000000);

	sec_init();
	debug("PBF relocate done\n");

	return 0;
}

int board_init(void)
{
	return 0;
}

void reset_cpu(void)
{
	struct arm_smccc_res res;

	debug("run in reset cpu\n");
	arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
	if (res.a0 != 0)
		panic("reset cpu error, %lx\n", res.a0);
}

int mach_cpu_init(void)
{
	check_reset();
	return 0;
}

int board_early_init_f(void)
{
	pcie_init();
	return 0;
}

static struct mm_region pomelo_mem_map[] = {
	{
		.virt = 0x0UL,
		.phys = 0x0UL,
		.size = 0x80000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
				 PTE_BLOCK_NON_SHARE |
				 PTE_BLOCK_PXN |
				 PTE_BLOCK_UXN
	},
	{
		.virt = 0x80000000UL,
		.phys = 0x80000000UL,
		.size = 0x7b000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
				 PTE_BLOCK_NS |
				 PTE_BLOCK_INNER_SHARE
	},
	{
		0,
	}
};

struct mm_region *mem_map = pomelo_mem_map;

int __asm_flush_l3_dcache(void)
{
	int i, pstate;

	for (i = 0; i < HNF_COUNT; i++)
		writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
	for (i = 0; i < HNF_COUNT; i++) {
		do {
			pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
		} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
	}

	for (i = 0; i < HNF_COUNT; i++)
		writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);

	return 0;
}

static int last_stage_init(void)
{
	int ret;

	/* pci e */
	pci_init();
	/* scsi scan */
	ret = scsi_scan(true);
	if (ret) {
		printf("scsi scan failed\n");
		return CMD_RET_FAILURE;
	}
	return ret;
}
EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);
Commit	Line	Data
b9d0f00a	1	// SPDX-License-Identifier: GPL-2.0+
	2	/*
	3	* Copyright (C) 2021
	4	* lixinde <lixinde@phytium.com.cn>
	5	* weichangzheng <weichangzheng@phytium.com.cn>
	6	*/
	7
	8	#include <stdio.h>
	9	#include <command.h>
91caa3bb	10	#include <event.h>
b9d0f00a	11	#include <init.h>
	12	#include <asm/armv8/mmu.h>
	13	#include <asm/io.h>
	14	#include <linux/arm-smccc.h>
	15	#include <scsi.h>
	16	#include <init.h>
d678a59d	17	#include <asm/u-boot.h>
b9d0f00a	18	#include "cpu.h"
	19
	20	DECLARE_GLOBAL_DATA_PTR;
	21
	22	int dram_init(void)
	23	{
	24	debug("Phytium ddr init\n");
	25	ddr_init();
	26
	27	gd->mem_clk = 0;
aa6e94de	28	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, 0x7b000000);
b9d0f00a	29
	30	sec_init();
	31	debug("PBF relocate done\n");
	32
	33	return 0;
	34	}
	35
	36	int board_init(void)
	37	{
	38	return 0;
	39	}
	40
	41	void reset_cpu(void)
	42	{
	43	struct arm_smccc_res res;
	44
	45	debug("run in reset cpu\n");
	46	arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res);
	47	if (res.a0 != 0)
	48	panic("reset cpu error, %lx\n", res.a0);
	49	}
	50
	51	int mach_cpu_init(void)
	52	{
	53	check_reset();
	54	return 0;
	55	}
	56
	57	int board_early_init_f(void)
	58	{
	59	pcie_init();
	60	return 0;
	61	}
	62
	63	static struct mm_region pomelo_mem_map[] = {
	64	{
	65	.virt = 0x0UL,
	66	.phys = 0x0UL,
	67	.size = 0x80000000UL,
	68	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	69	PTE_BLOCK_NON_SHARE \|
	70	PTE_BLOCK_PXN \|
	71	PTE_BLOCK_UXN
	72	},
	73	{
	74	.virt = 0x80000000UL,
	75	.phys = 0x80000000UL,
	76	.size = 0x7b000000UL,
	77	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	78	PTE_BLOCK_NS \|
	79	PTE_BLOCK_INNER_SHARE
	80	},
	81	{
	82	0,
	83	}
	84	};
	85
	86	struct mm_region *mem_map = pomelo_mem_map;
	87
	88	int __asm_flush_l3_dcache(void)
	89	{
	90	int i, pstate;
	91
	92	for (i = 0; i < HNF_COUNT; i++)
93	writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE);
94	for (i = 0; i < HNF_COUNT; i++) {
95	do {
96	pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE);
97	} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2));
98	}
99
100	for (i = 0; i < HNF_COUNT; i++)
101	writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE);
102
103	return 0;
104	}
105
91caa3bb	106	static int last_stage_init(void)
b9d0f00a	107	{
	108	int ret;
	109
	110	/* pci e */
	111	pci_init();
	112	/* scsi scan */
	113	ret = scsi_scan(true);
	114	if (ret) {
	115	printf("scsi scan failed\n");
	116	return CMD_RET_FAILURE;
	117	}
	118	return ret;
	119	}
91caa3bb	120	EVENT_SPY_SIMPLE(EVT_LAST_STAGE_INIT, last_stage_init);