[people/ms/u-boot.git] / board / prodrive / alpr / alpr.c

/*
 * (C) Copyright 2006
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>
#include <ppc4xx_enet.h>
#include <miiphy.h>

DECLARE_GLOBAL_DATA_PTR;

extern int alpr_fpga_init(void);

int board_early_init_f (void)
{
	/*-------------------------------------------------------------------------
	 * Initialize EBC CONFIG
	 *-------------------------------------------------------------------------*/
	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
	      EBC_CFG_PTD_DISABLE | EBC_CFG_RTC_64PERCLK |
	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	mtdcr (uic0sr, 0xffffffff);	/* clear all */
	mtdcr (uic0er, 0x00000000);	/* disable all */
	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
	mtdcr (uic0pr, 0xfffffe03);	/* per manual */
	mtdcr (uic0tr, 0x01c00000);	/* per manual */
	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (uic0sr, 0xffffffff);	/* clear all */

	mtdcr (uic1sr, 0xffffffff);	/* clear all */
	mtdcr (uic1er, 0x00000000);	/* disable all */
	mtdcr (uic1cr, 0x00000000);	/* all non-critical */
	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */
	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */
	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (uic1sr, 0xffffffff);	/* clear all */

	mtdcr (uic2sr, 0xffffffff);	/* clear all */
	mtdcr (uic2er, 0x00000000);	/* disable all */
	mtdcr (uic2cr, 0x00000000);	/* all non-critical */
	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */
	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */
	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr (uic2sr, 0xffffffff);	/* clear all */

	mtdcr (uicb0sr, 0xfc000000); /* clear all */
	mtdcr (uicb0er, 0x00000000); /* disable all */
	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
	mtdcr (uicb0pr, 0xfc000000); /* */
	mtdcr (uicb0tr, 0x00000000); /* */
	mtdcr (uicb0vr, 0x00000001); /* */

	/* Setup GPIO/IRQ multiplexing */
	mtsdr(sdr_pfc0, 0x01a03e00);

	return 0;
}

int last_stage_init(void)
{
	unsigned short reg;

	/*
	 * Configure LED's of both Marvell 88E1111 PHY's
	 *
	 * This has to be done after the 4xx ethernet driver is loaded,
	 * so "last_stage_init()" is the right place.
	 */
	miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, &reg);
	reg |= 0x0001;
	miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
	miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, &reg);
	reg |= 0x0001;
	miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);

	return 0;
}

static int board_rev(void)
{
	int rev;
	u32 pfc0;

	/* Setup GPIO14 & 15 as GPIO */
	mfsdr(sdr_pfc0, pfc0);
	pfc0 |= CFG_GPIO_REV0 | CFG_GPIO_REV1;
	mtsdr(sdr_pfc0, pfc0);

	/* Setup as input */
	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0));
	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV0));

	rev = (in32(GPIO0_IR) >> 16) & 0x3;

	/* Setup GPIO14 & 15 as non GPIO again */
	mfsdr(sdr_pfc0, pfc0);
	pfc0 &= ~(CFG_GPIO_REV0 | CFG_GPIO_REV1);
	mtsdr(sdr_pfc0, pfc0);

	return rev;
}

int checkboard (void)
{
	char *s = getenv ("serial#");

	printf ("Board: ALPR");
	if (s != NULL) {
		puts (", serial# ");
		puts (s);
	}
	printf(" (Rev. %d)\n", board_rev());

	return (0);
}

#if defined(CFG_DRAM_TEST)
int testdram (void)
{
	uint *pstart = (uint *) 0x00000000;
	uint *pend = (uint *) 0x08000000;
	uint *p;

	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf ("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}
	return 0;
}
#endif

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller * hose )
{
	unsigned long strap;

	/*--------------------------------------------------------------------------+
	 *	The ocotea board is always configured as the host & requires the
	 *	PCI arbiter to be enabled.
	 *--------------------------------------------------------------------------*/
	mfsdr(sdr_sdstp1, strap);
	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
		printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
		return 0;
	}

	/* FPGA Init */
	alpr_fpga_init ();

	return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
	/*--------------------------------------------------------------------------+
	 * Disable everything
	 *--------------------------------------------------------------------------*/
	out32r( PCIX0_PIM0SA, 0 ); /* disable */
	out32r( PCIX0_PIM1SA, 0 ); /* disable */
	out32r( PCIX0_PIM2SA, 0 ); /* disable */
	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */

	/*--------------------------------------------------------------------------+
	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
	 * options to not support sizes such as 128/256 MB.
	 *--------------------------------------------------------------------------*/
	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
	out32r( PCIX0_PIM0LAH, 0 );
	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );

	out32r( PCIX0_BAR0, 0 );

	/*--------------------------------------------------------------------------+
	 * Program the board's subsystem id/vendor id
	 *--------------------------------------------------------------------------*/
	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );

	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */

/*************************************************************************
 *  is_pci_host
 *
 *	This routine is called to determine if a pci scan should be
 *	performed. With various hardware environments (especially cPCI and
 *	PPMC) it's insufficient to depend on the state of the arbiter enable
 *	bit in the strap register, or generic host/adapter assumptions.
 *
 *	Rather than hard-code a bad assumption in the general 440 code, the
 *	440 pci code requires the board to decide at runtime.
 *
 *	Return 0 for adapter mode, non-zero for host (monarch) mode.
 *
 *
 ************************************************************************/
#if defined(CONFIG_PCI)

static void wait_for_pci_ready(void)
{
	/*
	 * Configure EREADY as input
	 */
	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY);
	udelay(1000);

	for (;;) {
		if (in32(GPIO0_IR) & CFG_GPIO_EREADY)
			return;
	}

}

int is_pci_host(struct pci_controller *hose)
{
	wait_for_pci_ready();
	return 1;		/* return 1 for host controller */
}
#endif /* defined(CONFIG_PCI) */

/*************************************************************************
 *  pci_master_init
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
	/*--------------------------------------------------------------------------+
	  | PowerPC440 PCI Master configuration.
	  | Map PLB/processor addresses to PCI memory space.
	  |   PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
	  |   Use byte reversed out routines to handle endianess.
	  | Make this region non-prefetchable.
	  +--------------------------------------------------------------------------*/
	out32r( PCIX0_POM0SA, 0 ); /* disable */
	out32r( PCIX0_POM1SA, 0 ); /* disable */
	out32r( PCIX0_POM2SA, 0 ); /* disable */

	out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
	out32r(PCIX0_POM0LAH, 0x00000003);	/* PMM0 Local Address */
	out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
	out32r(PCIX0_POM0PCIAH, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1);	/* 256MB + enable region */

	out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
	out32r(PCIX0_POM1LAH, 0x00000003);	/* PMM0 Local Address */
	out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
	out32r(PCIX0_POM1PCIAH, 0x00000000);	/* PMM0 PCI High Address */
	out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1);	/* 256MB + enable region */
}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */

#ifdef CONFIG_POST
/*
 * Returns 1 if keys pressed to start the power-on long-running tests
 * Called from board_init_f().
 */
int post_hotkeys_pressed(void)
{

	return (ctrlc());
}
#endif
Commit	Line	Data
899620c2 SR	1	/*
	2	* (C) Copyright 2006
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24
	25	#include <common.h>
	26	#include <asm/processor.h>
	27	#include <spd_sdram.h>
	28	#include <ppc4xx_enet.h>
1c2ce226	29	#include <miiphy.h>
899620c2 SR	30
	31	DECLARE_GLOBAL_DATA_PTR;
	32
	33	extern int alpr_fpga_init(void);
	34
	35	int board_early_init_f (void)
	36	{
1c2ce226 SR	37	/*-------------------------------------------------------------------------
	38	* Initialize EBC CONFIG
	39	-------------------------------------------------------------------------/
5bc528fa SR	40	mtebc(xbcfg, EBC_CFG_LE_UNLOCK \|
	41	EBC_CFG_PTD_DISABLE \| EBC_CFG_RTC_64PERCLK \|
	42	EBC_CFG_ATC_PREVIOUS \| EBC_CFG_DTC_PREVIOUS \|
	43	EBC_CFG_CTC_PREVIOUS \| EBC_CFG_EMC_NONDEFAULT \|
	44	EBC_CFG_PME_DISABLE \| EBC_CFG_PR_32);
899620c2 SR	45
	46	/*--------------------------------------------------------------------
	47	* Setup the interrupt controller polarities, triggers, etc.
	48	-------------------------------------------------------------------/
	49	mtdcr (uic0sr, 0xffffffff); /* clear all */
	50	mtdcr (uic0er, 0x00000000); /* disable all */
	51	mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
1c2ce226 SR	52	mtdcr (uic0pr, 0xfffffe03); /* per manual */
1c2ce226 SR	53	mtdcr (uic0tr, 0x01c00000); /* per manual */
899620c2 SR	54	mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */
	55	mtdcr (uic0sr, 0xffffffff); /* clear all */
	56
	57	mtdcr (uic1sr, 0xffffffff); /* clear all */
	58	mtdcr (uic1er, 0x00000000); /* disable all */
	59	mtdcr (uic1cr, 0x00000000); /* all non-critical */
	60	mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */
	61	mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */
	62	mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
	63	mtdcr (uic1sr, 0xffffffff); /* clear all */
	64
	65	mtdcr (uic2sr, 0xffffffff); /* clear all */
	66	mtdcr (uic2er, 0x00000000); /* disable all */
	67	mtdcr (uic2cr, 0x00000000); /* all non-critical */
	68	mtdcr (uic2pr, 0xffffffff); /* per ref-board manual */
	69	mtdcr (uic2tr, 0x00ff8c0f); /* per ref-board manual */
	70	mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
	71	mtdcr (uic2sr, 0xffffffff); /* clear all */
	72
	73	mtdcr (uicb0sr, 0xfc000000); /* clear all */
	74	mtdcr (uicb0er, 0x00000000); /* disable all */
	75	mtdcr (uicb0cr, 0x00000000); /* all non-critical */
	76	mtdcr (uicb0pr, 0xfc000000); /* */
	77	mtdcr (uicb0tr, 0x00000000); /* */
	78	mtdcr (uicb0vr, 0x00000001); /* */
1c2ce226 SR	79
	80	/* Setup GPIO/IRQ multiplexing */
	81	mtsdr(sdr_pfc0, 0x01a03e00);
899620c2 SR	82
	83	return 0;
	84	}
	85
1c2ce226 SR	86	int last_stage_init(void)
	87	{
	88	unsigned short reg;
	89
	90	/*
	91	* Configure LED's of both Marvell 88E1111 PHY's
	92	*
	93	* This has to be done after the 4xx ethernet driver is loaded,
	94	* so "last_stage_init()" is the right place.
	95	*/
	96	miiphy_read("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, &reg);
	97	reg \|= 0x0001;
	98	miiphy_write("ppc_4xx_eth2", CONFIG_PHY2_ADDR, 0x18, reg);
	99	miiphy_read("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, &reg);
	100	reg \|= 0x0001;
	101	miiphy_write("ppc_4xx_eth3", CONFIG_PHY3_ADDR, 0x18, reg);
	102
	103	return 0;
	104	}
	105
	106	static int board_rev(void)
	107	{
	108	int rev;
	109	u32 pfc0;
	110
	111	/* Setup GPIO14 & 15 as GPIO */
	112	mfsdr(sdr_pfc0, pfc0);
	113	pfc0 \|= CFG_GPIO_REV0 \| CFG_GPIO_REV1;
	114	mtsdr(sdr_pfc0, pfc0);
	115
	116	/* Setup as input */
	117	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 \| CFG_GPIO_REV0));
	118	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 \| CFG_GPIO_REV0));
	119
	120	rev = (in32(GPIO0_IR) >> 16) & 0x3;
	121
	122	/* Setup GPIO14 & 15 as non GPIO again */
	123	mfsdr(sdr_pfc0, pfc0);
	124	pfc0 &= ~(CFG_GPIO_REV0 \| CFG_GPIO_REV1);
	125	mtsdr(sdr_pfc0, pfc0);
	126
	127	return rev;
	128	}
	129
899620c2 SR	130	int checkboard (void)
	131	{
	132	char *s = getenv ("serial#");
	133
	134	printf ("Board: ALPR");
	135	if (s != NULL) {
	136	puts (", serial# ");
	137	puts (s);
	138	}
1c2ce226	139	printf(" (Rev. %d)\n", board_rev());
899620c2 SR	140
	141	return (0);
	142	}
	143
	144	#if defined(CFG_DRAM_TEST)
	145	int testdram (void)
	146	{
	147	uint pstart = (uint ) 0x00000000;
	148	uint pend = (uint ) 0x08000000;
	149	uint *p;
	150
	151	for (p = pstart; p < pend; p++)
	152	*p = 0xaaaaaaaa;
	153
	154	for (p = pstart; p < pend; p++) {
	155	if (*p != 0xaaaaaaaa) {
	156	printf ("SDRAM test fails at: %08x\n", (uint) p);
	157	return 1;
	158	}
	159	}
	160
	161	for (p = pstart; p < pend; p++)
	162	*p = 0x55555555;
	163
	164	for (p = pstart; p < pend; p++) {
	165	if (*p != 0x55555555) {
	166	printf ("SDRAM test fails at: %08x\n", (uint) p);
	167	return 1;
	168	}
	169	}
	170	return 0;
	171	}
	172	#endif
	173
	174	/*************************************************************************
	175	* pci_pre_init
	176	*
	177	* This routine is called just prior to registering the hose and gives
	178	* the board the opportunity to check things. Returning a value of zero
	179	* indicates that things are bad & PCI initialization should be aborted.
	180	*
	181	* Different boards may wish to customize the pci controller structure
	182	* (add regions, override default access routines, etc) or perform
	183	* certain pre-initialization actions.
	184	*
	185	************************************************************************/
	186	#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
	187	int pci_pre_init(struct pci_controller * hose )
	188	{
	189	unsigned long strap;
	190
	191	/*--------------------------------------------------------------------------+
	192	* The ocotea board is always configured as the host & requires the
	193	* PCI arbiter to be enabled.
	194	--------------------------------------------------------------------------/
	195	mfsdr(sdr_sdstp1, strap);
	196	if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
	197	printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
	198	return 0;
	199	}
	200
	201	/* FPGA Init */
	202	alpr_fpga_init ();
	203
204	return 1;
205	}
206	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
207
208	/*************************************************************************
209	* pci_target_init
210	*
211	* The bootstrap configuration provides default settings for the pci
212	* inbound map (PIM). But the bootstrap config choices are limited and
213	* may not be sufficient for a given board.
214	*
215	************************************************************************/
216	#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
217	void pci_target_init(struct pci_controller * hose )
218	{
219	/*--------------------------------------------------------------------------+
220	* Disable everything
221	--------------------------------------------------------------------------/
222	out32r( PCIX0_PIM0SA, 0 ); /* disable */
223	out32r( PCIX0_PIM1SA, 0 ); /* disable */
224	out32r( PCIX0_PIM2SA, 0 ); /* disable */
225	out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
226
227	/*--------------------------------------------------------------------------+
228	* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
229	* options to not support sizes such as 128/256 MB.
230	--------------------------------------------------------------------------/
231	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
232	out32r( PCIX0_PIM0LAH, 0 );
233	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) \| 1 );
234
235	out32r( PCIX0_BAR0, 0 );
236
237	/*--------------------------------------------------------------------------+
238	* Program the board's subsystem id/vendor id
239	--------------------------------------------------------------------------/
240	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
241	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
242
243	out16r( PCIX0_CMD, in16r(PCIX0_CMD) \| PCI_COMMAND_MEMORY \| PCI_COMMAND_MASTER);
244	}
245	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
246
247	/*************************************************************************
248	* is_pci_host
249	*
250	* This routine is called to determine if a pci scan should be
251	* performed. With various hardware environments (especially cPCI and
252	* PPMC) it's insufficient to depend on the state of the arbiter enable
253	* bit in the strap register, or generic host/adapter assumptions.
254	*
255	* Rather than hard-code a bad assumption in the general 440 code, the
256	* 440 pci code requires the board to decide at runtime.
257	*
258	* Return 0 for adapter mode, non-zero for host (monarch) mode.
259	*
260	*
261	************************************************************************/
262	#if defined(CONFIG_PCI)
1c2ce226 SR	263
	264	static void wait_for_pci_ready(void)
	265	{
	266	/*
	267	* Configure EREADY as input
	268	*/
	269	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY);
	270	udelay(1000);
	271
	272	for (;;) {
	273	if (in32(GPIO0_IR) & CFG_GPIO_EREADY)
	274	return;
	275	}
	276
	277	}
	278
899620c2 SR	279	int is_pci_host(struct pci_controller *hose)
899620c2 SR	280	{
1c2ce226 SR	281	wait_for_pci_ready();
1c2ce226 SR	282	return 1; /* return 1 for host controller */
899620c2 SR	283	}
	284	#endif /* defined(CONFIG_PCI) */
	285
	286	/*************************************************************************
	287	* pci_master_init
	288	*
	289	************************************************************************/
	290	#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
	291	void pci_master_init(struct pci_controller *hose)
	292	{
899620c2 SR	293	/*--------------------------------------------------------------------------+
	294	\| PowerPC440 PCI Master configuration.
	295	\| Map PLB/processor addresses to PCI memory space.
	296	\| PLB address 0xA0000000-0xCFFFFFFF ==> PCI address 0x80000000-0xCFFFFFFF
	297	\| Use byte reversed out routines to handle endianess.
	298	\| Make this region non-prefetchable.
	299	+--------------------------------------------------------------------------*/
	300	out32r( PCIX0_POM0SA, 0 ); /* disable */
	301	out32r( PCIX0_POM1SA, 0 ); /* disable */
	302	out32r( PCIX0_POM2SA, 0 ); /* disable */
	303
	304	out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE); /* PMM0 Local Address */
	305	out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */
	306	out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
	307	out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */
	308	out32r(PCIX0_POM0SA, ~(0x10000000 - 1) \| 1); /* 256MB + enable region */
	309
	310	out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
	311	out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */
	312	out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
	313	out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */
	314	out32r(PCIX0_POM1SA, ~(0x10000000 - 1) \| 1); /* 256MB + enable region */
899620c2 SR	315	}
	316	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
	317
	318	#ifdef CONFIG_POST
	319	/*
	320	* Returns 1 if keys pressed to start the power-on long-running tests
	321	* Called from board_init_f().
	322	*/
	323	int post_hotkeys_pressed(void)
	324	{
	325
	326	return (ctrlc());
	327	}
	328	#endif