[people/ms/u-boot.git] / board / prodrive / alpr / fpga.c

/*
 * (C) Copyright 2006
 * Heiko Schocher, DENX Software Engineering, hs@denx.de
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

/*
 * Altera FPGA configuration support for the ALPR computer from prodrive
 */

#include <common.h>
#include <altera.h>
#include <ACEX1K.h>
#include <command.h>
#include <asm-ppc/processor.h>
#include <ppc440.h>
#include "fpga.h"

DECLARE_GLOBAL_DATA_PTR;

#if defined(CONFIG_FPGA)

#ifdef FPGA_DEBUG
#define	PRINTF(fmt,args...)	printf (fmt ,##args)
#else
#define	PRINTF(fmt,args...)
#endif

static unsigned long regval;

#define SET_GPIO_REG_0(reg, bit) {				\
		regval = in32(reg);				\
		regval &= ~(0x80000000 >> bit);			\
		out32(reg, regval);				\
	}

#define SET_GPIO_REG_1(reg, bit) {				\
		regval = in32(reg);				\
		regval |= (0x80000000 >> bit);			\
		out32(reg, regval);				\
	}

#define	SET_GPIO_0(bit)		SET_GPIO_REG_0(GPIO0_OR, bit)
#define	SET_GPIO_1(bit)		SET_GPIO_REG_1(GPIO0_OR, bit)

#define FPGA_PRG		(0x80000000 >> CONFIG_SYS_GPIO_PROG_EN)
#define FPGA_CONFIG		(0x80000000 >> CONFIG_SYS_GPIO_CONFIG)
#define FPGA_DATA		(0x80000000 >> CONFIG_SYS_GPIO_DATA)
#define FPGA_CLK		(0x80000000 >> CONFIG_SYS_GPIO_CLK)
#define OLD_VAL			(FPGA_PRG | FPGA_CONFIG)

#define SET_FPGA(data)		out32(GPIO0_OR, data)

#define FPGA_WRITE_1 {							\
		SET_FPGA(OLD_VAL | 0        | FPGA_DATA);  /* set data to 1  */	\
		SET_FPGA(OLD_VAL | FPGA_CLK | FPGA_DATA);} /* set data to 1  */

#define FPGA_WRITE_0 {							\
		SET_FPGA(OLD_VAL | 0        | 0        );   /* set data to 0  */ \
		SET_FPGA(OLD_VAL | FPGA_CLK | 0        );}  /* set data to 1  */

/* Plattforminitializations */
/* Here we have to set the FPGA Chain */
/* PROGRAM_PROG_EN	= HIGH */
/* PROGRAM_SEL_DPR	= LOW */
int fpga_pre_fn (int cookie)
{
	unsigned long	reg;

	reg = in32(GPIO0_IR);
	/* Enable the FPGA Chain */
	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN);
	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN);
	SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN);
	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR);
	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR);
	SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR));

	/* initialize the GPIO Pins */
	/* output */
	SET_GPIO_0(CONFIG_SYS_GPIO_CLK);
	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK);
	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK);

	/* output */
	SET_GPIO_0(CONFIG_SYS_GPIO_DATA);
	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA);
	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA);

	/* First we set STATUS to 0 then as an input */
	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
	SET_GPIO_0(CONFIG_SYS_GPIO_STATUS);
	SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);

	/* output */
	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG);
	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG);
	SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);

	/* input */
	SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON);
	SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON);
	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON);

	/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
	SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
	return FPGA_SUCCESS;
}

/* Set the state of CONFIG Pin */
int fpga_config_fn (int assert_config, int flush, int cookie)
{
	if (assert_config) {
		SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG);
	} else {
		SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
	}
	return FPGA_SUCCESS;
}

/* Returns the state of STATUS Pin */
int fpga_status_fn (int cookie)
{
	unsigned long	reg;

	reg = in32(GPIO0_IR);
	if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) {
		PRINTF("STATUS = HIGH\n");
		return FPGA_FAIL;
	}
	PRINTF("STATUS = LOW\n");
	return FPGA_SUCCESS;
}

/* Returns the state of CONF_DONE Pin */
int fpga_done_fn (int cookie)
{
	unsigned long	reg;
	reg = in32(GPIO0_IR);
	if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) {
		PRINTF("CONF_DON = HIGH\n");
		return FPGA_FAIL;
	}
	PRINTF("CONF_DON = LOW\n");
	return FPGA_SUCCESS;
}

/* writes the complete buffer to the FPGA
   writing the complete buffer in one function is much faster,
   then calling it for every bit */
int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
{
	size_t bytecount = 0;
	unsigned char *data = (unsigned char *) buf;
	unsigned char val=0;
	int		i;
	int len_40 = len / 40;

	while (bytecount < len) {
		val = data[bytecount++];
		i = 8;
		do {
			if (val & 0x01) {
				FPGA_WRITE_1;
			} else {
				FPGA_WRITE_0;
			}
			val >>= 1;
			i --;
		} while (i > 0);

#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
		if (bytecount % len_40 == 0) {
			putc ('.');		/* let them know we are alive */
#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
			if (ctrlc ())
				return FPGA_FAIL;
#endif
		}
#endif
	}
	return FPGA_SUCCESS;
}

/* called, when programming is aborted */
int fpga_abort_fn (int cookie)
{
	SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR));
	return FPGA_SUCCESS;
}

/* called, when programming was succesful */
int fpga_post_fn (int cookie)
{
	return fpga_abort_fn (cookie);
}

/* Note that these are pointers to code that is in Flash.  They will be
 * relocated at runtime.
 */
Altera_CYC2_Passive_Serial_fns fpga_fns = {
	fpga_pre_fn,
	fpga_config_fn,
	fpga_status_fn,
	fpga_done_fn,
	fpga_write_fn,
	fpga_abort_fn,
	fpga_post_fn
};

Altera_desc fpga[CONFIG_FPGA_COUNT] = {
	{Altera_CYC2,
	 passive_serial,
	 Altera_EP2C35_SIZE,
	 (void *) &fpga_fns,
	 NULL,
	 0}
};

/*
 * Initialize the fpga.  Return 1 on success, 0 on failure.
 */
int alpr_fpga_init (void)
{
	int i;

	PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);
	fpga_init (gd->reloc_off);

	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
		PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
		fpga_add (fpga_altera, &fpga[i]);
	}
	return 1;
}

#endif
Commit	Line	Data
899620c2 SR	1	/*
	2	* (C) Copyright 2006
	3	* Heiko Schocher, DENX Software Engineering, hs@denx.de
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*
	23	*/
	24
	25	/*
	26	* Altera FPGA configuration support for the ALPR computer from prodrive
	27	*/
	28
	29	#include <common.h>
	30	#include <altera.h>
	31	#include <ACEX1K.h>
	32	#include <command.h>
	33	#include <asm-ppc/processor.h>
	34	#include <ppc440.h>
	35	#include "fpga.h"
	36
	37	DECLARE_GLOBAL_DATA_PTR;
	38
1c2ce226	39	#if defined(CONFIG_FPGA)
899620c2 SR	40
	41	#ifdef FPGA_DEBUG
	42	#define PRINTF(fmt,args...) printf (fmt ,##args)
	43	#else
	44	#define PRINTF(fmt,args...)
	45	#endif
	46
1c2ce226	47	static unsigned long regval;
899620c2	48
1c2ce226 SR	49	#define SET_GPIO_REG_0(reg, bit) { \
	50	regval = in32(reg); \
	51	regval &= ~(0x80000000 >> bit); \
	52	out32(reg, regval); \
	53	}
899620c2	54
1c2ce226 SR	55	#define SET_GPIO_REG_1(reg, bit) { \
	56	regval = in32(reg); \
	57	regval \|= (0x80000000 >> bit); \
	58	out32(reg, regval); \
	59	}
899620c2	60
1c2ce226 SR	61	#define SET_GPIO_0(bit) SET_GPIO_REG_0(GPIO0_OR, bit)
1c2ce226 SR	62	#define SET_GPIO_1(bit) SET_GPIO_REG_1(GPIO0_OR, bit)
899620c2	63
6d0f6bcf JCPV	64	#define FPGA_PRG (0x80000000 >> CONFIG_SYS_GPIO_PROG_EN)
	65	#define FPGA_CONFIG (0x80000000 >> CONFIG_SYS_GPIO_CONFIG)
	66	#define FPGA_DATA (0x80000000 >> CONFIG_SYS_GPIO_DATA)
	67	#define FPGA_CLK (0x80000000 >> CONFIG_SYS_GPIO_CLK)
1c2ce226	68	#define OLD_VAL (FPGA_PRG \| FPGA_CONFIG)
899620c2	69
1c2ce226	70	#define SET_FPGA(data) out32(GPIO0_OR, data)
899620c2	71
1c2ce226 SR	72	#define FPGA_WRITE_1 { \
	73	SET_FPGA(OLD_VAL \| 0 \| FPGA_DATA); /* set data to 1 */ \
	74	SET_FPGA(OLD_VAL \| FPGA_CLK \| FPGA_DATA);} /* set data to 1 */
899620c2	75
1c2ce226 SR	76	#define FPGA_WRITE_0 { \
	77	SET_FPGA(OLD_VAL \| 0 \| 0 ); /* set data to 0 */ \
	78	SET_FPGA(OLD_VAL \| FPGA_CLK \| 0 );} /* set data to 1 */
899620c2 SR	79
	80	/* Plattforminitializations */
	81	/* Here we have to set the FPGA Chain */
	82	/* PROGRAM_PROG_EN = HIGH */
	83	/* PROGRAM_SEL_DPR = LOW */
	84	int fpga_pre_fn (int cookie)
	85	{
	86	unsigned long reg;
	87
	88	reg = in32(GPIO0_IR);
	89	/* Enable the FPGA Chain */
6d0f6bcf JCPV	90	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN);
	91	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN);
	92	SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN);
	93	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR);
	94	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR);
	95	SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR));
899620c2	96
1c2ce226	97	/* initialize the GPIO Pins */
899620c2	98	/* output */
6d0f6bcf JCPV	99	SET_GPIO_0(CONFIG_SYS_GPIO_CLK);
	100	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK);
	101	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK);
899620c2 SR	102
899620c2 SR	103	/* output */
6d0f6bcf JCPV	104	SET_GPIO_0(CONFIG_SYS_GPIO_DATA);
	105	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA);
	106	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA);
899620c2 SR	107
899620c2 SR	108	/* First we set STATUS to 0 then as an input */
6d0f6bcf JCPV	109	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
	110	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
	111	SET_GPIO_0(CONFIG_SYS_GPIO_STATUS);
	112	SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
	113	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
899620c2 SR	114
899620c2 SR	115	/* output */
6d0f6bcf JCPV	116	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG);
	117	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG);
	118	SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
899620c2 SR	119
899620c2 SR	120	/* input */
6d0f6bcf JCPV	121	SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON);
	122	SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON);
	123	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON);
899620c2 SR	124
899620c2 SR	125	/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
6d0f6bcf	126	SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
899620c2 SR	127	return FPGA_SUCCESS;
	128	}
	129
	130	/* Set the state of CONFIG Pin */
	131	int fpga_config_fn (int assert_config, int flush, int cookie)
	132	{
	133	if (assert_config) {
6d0f6bcf	134	SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG);
899620c2	135	} else {
6d0f6bcf	136	SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
899620c2 SR	137	}
	138	return FPGA_SUCCESS;
	139	}
	140
	141	/* Returns the state of STATUS Pin */
	142	int fpga_status_fn (int cookie)
	143	{
	144	unsigned long reg;
	145
	146	reg = in32(GPIO0_IR);
6d0f6bcf	147	if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) {
899620c2 SR	148	PRINTF("STATUS = HIGH\n");
	149	return FPGA_FAIL;
	150	}
	151	PRINTF("STATUS = LOW\n");
	152	return FPGA_SUCCESS;
	153	}
	154
	155	/* Returns the state of CONF_DONE Pin */
	156	int fpga_done_fn (int cookie)
	157	{
	158	unsigned long reg;
	159	reg = in32(GPIO0_IR);
6d0f6bcf	160	if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) {
899620c2 SR	161	PRINTF("CONF_DON = HIGH\n");
	162	return FPGA_FAIL;
	163	}
	164	PRINTF("CONF_DON = LOW\n");
	165	return FPGA_SUCCESS;
	166	}
	167
	168	/* writes the complete buffer to the FPGA
1c2ce226	169	writing the complete buffer in one function is much faster,
899620c2 SR	170	then calling it for every bit */
	171	int fpga_write_fn (void *buf, size_t len, int flush, int cookie)
	172	{
	173	size_t bytecount = 0;
	174	unsigned char data = (unsigned char ) buf;
	175	unsigned char val=0;
	176	int i;
1c2ce226	177	int len_40 = len / 40;
899620c2 SR	178
899620c2 SR	179	while (bytecount < len) {
1c2ce226	180	val = data[bytecount++];
899620c2 SR	181	i = 8;
	182	do {
	183	if (val & 0x01) {
	184	FPGA_WRITE_1;
	185	} else {
	186	FPGA_WRITE_0;
	187	}
	188	val >>= 1;
	189	i --;
	190	} while (i > 0);
	191
6d0f6bcf	192	#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
1c2ce226	193	if (bytecount % len_40 == 0) {
899620c2	194	putc ('.'); /* let them know we are alive */
6d0f6bcf	195	#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
1c2ce226 SR	196	if (ctrlc ())
	197	return FPGA_FAIL;
	198	#endif
	199	}
899620c2 SR	200	#endif
	201	}
	202	return FPGA_SUCCESS;
	203	}
	204
	205	/* called, when programming is aborted */
	206	int fpga_abort_fn (int cookie)
	207	{
6d0f6bcf	208	SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR));
899620c2 SR	209	return FPGA_SUCCESS;
	210	}
	211
	212	/* called, when programming was succesful */
	213	int fpga_post_fn (int cookie)
	214	{
	215	return fpga_abort_fn (cookie);
	216	}
	217
	218	/* Note that these are pointers to code that is in Flash. They will be
	219	* relocated at runtime.
	220	*/
	221	Altera_CYC2_Passive_Serial_fns fpga_fns = {
	222	fpga_pre_fn,
	223	fpga_config_fn,
	224	fpga_status_fn,
	225	fpga_done_fn,
	226	fpga_write_fn,
	227	fpga_abort_fn,
	228	fpga_post_fn
	229	};
	230
	231	Altera_desc fpga[CONFIG_FPGA_COUNT] = {
	232	{Altera_CYC2,
	233	passive_serial,
	234	Altera_EP2C35_SIZE,
	235	(void *) &fpga_fns,
	236	NULL,
	237	0}
	238	};
	239
	240	/*
	241	* Initialize the fpga. Return 1 on success, 0 on failure.
	242	*/
	243	int alpr_fpga_init (void)
	244	{
	245	int i;
	246
	247	PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);
	248	fpga_init (gd->reloc_off);
	249
	250	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
	251	PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
	252	fpga_add (fpga_altera, &fpga[i]);
	253	}
	254	return 1;
	255	}
	256
	257	#endif