[people/ms/u-boot.git] / board / prodrive / pdnb3 / pdnb3.c

/*
 * (C) Copyright 2006
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <command.h>
#include <malloc.h>
#include <asm/arch/ixp425.h>

DECLARE_GLOBAL_DATA_PTR;

/* predefine these here for FPGA programming (before including fpga.c) */
#define SET_FPGA(data)	*IXP425_GPIO_GPOUTR = (data)
#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
#define OLD_VAL		old_val

static unsigned long old_val = 0;

/*
 * include common fpga code (for prodrive boards)
 */
#include "../common/fpga.c"

/*
 * Miscelaneous platform dependent initialisations
 */
int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = 0x00000100;

	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);

	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);

	/*
	 * Setup GPIO's for FPGA programming
	 */
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);

	/*
	 * Setup GPIO's for interrupts
	 */
	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);

	/*
	 * Setup GPIO's for 33MHz clock output
	 */
	*IXP425_GPIO_GPCLKR = 0x01FF0000;
	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);

	/*
	 * Setup other chip select's
	 */
	*IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;

	return 0;
}

/*
 * Check Board Identity
 */
int checkboard(void)
{
	char buf[64];
	int i = getenv_f("serial#", buf, sizeof(buf));

	puts("Board: PDNB3");

	if (i > 0) {
		puts(", serial# ");
		puts(buf);
	}
	putc('\n');

	return (0);
}

int dram_init(void)
{
	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;

	return (0);
}

int do_fpga_boot(unsigned char *fpgadata)
{
	unsigned char *dst;
	int status;
	int index;
	int i;
	ulong len = CONFIG_SYS_MALLOC_LEN;

	/*
	 * Setup GPIO's for FPGA programming
	 */
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);

	/*
	 * Save value so no readback is required upon programming
	 */
	old_val = *IXP425_GPIO_GPOUTR;

	/*
	 * First try to decompress fpga image (gzip compressed?)
	 */
	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
		printf("Error: Image has to be gzipp'ed!\n");
		return -1;
	}

	status = fpga_boot(dst, len);
	if (status != 0) {
		printf("\nFPGA: Booting failed ");
		switch (status) {
		case ERROR_FPGA_PRG_INIT_LOW:
			printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_INIT_HIGH:
			printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
			break;
		case ERROR_FPGA_PRG_DONE:
			printf("(Timeout: DONE not high after programming FPGA)\n ");
			break;
		}

		/* display infos on fpgaimage */
		index = 15;
		for (i=0; i<4; i++) {
			len = dst[index];
			printf("FPGA: %s\n", &(dst[index+1]));
			index += len+3;
		}
		putc ('\n');
		/* delayed reboot */
		for (i=5; i>0; i--) {
			printf("Rebooting in %2d seconds \r",i);
			for (index=0;index<1000;index++)
				udelay(1000);
		}
		putc('\n');
		do_reset(NULL, 0, 0, NULL);
	}

	puts("FPGA:  ");

	/* display infos on fpgaimage */
	index = 15;
	for (i=0; i<4; i++) {
		len = dst[index];
		printf("%s ", &(dst[index+1]));
		index += len+3;
	}
	putc('\n');

	free(dst);

	/*
	 * Reset FPGA
	 */
	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
	udelay(10);
	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);

	return (0);
}

int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	ulong addr;

	if (argc < 2)
		return cmd_usage(cmdtp);

	addr = simple_strtoul(argv[1], NULL, 16);

	return do_fpga_boot((unsigned char *)addr);
}

U_BOOT_CMD(
	fpga,     2,     0,      do_fpga,
	"boot FPGA",
	"address size\n    - boot FPGA with gzipped image at <address>"
);

#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
extern struct pci_controller hose;
extern void pci_ixp_init(struct pci_controller * hose);

void pci_init_board(void)
{
	extern void pci_ixp_init (struct pci_controller *hose);

	pci_ixp_init(&hose);
}
#endif
Commit	Line	Data
ba94a1bb WD	1	/*
	2	* (C) Copyright 2006
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
ba94a1bb WD	6	*/
	7
	8	#include <common.h>
	9	#include <command.h>
	10	#include <malloc.h>
	11	#include <asm/arch/ixp425.h>
	12
	13	DECLARE_GLOBAL_DATA_PTR;
	14
ba94a1bb WD	15	/* predefine these here for FPGA programming (before including fpga.c) */
ba94a1bb WD	16	#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data)
6d0f6bcf JCPV	17	#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
6d0f6bcf JCPV	18	#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
ba94a1bb WD	19	#define OLD_VAL old_val
	20
	21	static unsigned long old_val = 0;
	22
	23	/*
	24	* include common fpga code (for prodrive boards)
	25	*/
	26	#include "../common/fpga.c"
	27
	28	/*
	29	* Miscelaneous platform dependent initialisations
	30	*/
ba94a1bb WD	31	int board_init(void)
ba94a1bb WD	32	{
ba94a1bb WD	33	/* adress of boot parameters */
	34	gd->bd->bi_boot_params = 0x00000100;
	35
6d0f6bcf JCPV	36	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
6d0f6bcf JCPV	37	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
ba94a1bb	38
6d0f6bcf JCPV	39	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
6d0f6bcf JCPV	40	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
ba94a1bb WD	41
	42	/*
	43	* Setup GPIO's for FPGA programming
	44	*/
6d0f6bcf JCPV	45	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
	46	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
	47	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
	48	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
	49	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
	50	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
	51	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
	52	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
ba94a1bb WD	53
	54	/*
	55	* Setup GPIO's for interrupts
	56	*/
6d0f6bcf JCPV	57	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
	58	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
	59	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
	60	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
	61	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
	62	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
	63	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
	64	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
ba94a1bb WD	65
	66	/*
	67	* Setup GPIO's for 33MHz clock output
	68	*/
	69	*IXP425_GPIO_GPCLKR = 0x01FF0000;
6d0f6bcf	70	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
ba94a1bb WD	71
	72	/*
	73	* Setup other chip select's
	74	*/
6d0f6bcf	75	*IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
ba94a1bb WD	76
	77	return 0;
	78	}
	79
	80	/*
	81	* Check Board Identity
	82	*/
	83	int checkboard(void)
	84	{
f0c0b3a9 WD	85	char buf[64];
f0c0b3a9 WD	86	int i = getenv_f("serial#", buf, sizeof(buf));
ba94a1bb WD	87
	88	puts("Board: PDNB3");
	89
f0c0b3a9	90	if (i > 0) {
ba94a1bb	91	puts(", serial# ");
f0c0b3a9	92	puts(buf);
ba94a1bb WD	93	}
	94	putc('\n');
	95
	96	return (0);
	97	}
	98
	99	int dram_init(void)
	100	{
	101	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
	102	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
	103
	104	return (0);
	105	}
	106
	107	int do_fpga_boot(unsigned char *fpgadata)
	108	{
	109	unsigned char *dst;
	110	int status;
	111	int index;
	112	int i;
6d0f6bcf	113	ulong len = CONFIG_SYS_MALLOC_LEN;
ba94a1bb WD	114
	115	/*
	116	* Setup GPIO's for FPGA programming
	117	*/
6d0f6bcf JCPV	118	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
	119	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
	120	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
ba94a1bb WD	121
	122	/*
	123	* Save value so no readback is required upon programming
	124	*/
	125	old_val = *IXP425_GPIO_GPOUTR;
	126
	127	/*
	128	* First try to decompress fpga image (gzip compressed?)
	129	*/
6d0f6bcf JCPV	130	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
6d0f6bcf JCPV	131	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
ba94a1bb WD	132	printf("Error: Image has to be gzipp'ed!\n");
	133	return -1;
	134	}
	135
	136	status = fpga_boot(dst, len);
	137	if (status != 0) {
	138	printf("\nFPGA: Booting failed ");
	139	switch (status) {
	140	case ERROR_FPGA_PRG_INIT_LOW:
	141	printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
	142	break;
	143	case ERROR_FPGA_PRG_INIT_HIGH:
	144	printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
	145	break;
	146	case ERROR_FPGA_PRG_DONE:
	147	printf("(Timeout: DONE not high after programming FPGA)\n ");
	148	break;
	149	}
	150
	151	/* display infos on fpgaimage */
	152	index = 15;
	153	for (i=0; i<4; i++) {
	154	len = dst[index];
	155	printf("FPGA: %s\n", &(dst[index+1]));
	156	index += len+3;
	157	}
	158	putc ('\n');
	159	/* delayed reboot */
	160	for (i=5; i>0; i--) {
	161	printf("Rebooting in %2d seconds \r",i);
	162	for (index=0;index<1000;index++)
	163	udelay(1000);
	164	}
	165	putc('\n');
	166	do_reset(NULL, 0, 0, NULL);
	167	}
	168
	169	puts("FPGA: ");
	170
	171	/* display infos on fpgaimage */
	172	index = 15;
	173	for (i=0; i<4; i++) {
	174	len = dst[index];
	175	printf("%s ", &(dst[index+1]));
	176	index += len+3;
	177	}
	178	putc('\n');
	179
	180	free(dst);
	181
	182	/*
	183	* Reset FPGA
	184	*/
6d0f6bcf	185	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
ba94a1bb	186	udelay(10);
6d0f6bcf	187	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
ba94a1bb WD	188
	189	return (0);
	190	}
	191
54841ab5	192	int do_fpga(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
ba94a1bb WD	193	{
	194	ulong addr;
	195
47e26b1b WD	196	if (argc < 2)
47e26b1b WD	197	return cmd_usage(cmdtp);
ba94a1bb WD	198
	199	addr = simple_strtoul(argv[1], NULL, 16);
	200
	201	return do_fpga_boot((unsigned char *)addr);
	202	}
	203
	204	U_BOOT_CMD(
	205	fpga, 2, 0, do_fpga,
2fb2604d	206	"boot FPGA",
a89c33db	207	"address size\n - boot FPGA with gzipped image at <address>"
ba94a1bb WD	208	);
ba94a1bb WD	209
3fe00109	210	#if defined(CONFIG_CMD_PCI) \|\| defined(CONFIG_PCI)
ba94a1bb WD	211	extern struct pci_controller hose;
	212	extern void pci_ixp_init(struct pci_controller * hose);
	213
	214	void pci_init_board(void)
	215	{
	216	extern void pci_ixp_init (struct pci_controller *hose);
	217
	218	pci_ixp_init(&hose);
	219	}
	220	#endif