[people/ms/u-boot.git] / board / pxa255_idp / lowlevel_init.S

/*
 * Most of this taken from Redboot hal_platform_setup.h with cleanup
 *
 * NOTE: I haven't clean this up considerably, just enough to get it
 * running. See hal_platform_setup.h for the source. See
 * board/cradle/lowlevel_init.S for another PXA250 setup that is
 * much cleaner.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <version.h>
#include <asm/arch/pxa-regs.h>

DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE

/* wait for coprocessor write complete */
	.macro CPWAIT reg
	mrc  p15,0,\reg,c2,c0,0
	mov  \reg,\reg
	sub  pc,pc,#4
	.endm

/*
 *	Memory setup
 */
.globl lowlevel_init
lowlevel_init:

	mov      r10, lr

#ifdef DEBUG_BLINK_ENABLE
	/* 3rd blink */
	bl	blink
#endif

	/* Set up GPIO pins first ----------------------------------------- */
	ldr		r0,	=GPSR0
	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
	str		r1,   [r0]

	ldr		r0,	=GPSR1
	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
	str		r1,   [r0]

	ldr		r0,	=GPSR2
	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
	str		r1,   [r0]

	ldr		r0,	=GPCR0
	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
	str		r1,   [r0]

	ldr		r0,	=GPCR1
	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
	str		r1,   [r0]

	ldr		r0,	=GPCR2
	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
	str		r1,   [r0]

	ldr		r0,	=GPDR0
	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
	str		r1,   [r0]

	ldr		r0,	=GPDR1
	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
	str		r1,   [r0]

	ldr		r0,	=GPDR2
	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR0_L
	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR0_U
	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR1_L
	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR1_U
	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR2_L
	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
	str		r1,   [r0]

	ldr		r0,	=GAFR2_U
	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
	str		r1,   [r0]

	ldr	r0,	=PSSR		/* enable GPIO pins */
	ldr		r1,	=CONFIG_SYS_PSSR_VAL
	str		r1,   [r0]

#ifdef DEBUG_BLINK_ENABLE
	/* 4th debug blink */
	bl	blink
#endif

	/* ---------------------------------------------------------------- */
	/* Enable memory interface                                          */
	/*                                                                  */
	/* The sequence below is based on the recommended init steps        */
	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
	/* Chapter 10.                                                      */
	/* ---------------------------------------------------------------- */

	/* ---------------------------------------------------------------- */
	/* Step 1: Wait for at least 200 microsedonds to allow internal     */
	/*         clocks to settle. Only necessary after hard reset...     */
	/*         FIXME: can be optimized later                            */
	/* ---------------------------------------------------------------- */

	ldr r3, =OSCR			/* reset the OS Timer Count to zero */
	mov r2, #0
	str r2, [r3]
	ldr r4, =0x300			/* really 0x2E1 is about 200usec,   */
					/* so 0x300 should be plenty        */
1:
	ldr r2, [r3]
	cmp r4, r2
	bgt 1b

mem_init:

	ldr     r1,  =MEMC_BASE		/* get memory controller base addr. */

	/* ---------------------------------------------------------------- */
	/* Step 2a: Initialize Asynchronous static memory controller        */
	/* ---------------------------------------------------------------- */

	/* MSC registers: timing, bus width, mem type                       */

	/* MSC0: nCS(0,1)                                                   */
	ldr     r2,   =CONFIG_SYS_MSC0_VAL
	str     r2,   [r1, #MSC0_OFFSET]
	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
						/* that data latches        */
	/* MSC1: nCS(2,3)                                                   */
	ldr     r2,  =CONFIG_SYS_MSC1_VAL
	str     r2,  [r1, #MSC1_OFFSET]
	ldr     r2,  [r1, #MSC1_OFFSET]

	/* MSC2: nCS(4,5)                                                   */
	ldr     r2,  =CONFIG_SYS_MSC2_VAL
	str     r2,  [r1, #MSC2_OFFSET]
	ldr     r2,  [r1, #MSC2_OFFSET]

	/* ---------------------------------------------------------------- */
	/* Step 2b: Initialize Card Interface                               */
	/* ---------------------------------------------------------------- */

	/* MECR: Memory Expansion Card Register                             */
	ldr     r2,  =CONFIG_SYS_MECR_VAL
	str     r2,  [r1, #MECR_OFFSET]
	ldr	r2,	[r1, #MECR_OFFSET]

	/* MCMEM0: Card Interface slot 0 timing                             */
	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
	str     r2,  [r1, #MCMEM0_OFFSET]
	ldr	r2,	[r1, #MCMEM0_OFFSET]

	/* MCMEM1: Card Interface slot 1 timing                             */
	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
	str     r2,  [r1, #MCMEM1_OFFSET]
	ldr	r2,	[r1, #MCMEM1_OFFSET]

	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
	str     r2,  [r1, #MCATT0_OFFSET]
	ldr	r2,	[r1, #MCATT0_OFFSET]

	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
	str     r2,  [r1, #MCATT1_OFFSET]
	ldr	r2,	[r1, #MCATT1_OFFSET]

	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
	str     r2,  [r1, #MCIO0_OFFSET]
	ldr	r2,	[r1, #MCIO0_OFFSET]

	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
	str     r2,  [r1, #MCIO1_OFFSET]
	ldr	r2,	[r1, #MCIO1_OFFSET]

#ifdef DEBUG_BLINK_ENABLE
	/* 5th blink */
	bl	blink
#endif

	/* ---------------------------------------------------------------- */
	/* Step 2c: Write FLYCNFG  FIXME: what's that???                    */
	/* ---------------------------------------------------------------- */

	/* ---------------------------------------------------------------- */
	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0)              */
	/* ---------------------------------------------------------------- */

	/* Before accessing MDREFR we need a valid DRI field, so we set     */
	/* this to power on defaults + DRI field.                           */

	ldr     r3,     =CONFIG_SYS_MDREFR_VAL
	ldr     r2,     =0xFFF
	and     r3,     r3,  r2
	ldr	r4,	=0x03ca4000
	orr     r4,     r4,  r3
	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
	ldr     r4,  [r1, #MDREFR_OFFSET]

	/* Note: preserve the mdrefr value in r4                            */

	/* ---------------------------------------------------------------- */
	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
	/* ---------------------------------------------------------------- */

	/* Initialize SXCNFG register. Assert the enable bits               */

	/* Write SXMRS to cause an MRS command to all enabled banks of      */
	/* synchronous static memory. Note that SXLCR need not be written   */
	/* at this time.                                                    */

	/* FIXME: we use async mode for now                                 */

	/* ---------------------------------------------------------------- */
	/* Step 4: Initialize SDRAM                                         */
	/* ---------------------------------------------------------------- */

	/* set MDREFR according to user define with exception of a few bits */

	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
	orr	r4,	r4,	#(MDREFR_SLFRSH)
	bic	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
	ldr     r4,  [r1, #MDREFR_OFFSET]

	/* Step 4b: de-assert MDREFR:SLFRSH.                                */

	bic	r4,	r4,	#(MDREFR_SLFRSH)
	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
	ldr     r4,  [r1, #MDREFR_OFFSET]

	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */

	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
	ldr     r4,     [r1, #MDREFR_OFFSET]


	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
	/*          configure but not enable each SDRAM partition pair.     */

	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)

	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
	ldr     r4,     [r1, #MDCNFG_OFFSET]

	/* Step 4e: Wait for the clock to the SDRAMs to stabilize,          */
Commit	Line	Data
70a2047f WD	1	/*
	2	* Most of this taken from Redboot hal_platform_setup.h with cleanup
	3	*
	4	* NOTE: I haven't clean this up considerably, just enough to get it
	5	* running. See hal_platform_setup.h for the source. See
2a4741d9	6	* board/cradle/lowlevel_init.S for another PXA250 setup that is
70a2047f WD	7	* much cleaner.
	8	*
	9	* See file CREDITS for list of people who contributed to this
	10	* project.
	11	*
	12	* This program is free software; you can redistribute it and/or
	13	* modify it under the terms of the GNU General Public License as
	14	* published by the Free Software Foundation; either version 2 of
	15	* the License, or (at your option) any later version.
	16	*
	17	* This program is distributed in the hope that it will be useful,
	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	* GNU General Public License for more details.
	21	*
	22	* You should have received a copy of the GNU General Public License
	23	* along with this program; if not, write to the Free Software
	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	* MA 02111-1307 USA
	26	*/
	27
	28	#include <config.h>
	29	#include <version.h>
	30	#include <asm/arch/pxa-regs.h>
	31
6d0f6bcf	32	DRAM_SIZE: .long CONFIG_SYS_DRAM_SIZE
70a2047f WD	33
	34	/* wait for coprocessor write complete */
	35	.macro CPWAIT reg
	36	mrc p15,0,\reg,c2,c0,0
	37	mov \reg,\reg
	38	sub pc,pc,#4
	39	.endm
	40
	41	/*
53677ef1	42	* Memory setup
70a2047f	43	*/
2a4741d9 MZ	44	.globl lowlevel_init
2a4741d9 MZ	45	lowlevel_init:
70a2047f WD	46
	47	mov r10, lr
	48
	49	#ifdef DEBUG_BLINK_ENABLE
	50	/* 3rd blink */
	51	bl blink
	52	#endif
	53
	54	/* Set up GPIO pins first ----------------------------------------- */
	55	ldr r0, =GPSR0
6d0f6bcf	56	ldr r1, =CONFIG_SYS_GPSR0_VAL
70a2047f WD	57	str r1, [r0]
	58
	59	ldr r0, =GPSR1
6d0f6bcf	60	ldr r1, =CONFIG_SYS_GPSR1_VAL
70a2047f WD	61	str r1, [r0]
	62
	63	ldr r0, =GPSR2
6d0f6bcf	64	ldr r1, =CONFIG_SYS_GPSR2_VAL
70a2047f WD	65	str r1, [r0]
	66
	67	ldr r0, =GPCR0
6d0f6bcf	68	ldr r1, =CONFIG_SYS_GPCR0_VAL
70a2047f WD	69	str r1, [r0]
	70
	71	ldr r0, =GPCR1
6d0f6bcf	72	ldr r1, =CONFIG_SYS_GPCR1_VAL
70a2047f WD	73	str r1, [r0]
	74
	75	ldr r0, =GPCR2
6d0f6bcf	76	ldr r1, =CONFIG_SYS_GPCR2_VAL
70a2047f WD	77	str r1, [r0]
	78
	79	ldr r0, =GPDR0
6d0f6bcf	80	ldr r1, =CONFIG_SYS_GPDR0_VAL
70a2047f WD	81	str r1, [r0]
	82
	83	ldr r0, =GPDR1
6d0f6bcf	84	ldr r1, =CONFIG_SYS_GPDR1_VAL
70a2047f WD	85	str r1, [r0]
	86
	87	ldr r0, =GPDR2
6d0f6bcf	88	ldr r1, =CONFIG_SYS_GPDR2_VAL
70a2047f WD	89	str r1, [r0]
	90
	91	ldr r0, =GAFR0_L
6d0f6bcf	92	ldr r1, =CONFIG_SYS_GAFR0_L_VAL
70a2047f WD	93	str r1, [r0]
	94
	95	ldr r0, =GAFR0_U
6d0f6bcf	96	ldr r1, =CONFIG_SYS_GAFR0_U_VAL
70a2047f WD	97	str r1, [r0]
	98
	99	ldr r0, =GAFR1_L
6d0f6bcf	100	ldr r1, =CONFIG_SYS_GAFR1_L_VAL
70a2047f WD	101	str r1, [r0]
	102
	103	ldr r0, =GAFR1_U
6d0f6bcf	104	ldr r1, =CONFIG_SYS_GAFR1_U_VAL
70a2047f WD	105	str r1, [r0]
	106
	107	ldr r0, =GAFR2_L
6d0f6bcf	108	ldr r1, =CONFIG_SYS_GAFR2_L_VAL
70a2047f WD	109	str r1, [r0]
	110
	111	ldr r0, =GAFR2_U
6d0f6bcf	112	ldr r1, =CONFIG_SYS_GAFR2_U_VAL
70a2047f WD	113	str r1, [r0]
	114
	115	ldr r0, =PSSR /* enable GPIO pins */
6d0f6bcf	116	ldr r1, =CONFIG_SYS_PSSR_VAL
70a2047f WD	117	str r1, [r0]
	118
	119	#ifdef DEBUG_BLINK_ENABLE
	120	/* 4th debug blink */
53677ef1	121	bl blink
70a2047f WD	122	#endif
	123
	124	/* ---------------------------------------------------------------- */
	125	/* Enable memory interface */
	126	/* */
	127	/* The sequence below is based on the recommended init steps */
	128	/* detailed in the Intel PXA250 Operating Systems Developers Guide, */
	129	/* Chapter 10. */
	130	/* ---------------------------------------------------------------- */
	131
	132	/* ---------------------------------------------------------------- */
	133	/* Step 1: Wait for at least 200 microsedonds to allow internal */
	134	/* clocks to settle. Only necessary after hard reset... */
	135	/* FIXME: can be optimized later */
	136	/* ---------------------------------------------------------------- */
	137
	138	ldr r3, =OSCR /* reset the OS Timer Count to zero */
	139	mov r2, #0
	140	str r2, [r3]
	141	ldr r4, =0x300 /* really 0x2E1 is about 200usec, */
	142	/* so 0x300 should be plenty */
	143	1:
	144	ldr r2, [r3]
	145	cmp r4, r2
	146	bgt 1b
	147
	148	mem_init:
	149
	150	ldr r1, =MEMC_BASE /* get memory controller base addr. */
	151
	152	/* ---------------------------------------------------------------- */
	153	/* Step 2a: Initialize Asynchronous static memory controller */
	154	/* ---------------------------------------------------------------- */
	155
	156	/* MSC registers: timing, bus width, mem type */
	157
	158	/* MSC0: nCS(0,1) */
6d0f6bcf	159	ldr r2, =CONFIG_SYS_MSC0_VAL
70a2047f WD	160	str r2, [r1, #MSC0_OFFSET]
	161	ldr r2, [r1, #MSC0_OFFSET] /* read back to ensure */
	162	/* that data latches */
	163	/* MSC1: nCS(2,3) */
6d0f6bcf	164	ldr r2, =CONFIG_SYS_MSC1_VAL
70a2047f WD	165	str r2, [r1, #MSC1_OFFSET]
	166	ldr r2, [r1, #MSC1_OFFSET]
	167
	168	/* MSC2: nCS(4,5) */
6d0f6bcf	169	ldr r2, =CONFIG_SYS_MSC2_VAL
70a2047f WD	170	str r2, [r1, #MSC2_OFFSET]
	171	ldr r2, [r1, #MSC2_OFFSET]
	172
	173	/* ---------------------------------------------------------------- */
	174	/* Step 2b: Initialize Card Interface */
	175	/* ---------------------------------------------------------------- */
	176
	177	/* MECR: Memory Expansion Card Register */
6d0f6bcf	178	ldr r2, =CONFIG_SYS_MECR_VAL
70a2047f WD	179	str r2, [r1, #MECR_OFFSET]
	180	ldr r2, [r1, #MECR_OFFSET]
	181
	182	/* MCMEM0: Card Interface slot 0 timing */
6d0f6bcf	183	ldr r2, =CONFIG_SYS_MCMEM0_VAL
70a2047f WD	184	str r2, [r1, #MCMEM0_OFFSET]
	185	ldr r2, [r1, #MCMEM0_OFFSET]
	186
	187	/* MCMEM1: Card Interface slot 1 timing */
6d0f6bcf	188	ldr r2, =CONFIG_SYS_MCMEM1_VAL
70a2047f WD	189	str r2, [r1, #MCMEM1_OFFSET]
	190	ldr r2, [r1, #MCMEM1_OFFSET]
	191
	192	/* MCATT0: Card Interface Attribute Space Timing, slot 0 */
6d0f6bcf	193	ldr r2, =CONFIG_SYS_MCATT0_VAL
70a2047f WD	194	str r2, [r1, #MCATT0_OFFSET]
	195	ldr r2, [r1, #MCATT0_OFFSET]
	196
	197	/* MCATT1: Card Interface Attribute Space Timing, slot 1 */
6d0f6bcf	198	ldr r2, =CONFIG_SYS_MCATT1_VAL
70a2047f WD	199	str r2, [r1, #MCATT1_OFFSET]
	200	ldr r2, [r1, #MCATT1_OFFSET]
	201
	202	/* MCIO0: Card Interface I/O Space Timing, slot 0 */
6d0f6bcf	203	ldr r2, =CONFIG_SYS_MCIO0_VAL
70a2047f WD	204	str r2, [r1, #MCIO0_OFFSET]
	205	ldr r2, [r1, #MCIO0_OFFSET]
	206
	207	/* MCIO1: Card Interface I/O Space Timing, slot 1 */
6d0f6bcf	208	ldr r2, =CONFIG_SYS_MCIO1_VAL
70a2047f WD	209	str r2, [r1, #MCIO1_OFFSET]
	210	ldr r2, [r1, #MCIO1_OFFSET]
	211
	212	#ifdef DEBUG_BLINK_ENABLE
	213	/* 5th blink */
53677ef1	214	bl blink
70a2047f WD	215	#endif
	216
	217	/* ---------------------------------------------------------------- */
	218	/* Step 2c: Write FLYCNFG FIXME: what's that??? */
	219	/* ---------------------------------------------------------------- */
	220
	221	/* ---------------------------------------------------------------- */
	222	/* Step 2d: Initialize Timing for Sync Memory (SDCLK0) */
	223	/* ---------------------------------------------------------------- */
	224
	225	/* Before accessing MDREFR we need a valid DRI field, so we set */
	226	/* this to power on defaults + DRI field. */
	227
6d0f6bcf	228	ldr r3, =CONFIG_SYS_MDREFR_VAL
70a2047f WD	229	ldr r2, =0xFFF
	230	and r3, r3, r2
	231	ldr r4, =0x03ca4000
	232	orr r4, r4, r3
	233	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
	234	ldr r4, [r1, #MDREFR_OFFSET]
	235
	236	/* Note: preserve the mdrefr value in r4 */
	237
	238	/* ---------------------------------------------------------------- */
	239	/* Step 3: Initialize Synchronous Static Memory (Flash/Peripherals) */
	240	/* ---------------------------------------------------------------- */
	241
	242	/* Initialize SXCNFG register. Assert the enable bits */
	243
	244	/* Write SXMRS to cause an MRS command to all enabled banks of */
	245	/* synchronous static memory. Note that SXLCR need not be written */
	246	/* at this time. */
	247
	248	/* FIXME: we use async mode for now */
	249
	250	/* ---------------------------------------------------------------- */
	251	/* Step 4: Initialize SDRAM */
	252	/* ---------------------------------------------------------------- */
	253
	254	/* set MDREFR according to user define with exception of a few bits */
	255
6d0f6bcf	256	ldr r4, =CONFIG_SYS_MDREFR_VAL
70a2047f WD	257	orr r4, r4, #(MDREFR_SLFRSH)
	258	bic r4, r4, #(MDREFR_E1PIN\|MDREFR_E0PIN)
	259	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
	260	ldr r4, [r1, #MDREFR_OFFSET]
	261
	262	/* Step 4b: de-assert MDREFR:SLFRSH. */
	263
	264	bic r4, r4, #(MDREFR_SLFRSH)
	265	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
	266	ldr r4, [r1, #MDREFR_OFFSET]
	267
	268	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired */
	269
6d0f6bcf	270	ldr r4, =CONFIG_SYS_MDREFR_VAL
70a2047f WD	271	str r4, [r1, #MDREFR_OFFSET] /* write back MDREFR */
	272	ldr r4, [r1, #MDREFR_OFFSET]
	273
	274
	275	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to */
	276	/* configure but not enable each SDRAM partition pair. */
	277
6d0f6bcf	278	ldr r4, =CONFIG_SYS_MDCNFG_VAL
70a2047f WD	279	bic r4, r4, #(MDCNFG_DE0\|MDCNFG_DE1)
	280
	281	str r4, [r1, #MDCNFG_OFFSET] /* write back MDCNFG */
	282	ldr r4, [r1, #MDCNFG_OFFSET]
	283
	284	/* Step 4e: Wait for the clock to the SDRAMs to stabilize, */
	285