[thirdparty/u-boot.git] / board / renesas / alt / alt.c

// SPDX-License-Identifier: GPL-2.0
/*
 * board/renesas/alt/alt.c
 *
 * Copyright (C) 2014, 2015 Renesas Electronics Corporation
 */

#include <cpu_func.h>
#include <env.h>
#include <hang.h>
#include <init.h>
#include <malloc.h>
#include <dm.h>
#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <env_internal.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/rmobile.h>
#include <asm/arch/rcar-mstp.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#include <div64.h>
#include "qos.h"

DECLARE_GLOBAL_DATA_PTR;

void s_init(void)
{
	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;

	/* Watchdog init */
	writel(0xA5A5A500, &rwdt->rwtcsra);
	writel(0xA5A5A500, &swdt->swtcsra);

	/* QoS */
	qos_init();
}

#define TMU0_MSTP125	BIT(25)
#define MMC0_MSTP315	BIT(15)

#define SD1CKCR		0xE6150078
#define SD_97500KHZ	0x7

int board_early_init_f(void)
{
	/* TMU */
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);

	/* Set SD1 to the 97.5MHz */
	writel(SD_97500KHZ, SD1CKCR);

	return 0;
}

#define ETHERNET_PHY_RESET	56	/* GPIO 1 24 */

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;

	/* Force ethernet PHY out of reset */
	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
	gpio_direction_output(ETHERNET_PHY_RESET, 0);
	mdelay(20);
	gpio_direction_output(ETHERNET_PHY_RESET, 1);
	udelay(1);

	return 0;
}

int dram_init(void)
{
	if (fdtdec_setup_mem_size_base() != 0)
		return -EINVAL;

	return 0;
}

int dram_init_banksize(void)
{
	fdtdec_setup_memory_banksize();

	return 0;
}

/* KSZ8041RNLI */
#define PHY_CONTROL1		0x1E
#define PHY_LED_MODE		0xC000
#define PHY_LED_MODE_ACK	0x4000
int board_phy_config(struct phy_device *phydev)
{
	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
	ret &= ~PHY_LED_MODE;
	ret |= PHY_LED_MODE_ACK;
	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);

	return 0;
}

void reset_cpu(void)
{
	struct udevice *dev;
	const u8 pmic_bus = 7;
	const u8 pmic_addr = 0x58;
	u8 data;
	int ret;

	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
	if (ret)
		hang();

	ret = dm_i2c_read(dev, 0x13, &data, 1);
	if (ret)
		hang();

	data |= BIT(1);

	ret = dm_i2c_write(dev, 0x13, &data, 1);
	if (ret)
		hang();
}

enum env_location env_get_location(enum env_operation op, int prio)
{
	const u32 load_magic = 0xb33fc0de;

	/* Block environment access if loaded using JTAG */
	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
	    (op != ENVOP_INIT))
		return ENVL_UNKNOWN;

	if (prio)
		return ENVL_UNKNOWN;

	return ENVL_SPI_FLASH;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
cff2f5f0 NI	2	/*
	3	* board/renesas/alt/alt.c
	4	*
cae72042	5	* Copyright (C) 2014, 2015 Renesas Electronics Corporation
cff2f5f0 NI	6	*/
cff2f5f0 NI	7
9a3b4ceb	8	#include <cpu_func.h>
7b51b576	9	#include <env.h>
db41d65a	10	#include <hang.h>
691d719d	11	#include <init.h>
cff2f5f0	12	#include <malloc.h>
9e116f64	13	#include <dm.h>
401d1c4f	14	#include <asm/global_data.h>
9e116f64	15	#include <dm/platform_data/serial_sh.h>
f3998fdc	16	#include <env_internal.h>
cff2f5f0 NI	17	#include <asm/processor.h>
	18	#include <asm/mach-types.h>
	19	#include <asm/io.h>
cd93d625	20	#include <linux/bitops.h>
c05ed00a	21	#include <linux/delay.h>
1221ce45	22	#include <linux/errno.h>
cff2f5f0 NI	23	#include <asm/arch/sys_proto.h>
	24	#include <asm/gpio.h>
	25	#include <asm/arch/rmobile.h>
44e1eebf	26	#include <asm/arch/rcar-mstp.h>
cff2f5f0 NI	27	#include <netdev.h>
	28	#include <miiphy.h>
	29	#include <i2c.h>
	30	#include <div64.h>
	31	#include "qos.h"
	32
	33	DECLARE_GLOBAL_DATA_PTR;
	34
cff2f5f0 NI	35	void s_init(void)
	36	{
	37	struct rcar_rwdt rwdt = (struct rcar_rwdt )RWDT_BASE;
	38	struct rcar_swdt swdt = (struct rcar_swdt )SWDT_BASE;
	39
	40	/* Watchdog init */
	41	writel(0xA5A5A500, &rwdt->rwtcsra);
	42	writel(0xA5A5A500, &swdt->swtcsra);
	43
	44	/* QoS */
	45	qos_init();
	46	}
	47
bb6d2ff2 MV	48	#define TMU0_MSTP125 BIT(25)
bb6d2ff2 MV	49	#define MMC0_MSTP315 BIT(15)
25f9613f NI	50
25f9613f NI	51	#define SD1CKCR 0xE6150078
bb6d2ff2	52	#define SD_97500KHZ 0x7
92ef38ee	53
cff2f5f0 NI	54	int board_early_init_f(void)
	55	{
	56	/* TMU */
	57	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
	58
bb6d2ff2 MV	59	/* Set SD1 to the 97.5MHz */
bb6d2ff2 MV	60	writel(SD_97500KHZ, SD1CKCR);
cff2f5f0	61
cff2f5f0 NI	62	return 0;
	63	}
	64
bb6d2ff2 MV	65	#define ETHERNET_PHY_RESET 56 /* GPIO 1 24 */
bb6d2ff2 MV	66
cff2f5f0 NI	67	int board_init(void)
	68	{
	69	/* adress of boot parameters */
aa6e94de	70	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
cff2f5f0	71
bb6d2ff2 MV	72	/* Force ethernet PHY out of reset */
	73	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
	74	gpio_direction_output(ETHERNET_PHY_RESET, 0);
cff2f5f0	75	mdelay(20);
bb6d2ff2	76	gpio_direction_output(ETHERNET_PHY_RESET, 1);
cff2f5f0 NI	77	udelay(1);
	78
	79	return 0;
	80	}
	81
bb6d2ff2	82	int dram_init(void)
cff2f5f0	83	{
12308b12	84	if (fdtdec_setup_mem_size_base() != 0)
bb6d2ff2	85	return -EINVAL;
cff2f5f0	86
cff2f5f0	87	return 0;
cff2f5f0 NI	88	}
cff2f5f0 NI	89
bb6d2ff2	90	int dram_init_banksize(void)
2b8c0814	91	{
bb6d2ff2	92	fdtdec_setup_memory_banksize();
25f9613f	93
bb6d2ff2	94	return 0;
2b8c0814 NI	95	}
2b8c0814 NI	96
bb6d2ff2 MV	97	/* KSZ8041RNLI */
bb6d2ff2 MV	98	#define PHY_CONTROL1 0x1E
4bbd4642	99	#define PHY_LED_MODE 0xC000
bb6d2ff2 MV	100	#define PHY_LED_MODE_ACK 0x4000
bb6d2ff2 MV	101	int board_phy_config(struct phy_device *phydev)
cff2f5f0	102	{
bb6d2ff2 MV	103	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
	104	ret &= ~PHY_LED_MODE;
	105	ret \|= PHY_LED_MODE_ACK;
	106	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
cff2f5f0 NI	107
	108	return 0;
	109	}
	110
35b65dd8	111	void reset_cpu(void)
cff2f5f0	112	{
bb6d2ff2	113	struct udevice *dev;
0c78ec64	114	const u8 pmic_bus = 7;
bb6d2ff2 MV	115	const u8 pmic_addr = 0x58;
	116	u8 data;
	117	int ret;
cff2f5f0	118
bb6d2ff2 MV	119	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
	120	if (ret)
	121	hang();
	122
	123	ret = dm_i2c_read(dev, 0x13, &data, 1);
	124	if (ret)
	125	hang();
	126
	127	data \|= BIT(1);
	128
	129	ret = dm_i2c_write(dev, 0x13, &data, 1);
	130	if (ret)
	131	hang();
cff2f5f0	132	}
9e116f64	133
bb6d2ff2 MV	134	enum env_location env_get_location(enum env_operation op, int prio)
	135	{
	136	const u32 load_magic = 0xb33fc0de;
9e116f64	137
bb6d2ff2 MV	138	/* Block environment access if loaded using JTAG */
	139	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
	140	(op != ENVOP_INIT))
	141	return ENVL_UNKNOWN;
	142
	143	if (prio)
	144	return ENVL_UNKNOWN;
	145
	146	return ENVL_SPI_FLASH;
	147	}