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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
6a994e5b NI |
2 | /* |
3 | * board/renesas/gose/gose.c | |
4 | * | |
5 | * Copyright (C) 2014 Renesas Electronics Corporation | |
6a994e5b NI |
6 | */ |
7 | ||
2f8a6db5 | 8 | #include <clock_legacy.h> |
9a3b4ceb | 9 | #include <cpu_func.h> |
7b51b576 | 10 | #include <env.h> |
db41d65a | 11 | #include <hang.h> |
691d719d | 12 | #include <init.h> |
6a994e5b | 13 | #include <malloc.h> |
9d86e48e | 14 | #include <dm.h> |
401d1c4f | 15 | #include <asm/global_data.h> |
9d86e48e | 16 | #include <dm/platform_data/serial_sh.h> |
f3998fdc | 17 | #include <env_internal.h> |
6a994e5b NI |
18 | #include <asm/processor.h> |
19 | #include <asm/mach-types.h> | |
20 | #include <asm/io.h> | |
cd93d625 | 21 | #include <linux/bitops.h> |
c05ed00a | 22 | #include <linux/delay.h> |
1221ce45 | 23 | #include <linux/errno.h> |
6a994e5b NI |
24 | #include <asm/arch/sys_proto.h> |
25 | #include <asm/gpio.h> | |
65abdd19 | 26 | #include <asm/arch/renesas.h> |
44e1eebf | 27 | #include <asm/arch/rcar-mstp.h> |
f0261243 NI |
28 | #include <netdev.h> |
29 | #include <miiphy.h> | |
6a994e5b NI |
30 | #include <i2c.h> |
31 | #include "qos.h" | |
32 | ||
33 | DECLARE_GLOBAL_DATA_PTR; | |
34 | ||
35 | #define CLK2MHZ(clk) (clk / 1000 / 1000) | |
36 | void s_init(void) | |
37 | { | |
38 | struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; | |
39 | struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; | |
40 | u32 stc; | |
41 | ||
42 | /* Watchdog init */ | |
43 | writel(0xA5A5A500, &rwdt->rwtcsra); | |
44 | writel(0xA5A5A500, &swdt->swtcsra); | |
45 | ||
46 | /* CPU frequency setting. Set to 1.5GHz */ | |
2f8a6db5 | 47 | stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT; |
6a994e5b NI |
48 | clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); |
49 | ||
50 | /* QoS */ | |
51 | qos_init(); | |
52 | } | |
53 | ||
49aefe30 | 54 | #define TMU0_MSTP125 BIT(25) |
e2abab69 NI |
55 | |
56 | #define SD1CKCR 0xE6150078 | |
57 | #define SD2CKCR 0xE615026C | |
58 | #define SD_97500KHZ 0x7 | |
59 | ||
6a994e5b NI |
60 | int board_early_init_f(void) |
61 | { | |
6a994e5b NI |
62 | mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); |
63 | ||
49aefe30 MV |
64 | /* |
65 | * SD0 clock is set to 97.5MHz by default. | |
66 | * Set SD1 and SD2 to the 97.5MHz as well. | |
67 | */ | |
e2abab69 NI |
68 | writel(SD_97500KHZ, SD1CKCR); |
69 | writel(SD_97500KHZ, SD2CKCR); | |
70 | ||
6a994e5b NI |
71 | return 0; |
72 | } | |
73 | ||
49aefe30 | 74 | #define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */ |
f0261243 | 75 | |
6a994e5b NI |
76 | int board_init(void) |
77 | { | |
78 | /* adress of boot parameters */ | |
aa6e94de | 79 | gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; |
6a994e5b | 80 | |
49aefe30 MV |
81 | /* Force ethernet PHY out of reset */ |
82 | gpio_request(ETHERNET_PHY_RESET, "phy_reset"); | |
83 | gpio_direction_output(ETHERNET_PHY_RESET, 0); | |
84 | mdelay(10); | |
85 | gpio_direction_output(ETHERNET_PHY_RESET, 1); | |
f0261243 | 86 | |
6a994e5b NI |
87 | return 0; |
88 | } | |
89 | ||
49aefe30 | 90 | int dram_init(void) |
f0261243 | 91 | { |
12308b12 | 92 | if (fdtdec_setup_mem_size_base() != 0) |
49aefe30 | 93 | return -EINVAL; |
f0261243 | 94 | |
49aefe30 | 95 | return 0; |
f0261243 NI |
96 | } |
97 | ||
49aefe30 | 98 | int dram_init_banksize(void) |
e2abab69 | 99 | { |
49aefe30 | 100 | fdtdec_setup_memory_banksize(); |
e2abab69 | 101 | |
49aefe30 | 102 | return 0; |
e2abab69 NI |
103 | } |
104 | ||
49aefe30 MV |
105 | /* KSZ8041RNLI */ |
106 | #define PHY_CONTROL1 0x1E | |
4bbd4642 | 107 | #define PHY_LED_MODE 0xC000 |
49aefe30 MV |
108 | #define PHY_LED_MODE_ACK 0x4000 |
109 | int board_phy_config(struct phy_device *phydev) | |
6a994e5b | 110 | { |
49aefe30 MV |
111 | int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); |
112 | ret &= ~PHY_LED_MODE; | |
113 | ret |= PHY_LED_MODE_ACK; | |
114 | ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); | |
6a994e5b NI |
115 | |
116 | return 0; | |
117 | } | |
118 | ||
35b65dd8 | 119 | void reset_cpu(void) |
6a994e5b | 120 | { |
49aefe30 MV |
121 | struct udevice *dev; |
122 | const u8 pmic_bus = 6; | |
123 | const u8 pmic_addr = 0x58; | |
124 | u8 data; | |
125 | int ret; | |
126 | ||
127 | ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); | |
128 | if (ret) | |
129 | hang(); | |
130 | ||
131 | ret = dm_i2c_read(dev, 0x13, &data, 1); | |
132 | if (ret) | |
133 | hang(); | |
134 | ||
135 | data |= BIT(1); | |
6a994e5b | 136 | |
49aefe30 MV |
137 | ret = dm_i2c_write(dev, 0x13, &data, 1); |
138 | if (ret) | |
139 | hang(); | |
6a994e5b | 140 | } |
9d86e48e | 141 | |
49aefe30 MV |
142 | enum env_location env_get_location(enum env_operation op, int prio) |
143 | { | |
144 | const u32 load_magic = 0xb33fc0de; | |
9d86e48e | 145 | |
49aefe30 MV |
146 | /* Block environment access if loaded using JTAG */ |
147 | if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && | |
148 | (op != ENVOP_INIT)) | |
149 | return ENVL_UNKNOWN; | |
150 | ||
151 | if (prio) | |
152 | return ENVL_UNKNOWN; | |
153 | ||
154 | return ENVL_SPI_FLASH; | |
155 | } |