[thirdparty/u-boot.git] / board / renesas / koelsch / koelsch.c

// SPDX-License-Identifier: GPL-2.0
/*
 * board/renesas/koelsch/koelsch.c
 *
 * Copyright (C) 2013 Renesas Electronics Corporation
 *
 */

#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <hang.h>
#include <init.h>
#include <malloc.h>
#include <dm.h>
#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <env_internal.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#include <div64.h>
#include "qos.h"

DECLARE_GLOBAL_DATA_PTR;

#define CLK2MHZ(clk)	(clk / 1000 / 1000)
void s_init(void)
{
	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
	u32 stc;

	/* Watchdog init */
	writel(0xA5A5A500, &rwdt->rwtcsra);
	writel(0xA5A5A500, &swdt->swtcsra);

	/* CPU frequency setting. Set to 1.5GHz */
	stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);

	/* QoS */
	qos_init();
}

#define TMU0_MSTP125	BIT(25)

#define SD1CKCR		0xE6150078
#define SD2CKCR		0xE615026C
#define SD_97500KHZ	0x7

int board_early_init_f(void)
{
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);

	/*
	 * SD0 clock is set to 97.5MHz by default.
	 * Set SD1 and SD2 to the 97.5MHz as well.
	 */
	writel(SD_97500KHZ, SD1CKCR);
	writel(SD_97500KHZ, SD2CKCR);

	return 0;
}

#define ETHERNET_PHY_RESET	176	/* GPIO 5 22 */

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;

	/* Force ethernet PHY out of reset */
	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
	gpio_direction_output(ETHERNET_PHY_RESET, 0);
	mdelay(10);
	gpio_direction_output(ETHERNET_PHY_RESET, 1);

	return 0;
}

int dram_init(void)
{
	if (fdtdec_setup_mem_size_base() != 0)
		return -EINVAL;

	return 0;
}

int dram_init_banksize(void)
{
	fdtdec_setup_memory_banksize();

	return 0;
}

/* Koelsch has KSZ8041NL/RNL */
#define PHY_CONTROL1		0x1E
#define PHY_LED_MODE		0xC000
#define PHY_LED_MODE_ACK	0x4000
int board_phy_config(struct phy_device *phydev)
{
	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
	ret &= ~PHY_LED_MODE;
	ret |= PHY_LED_MODE_ACK;
	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);

	return 0;
}

void reset_cpu(void)
{
	struct udevice *dev;
	const u8 pmic_bus = 6;
	const u8 pmic_addr = 0x58;
	u8 data;
	int ret;

	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
	if (ret)
		hang();

	ret = dm_i2c_read(dev, 0x13, &data, 1);
	if (ret)
		hang();

	data |= BIT(1);

	ret = dm_i2c_write(dev, 0x13, &data, 1);
	if (ret)
		hang();
}

enum env_location env_get_location(enum env_operation op, int prio)
{
	const u32 load_magic = 0xb33fc0de;

	/* Block environment access if loaded using JTAG */
	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
	    (op != ENVOP_INIT))
		return ENVL_UNKNOWN;

	if (prio)
		return ENVL_UNKNOWN;

	return ENVL_SPI_FLASH;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
1251e490 NI	2	/*
	3	* board/renesas/koelsch/koelsch.c
	4	*
	5	* Copyright (C) 2013 Renesas Electronics Corporation
	6	*
1251e490 NI	7	*/
1251e490 NI	8
2f8a6db5	9	#include <clock_legacy.h>
9a3b4ceb	10	#include <cpu_func.h>
7b51b576	11	#include <env.h>
db41d65a	12	#include <hang.h>
691d719d	13	#include <init.h>
1251e490	14	#include <malloc.h>
0bf51cb0	15	#include <dm.h>
401d1c4f	16	#include <asm/global_data.h>
0bf51cb0	17	#include <dm/platform_data/serial_sh.h>
f3998fdc	18	#include <env_internal.h>
1251e490 NI	19	#include <asm/processor.h>
	20	#include <asm/mach-types.h>
	21	#include <asm/io.h>
cd93d625	22	#include <linux/bitops.h>
c05ed00a	23	#include <linux/delay.h>
1221ce45	24	#include <linux/errno.h>
1251e490 NI	25	#include <asm/arch/sys_proto.h>
1251e490 NI	26	#include <asm/gpio.h>
65abdd19	27	#include <asm/arch/renesas.h>
44e1eebf	28	#include <asm/arch/rcar-mstp.h>
90362c0c NI	29	#include <netdev.h>
90362c0c NI	30	#include <miiphy.h>
1251e490	31	#include <i2c.h>
ccde6771	32	#include <div64.h>
1251e490 NI	33	#include "qos.h"
	34
	35	DECLARE_GLOBAL_DATA_PTR;
	36
ccde6771	37	#define CLK2MHZ(clk) (clk / 1000 / 1000)
1251e490 NI	38	void s_init(void)
1251e490 NI	39	{
ec9b386e NI	40	struct rcar_rwdt rwdt = (struct rcar_rwdt )RWDT_BASE;
ec9b386e NI	41	struct rcar_swdt swdt = (struct rcar_swdt )SWDT_BASE;
ccde6771	42	u32 stc;
1251e490 NI	43
	44	/* Watchdog init */
	45	writel(0xA5A5A500, &rwdt->rwtcsra);
	46	writel(0xA5A5A500, &swdt->swtcsra);
	47
ccde6771	48	/* CPU frequency setting. Set to 1.5GHz */
2f8a6db5	49	stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
ccde6771 NI	50	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
ccde6771 NI	51
1251e490 NI	52	/* QoS */
1251e490 NI	53	qos_init();
1251e490 NI	54	}
1251e490 NI	55
7d0299cd	56	#define TMU0_MSTP125 BIT(25)
11e32910 NI	57
	58	#define SD1CKCR 0xE6150078
	59	#define SD2CKCR 0xE615026C
	60	#define SD_97500KHZ 0x7
	61
1251e490 NI	62	int board_early_init_f(void)
	63	{
	64	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
	65
11e32910 NI	66	/*
	67	* SD0 clock is set to 97.5MHz by default.
	68	* Set SD1 and SD2 to the 97.5MHz as well.
	69	*/
	70	writel(SD_97500KHZ, SD1CKCR);
	71	writel(SD_97500KHZ, SD2CKCR);
	72
1251e490 NI	73	return 0;
	74	}
	75
7d0299cd MV	76	#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
7d0299cd MV	77
1251e490 NI	78	int board_init(void)
	79	{
	80	/* adress of boot parameters */
aa6e94de	81	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
1251e490	82
7d0299cd MV	83	/* Force ethernet PHY out of reset */
	84	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
	85	gpio_direction_output(ETHERNET_PHY_RESET, 0);
	86	mdelay(10);
	87	gpio_direction_output(ETHERNET_PHY_RESET, 1);
90362c0c NI	88
	89	return 0;
	90	}
	91
7d0299cd	92	int dram_init(void)
90362c0c	93	{
12308b12	94	if (fdtdec_setup_mem_size_base() != 0)
7d0299cd	95	return -EINVAL;
90362c0c	96
1251e490 NI	97	return 0;
	98	}
	99
7d0299cd	100	int dram_init_banksize(void)
11e32910	101	{
7d0299cd	102	fdtdec_setup_memory_banksize();
1251e490 NI	103
	104	return 0;
	105	}
	106
7d0299cd MV	107	/* Koelsch has KSZ8041NL/RNL */
7d0299cd MV	108	#define PHY_CONTROL1 0x1E
4bbd4642	109	#define PHY_LED_MODE 0xC000
90362c0c NI	110	#define PHY_LED_MODE_ACK 0x4000
	111	int board_phy_config(struct phy_device *phydev)
	112	{
	113	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
	114	ret &= ~PHY_LED_MODE;
	115	ret \|= PHY_LED_MODE_ACK;
	116	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
	117
	118	return 0;
	119	}
	120
35b65dd8	121	void reset_cpu(void)
1251e490	122	{
7d0299cd MV	123	struct udevice *dev;
	124	const u8 pmic_bus = 6;
	125	const u8 pmic_addr = 0x58;
	126	u8 data;
	127	int ret;
	128
	129	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
	130	if (ret)
	131	hang();
	132
	133	ret = dm_i2c_read(dev, 0x13, &data, 1);
	134	if (ret)
	135	hang();
	136
	137	data \|= BIT(1);
b8f383b8	138
7d0299cd MV	139	ret = dm_i2c_write(dev, 0x13, &data, 1);
	140	if (ret)
	141	hang();
1251e490	142	}
0bf51cb0	143
7d0299cd MV	144	enum env_location env_get_location(enum env_operation op, int prio)
	145	{
	146	const u32 load_magic = 0xb33fc0de;
0bf51cb0	147
7d0299cd MV	148	/* Block environment access if loaded using JTAG */
	149	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
	150	(op != ENVOP_INIT))
	151	return ENVL_UNKNOWN;
	152
	153	if (prio)
	154	return ENVL_UNKNOWN;
	155
	156	return ENVL_SPI_FLASH;
	157	}