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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0 |
f4ec4522 NI |
2 | /* |
3 | * board/renesas/lager/lager.c | |
4 | * This file is lager board support. | |
5 | * | |
6 | * Copyright (C) 2013 Renesas Electronics Corporation | |
7 | * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> | |
f4ec4522 NI |
8 | */ |
9 | ||
2f8a6db5 | 10 | #include <clock_legacy.h> |
9a3b4ceb | 11 | #include <cpu_func.h> |
7b51b576 | 12 | #include <env.h> |
f3998fdc | 13 | #include <env_internal.h> |
db41d65a | 14 | #include <hang.h> |
691d719d | 15 | #include <init.h> |
f4ec4522 NI |
16 | #include <malloc.h> |
17 | #include <netdev.h> | |
cf839572 | 18 | #include <dm.h> |
401d1c4f | 19 | #include <asm/global_data.h> |
cf839572 | 20 | #include <dm/platform_data/serial_sh.h> |
f4ec4522 NI |
21 | #include <asm/processor.h> |
22 | #include <asm/mach-types.h> | |
23 | #include <asm/io.h> | |
cd93d625 | 24 | #include <linux/bitops.h> |
c05ed00a | 25 | #include <linux/delay.h> |
1221ce45 | 26 | #include <linux/errno.h> |
f4ec4522 NI |
27 | #include <asm/arch/sys_proto.h> |
28 | #include <asm/gpio.h> | |
29 | #include <asm/arch/rmobile.h> | |
44e1eebf | 30 | #include <asm/arch/rcar-mstp.h> |
d7916b1d | 31 | #include <asm/arch/mmc.h> |
23565c6b | 32 | #include <miiphy.h> |
b9986be0 | 33 | #include <i2c.h> |
d7916b1d | 34 | #include <mmc.h> |
f4ec4522 NI |
35 | #include "qos.h" |
36 | ||
37 | DECLARE_GLOBAL_DATA_PTR; | |
38 | ||
2c2c6ba6 | 39 | #define CLK2MHZ(clk) (clk / 1000 / 1000) |
f4ec4522 NI |
40 | void s_init(void) |
41 | { | |
dc535e10 NI |
42 | struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; |
43 | struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; | |
f4ec4522 NI |
44 | |
45 | /* Watchdog init */ | |
46 | writel(0xA5A5A500, &rwdt->rwtcsra); | |
47 | writel(0xA5A5A500, &swdt->swtcsra); | |
48 | ||
2c2c6ba6 | 49 | /* CPU frequency setting. Set to 1.4GHz */ |
f212a8ab | 50 | if (rmobile_get_cpu_rev_integer() >= R8A7790_CUT_ES2X) { |
d8659c6d | 51 | u32 stat = 0; |
2f8a6db5 | 52 | u32 stc = ((1400 / CLK2MHZ(get_board_sys_clk())) - 1) |
f212a8ab NI |
53 | << PLL0_STC_BIT; |
54 | clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc); | |
d8659c6d NI |
55 | |
56 | do { | |
57 | stat = readl(PLLECR) & PLL0ST; | |
58 | } while (stat == 0x0); | |
f212a8ab | 59 | } |
2c2c6ba6 | 60 | |
f4ec4522 NI |
61 | /* QoS(Quality-of-Service) Init */ |
62 | qos_init(); | |
f4ec4522 NI |
63 | } |
64 | ||
e6027e6f | 65 | #define TMU0_MSTP125 BIT(25) |
23565c6b | 66 | |
e6027e6f MV |
67 | #define SD1CKCR 0xE6150078 |
68 | #define SD2CKCR 0xE615026C | |
69 | #define SD_97500KHZ 0x7 | |
acdfecbb | 70 | |
f4ec4522 NI |
71 | int board_early_init_f(void) |
72 | { | |
f4ec4522 | 73 | mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); |
acdfecbb NI |
74 | |
75 | /* | |
76 | * SD0 clock is set to 97.5MHz by default. | |
e6027e6f | 77 | * Set SD1 and SD2 to the 97.5MHz as well. |
acdfecbb | 78 | */ |
e6027e6f MV |
79 | writel(SD_97500KHZ, SD1CKCR); |
80 | writel(SD_97500KHZ, SD2CKCR); | |
23565c6b | 81 | |
f4ec4522 NI |
82 | return 0; |
83 | } | |
84 | ||
e6027e6f MV |
85 | #define ETHERNET_PHY_RESET 185 /* GPIO 5 31 */ |
86 | ||
f4ec4522 NI |
87 | int board_init(void) |
88 | { | |
f4ec4522 | 89 | /* adress of boot parameters */ |
aa6e94de | 90 | gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; |
f4ec4522 | 91 | |
e6027e6f MV |
92 | /* Force ethernet PHY out of reset */ |
93 | gpio_request(ETHERNET_PHY_RESET, "phy_reset"); | |
94 | gpio_direction_output(ETHERNET_PHY_RESET, 0); | |
95 | mdelay(10); | |
96 | gpio_direction_output(ETHERNET_PHY_RESET, 1); | |
23565c6b NI |
97 | |
98 | return 0; | |
99 | } | |
100 | ||
e6027e6f | 101 | int dram_init(void) |
23565c6b | 102 | { |
12308b12 | 103 | if (fdtdec_setup_mem_size_base() != 0) |
e6027e6f | 104 | return -EINVAL; |
23565c6b | 105 | |
e6027e6f MV |
106 | return 0; |
107 | } | |
23565c6b | 108 | |
e6027e6f MV |
109 | int dram_init_banksize(void) |
110 | { | |
111 | fdtdec_setup_memory_banksize(); | |
23565c6b | 112 | |
e6027e6f | 113 | return 0; |
23565c6b NI |
114 | } |
115 | ||
e6027e6f MV |
116 | /* KSZ8041NL/RNL */ |
117 | #define PHY_CONTROL1 0x1E | |
4bbd4642 | 118 | #define PHY_LED_MODE 0xC000 |
23565c6b NI |
119 | #define PHY_LED_MODE_ACK 0x4000 |
120 | int board_phy_config(struct phy_device *phydev) | |
121 | { | |
122 | int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1); | |
123 | ret &= ~PHY_LED_MODE; | |
124 | ret |= PHY_LED_MODE_ACK; | |
125 | ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret); | |
126 | ||
f4ec4522 NI |
127 | return 0; |
128 | } | |
129 | ||
35b65dd8 | 130 | void reset_cpu(void) |
d7916b1d | 131 | { |
e6027e6f MV |
132 | struct udevice *dev; |
133 | const u8 pmic_bus = 2; | |
134 | const u8 pmic_addr = 0x58; | |
135 | u8 data; | |
136 | int ret; | |
acdfecbb | 137 | |
e6027e6f MV |
138 | ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev); |
139 | if (ret) | |
140 | hang(); | |
acdfecbb | 141 | |
e6027e6f | 142 | ret = dm_i2c_read(dev, 0x13, &data, 1); |
acdfecbb | 143 | if (ret) |
e6027e6f | 144 | hang(); |
acdfecbb | 145 | |
e6027e6f | 146 | data |= BIT(1); |
acdfecbb | 147 | |
e6027e6f MV |
148 | ret = dm_i2c_write(dev, 0x13, &data, 1); |
149 | if (ret) | |
150 | hang(); | |
d7916b1d NI |
151 | } |
152 | ||
e6027e6f | 153 | enum env_location env_get_location(enum env_operation op, int prio) |
f4ec4522 | 154 | { |
e6027e6f | 155 | const u32 load_magic = 0xb33fc0de; |
f4ec4522 | 156 | |
e6027e6f MV |
157 | /* Block environment access if loaded using JTAG */ |
158 | if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) && | |
159 | (op != ENVOP_INIT)) | |
160 | return ENVL_UNKNOWN; | |
f4ec4522 | 161 | |
e6027e6f MV |
162 | if (prio) |
163 | return ENVL_UNKNOWN; | |
b9986be0 | 164 | |
e6027e6f | 165 | return ENVL_SPI_FLASH; |
f4ec4522 | 166 | } |