[thirdparty/u-boot.git] / board / renesas / porter / porter.c

// SPDX-License-Identifier: GPL-2.0
/*
 * board/renesas/porter/porter.c
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 * Copyright (C) 2015 Cogent Embedded, Inc.
 */

#include <clock_legacy.h>
#include <cpu_func.h>
#include <env.h>
#include <hang.h>
#include <init.h>
#include <malloc.h>
#include <dm.h>
#include <asm/global_data.h>
#include <dm/platform_data/serial_sh.h>
#include <env_internal.h>
#include <asm/processor.h>
#include <asm/mach-types.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/arch/renesas.h>
#include <asm/arch/rcar-mstp.h>
#include <netdev.h>
#include <miiphy.h>
#include <i2c.h>
#include <div64.h>
#include "qos.h"

DECLARE_GLOBAL_DATA_PTR;

#define CLK2MHZ(clk)	(clk / 1000 / 1000)
void s_init(void)
{
	struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE;
	struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE;
	u32 stc;

	/* Watchdog init */
	writel(0xA5A5A500, &rwdt->rwtcsra);
	writel(0xA5A5A500, &swdt->swtcsra);

	/* CPU frequency setting. Set to 1.5GHz */
	stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);

	/* QoS */
	qos_init();
}

#define TMU0_MSTP125	BIT(25)

#define SD2CKCR		0xE615026C
#define SD_97500KHZ	0x7

int board_early_init_f(void)
{
	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);

	/*
	 * SD0 clock is set to 97.5MHz by default.
	 * Set SD2 to the 97.5MHz as well.
	 */
	writel(SD_97500KHZ, SD2CKCR);

	return 0;
}

#define ETHERNET_PHY_RESET	176	/* GPIO 5 22 */

int board_init(void)
{
	/* adress of boot parameters */
	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;

	/* Force ethernet PHY out of reset */
	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
	gpio_direction_output(ETHERNET_PHY_RESET, 0);
	mdelay(10);
	gpio_direction_output(ETHERNET_PHY_RESET, 1);

	return 0;
}

int dram_init(void)
{
	if (fdtdec_setup_mem_size_base() != 0)
		return -EINVAL;

	return 0;
}

int dram_init_banksize(void)
{
	fdtdec_setup_memory_banksize();

	return 0;
}

/* porter has KSZ8041RNLI */
#define PHY_CONTROL1		0x1E
#define PHY_LED_MODE		0xC000
#define PHY_LED_MODE_ACK	0x4000
int board_phy_config(struct phy_device *phydev)
{
	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
	ret &= ~PHY_LED_MODE;
	ret |= PHY_LED_MODE_ACK;
	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);

	return 0;
}

void reset_cpu(void)
{
	struct udevice *dev;
	const u8 pmic_bus = 6;
	const u8 pmic_addr = 0x5a;
	u8 data;
	int ret;

	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
	if (ret)
		hang();

	ret = dm_i2c_read(dev, 0x13, &data, 1);
	if (ret)
		hang();

	data |= BIT(1);

	ret = dm_i2c_write(dev, 0x13, &data, 1);
	if (ret)
		hang();
}

enum env_location env_get_location(enum env_operation op, int prio)
{
	const u32 load_magic = 0xb33fc0de;

	/* Block environment access if loaded using JTAG */
	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
	    (op != ENVOP_INIT))
		return ENVL_UNKNOWN;

	if (prio)
		return ENVL_UNKNOWN;

	return ENVL_SPI_FLASH;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0
60c0467a VB	2	/*
	3	* board/renesas/porter/porter.c
	4	*
	5	* Copyright (C) 2015 Renesas Electronics Corporation
	6	* Copyright (C) 2015 Cogent Embedded, Inc.
60c0467a VB	7	*/
60c0467a VB	8
2f8a6db5	9	#include <clock_legacy.h>
9a3b4ceb	10	#include <cpu_func.h>
7b51b576	11	#include <env.h>
db41d65a	12	#include <hang.h>
691d719d	13	#include <init.h>
60c0467a VB	14	#include <malloc.h>
60c0467a VB	15	#include <dm.h>
401d1c4f	16	#include <asm/global_data.h>
60c0467a	17	#include <dm/platform_data/serial_sh.h>
f3998fdc	18	#include <env_internal.h>
60c0467a VB	19	#include <asm/processor.h>
	20	#include <asm/mach-types.h>
	21	#include <asm/io.h>
cd93d625	22	#include <linux/bitops.h>
c05ed00a	23	#include <linux/delay.h>
1221ce45	24	#include <linux/errno.h>
60c0467a VB	25	#include <asm/arch/sys_proto.h>
60c0467a VB	26	#include <asm/gpio.h>
65abdd19	27	#include <asm/arch/renesas.h>
60c0467a	28	#include <asm/arch/rcar-mstp.h>
60c0467a VB	29	#include <netdev.h>
	30	#include <miiphy.h>
	31	#include <i2c.h>
	32	#include <div64.h>
	33	#include "qos.h"
	34
	35	DECLARE_GLOBAL_DATA_PTR;
	36
	37	#define CLK2MHZ(clk) (clk / 1000 / 1000)
	38	void s_init(void)
	39	{
	40	struct rcar_rwdt rwdt = (struct rcar_rwdt )RWDT_BASE;
	41	struct rcar_swdt swdt = (struct rcar_swdt )SWDT_BASE;
	42	u32 stc;
	43
	44	/* Watchdog init */
	45	writel(0xA5A5A500, &rwdt->rwtcsra);
	46	writel(0xA5A5A500, &swdt->swtcsra);
	47
	48	/* CPU frequency setting. Set to 1.5GHz */
2f8a6db5	49	stc = ((1500 / CLK2MHZ(get_board_sys_clk())) - 1) << PLL0_STC_BIT;
60c0467a VB	50	clrsetbits_le32(PLL0CR, PLL0_STC_MASK, stc);
	51
	52	/* QoS */
	53	qos_init();
	54	}
	55
789edf69	56	#define TMU0_MSTP125 BIT(25)
60c0467a VB	57
	58	#define SD2CKCR 0xE615026C
	59	#define SD_97500KHZ 0x7
	60
	61	int board_early_init_f(void)
	62	{
	63	mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125);
	64
60c0467a VB	65	/*
	66	* SD0 clock is set to 97.5MHz by default.
	67	* Set SD2 to the 97.5MHz as well.
	68	*/
	69	writel(SD_97500KHZ, SD2CKCR);
	70
	71	return 0;
	72	}
	73
cd07358c MV	74	#define ETHERNET_PHY_RESET 176 /* GPIO 5 22 */
cd07358c MV	75
60c0467a VB	76	int board_init(void)
	77	{
	78	/* adress of boot parameters */
aa6e94de	79	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
60c0467a	80
cd07358c MV	81	/* Force ethernet PHY out of reset */
	82	gpio_request(ETHERNET_PHY_RESET, "phy_reset");
	83	gpio_direction_output(ETHERNET_PHY_RESET, 0);
	84	mdelay(10);
	85	gpio_direction_output(ETHERNET_PHY_RESET, 1);
	86
60c0467a VB	87	return 0;
	88	}
	89
789edf69	90	int dram_init(void)
60c0467a	91	{
12308b12	92	if (fdtdec_setup_mem_size_base() != 0)
789edf69	93	return -EINVAL;
60c0467a	94
60c0467a	95	return 0;
60c0467a VB	96	}
60c0467a VB	97
789edf69	98	int dram_init_banksize(void)
60c0467a	99	{
789edf69	100	fdtdec_setup_memory_banksize();
60c0467a VB	101
	102	return 0;
	103	}
	104
	105	/* porter has KSZ8041RNLI */
	106	#define PHY_CONTROL1 0x1E
4bbd4642	107	#define PHY_LED_MODE 0xC000
60c0467a VB	108	#define PHY_LED_MODE_ACK 0x4000
	109	int board_phy_config(struct phy_device *phydev)
	110	{
	111	int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
	112	ret &= ~PHY_LED_MODE;
	113	ret \|= PHY_LED_MODE_ACK;
	114	ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
	115
	116	return 0;
	117	}
	118
35b65dd8	119	void reset_cpu(void)
60c0467a	120	{
25f6dc89 MV	121	struct udevice *dev;
	122	const u8 pmic_bus = 6;
	123	const u8 pmic_addr = 0x5a;
	124	u8 data;
	125	int ret;
60c0467a	126
25f6dc89 MV	127	ret = i2c_get_chip_for_busnum(pmic_bus, pmic_addr, 1, &dev);
	128	if (ret)
	129	hang();
	130
	131	ret = dm_i2c_read(dev, 0x13, &data, 1);
	132	if (ret)
	133	hang();
	134
	135	data \|= BIT(1);
	136
	137	ret = dm_i2c_write(dev, 0x13, &data, 1);
	138	if (ret)
	139	hang();
60c0467a	140	}
f2b6f82b MV	141
	142	enum env_location env_get_location(enum env_operation op, int prio)
	143	{
	144	const u32 load_magic = 0xb33fc0de;
	145
	146	/* Block environment access if loaded using JTAG */
	147	if ((readl(CONFIG_SPL_TEXT_BASE + 0x24) == load_magic) &&
	148	(op != ENVOP_INIT))
	149	return ENVL_UNKNOWN;
	150
	151	if (prio)
	152	return ENVL_UNKNOWN;
	153
	154	return ENVL_SPI_FLASH;
	155	}