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c655fad0 NI |
1 | /* |
2 | * Copyright (C) 2008 Nobuhiro Iwamatsu | |
3 | * Copyright (C) 2008 Renesas Solutions Corp. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License as | |
7 | * published by the Free Software Foundation; either version 2 of | |
8 | * the License, or (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
18 | * MA 02111-1307 USA | |
19 | */ | |
20 | #include <config.h> | |
21 | #include <version.h> | |
22 | ||
23 | #include <asm/processor.h> | |
f7e78f3b | 24 | #include <asm/macro.h> |
c655fad0 NI |
25 | |
26 | .global lowlevel_init | |
27 | ||
28 | .text | |
29 | .align 2 | |
30 | ||
31 | lowlevel_init: | |
32 | /* Cache setting */ | |
f7e78f3b | 33 | write32 CCR1_A ,CCR1_D |
c655fad0 NI |
34 | |
35 | /* ConfigurePortPins */ | |
f7e78f3b | 36 | write16 PECRL3_A, PECRL3_D |
c655fad0 | 37 | |
f7e78f3b | 38 | write16 PCCRL4_A, PCCRL4_D0 |
c655fad0 | 39 | |
f7e78f3b | 40 | write16 PECRL4_A, PECRL4_D0 |
c655fad0 | 41 | |
f7e78f3b | 42 | write16 PEIORL_A, PEIORL_D0 |
c655fad0 | 43 | |
f7e78f3b | 44 | write16 PCIORL_A, PCIORL_D |
c655fad0 | 45 | |
f7e78f3b | 46 | write16 PFCRH2_A, PFCRH2_D |
c655fad0 | 47 | |
f7e78f3b | 48 | write16 PFCRH3_A, PFCRH3_D |
c655fad0 | 49 | |
f7e78f3b | 50 | write16 PFCRH1_A, PFCRH1_D |
c655fad0 | 51 | |
f7e78f3b | 52 | write16 PFIORH_A, PFIORH_D |
c655fad0 | 53 | |
f7e78f3b | 54 | write16 PECRL1_A, PECRL1_D0 |
c655fad0 | 55 | |
f7e78f3b | 56 | write16 PEIORL_A, PEIORL_D1 |
c655fad0 NI |
57 | |
58 | /* Configure Operating Frequency */ | |
f7e78f3b | 59 | write16 WTCSR_A, WTCSR_D0 |
c655fad0 | 60 | |
f7e78f3b | 61 | write16 WTCSR_A, WTCSR_D1 |
c655fad0 | 62 | |
f7e78f3b | 63 | write16 WTCNT_A, WTCNT_D |
c655fad0 NI |
64 | |
65 | /* Set clock mode*/ | |
f7e78f3b | 66 | write16 FRQCR_A, FRQCR_D |
c655fad0 NI |
67 | |
68 | /* Configure Bus And Memory */ | |
69 | init_bsc_cs0: | |
f7e78f3b | 70 | write16 PCCRL4_A, PCCRL4_D1 |
c655fad0 | 71 | |
f7e78f3b | 72 | write16 PECRL1_A, PECRL1_D1 |
c655fad0 | 73 | |
f7e78f3b | 74 | write32 CMNCR_A, CMNCR_D |
c655fad0 | 75 | |
ed56fb1d | 76 | write32 CS0BCR_A, CS0BCR_D |
c655fad0 | 77 | |
f7e78f3b | 78 | write32 CS0WCR_A, CS0WCR_D |
c655fad0 NI |
79 | |
80 | init_bsc_cs1: | |
f7e78f3b | 81 | write16 PECRL4_A, PECRL4_D1 |
c655fad0 | 82 | |
f7e78f3b | 83 | write32 CS1WCR_A, CS1WCR_D |
c655fad0 NI |
84 | |
85 | init_sdram: | |
f7e78f3b | 86 | write16 PCCRL2_A, PCCRL2_D |
c655fad0 | 87 | |
f7e78f3b | 88 | write16 PCCRL4_A, PCCRL4_D2 |
c655fad0 | 89 | |
f7e78f3b | 90 | write16 PCCRL1_A, PCCRL1_D |
c655fad0 | 91 | |
f7e78f3b | 92 | write16 PCCRL3_A, PCCRL3_D |
c655fad0 | 93 | |
f7e78f3b | 94 | write32 CS3BCR_A, CS3BCR_D |
c655fad0 | 95 | |
f7e78f3b | 96 | write32 CS3WCR_A, CS3WCR_D |
c655fad0 | 97 | |
f7e78f3b | 98 | write32 SDCR_A, SDCR_D |
c655fad0 | 99 | |
f7e78f3b | 100 | write32 RTCOR_A, RTCOR_D |
c655fad0 | 101 | |
f7e78f3b | 102 | write32 RTCSR_A, RTCSR_D |
c655fad0 NI |
103 | |
104 | /* wait 200us */ | |
e4430779 JCPV |
105 | mov.l REPEAT_D, r3 |
106 | mov #0, r2 | |
c655fad0 | 107 | repeat0: |
e4430779 JCPV |
108 | add #1, r2 |
109 | cmp/hs r3, r2 | |
110 | bf repeat0 | |
c655fad0 NI |
111 | nop |
112 | ||
e4430779 JCPV |
113 | mov.l SDRAM_MODE, r1 |
114 | mov #0, r0 | |
115 | mov.l r0, @r1 | |
c655fad0 NI |
116 | |
117 | nop | |
118 | rts | |
119 | ||
120 | .align 4 | |
121 | ||
122 | CCR1_A: .long CCR1 | |
123 | CCR1_D: .long 0x0000090B | |
124 | PCCRL4_A: .long 0xFFFE3910 | |
ed56fb1d NI |
125 | PCCRL4_D0: .word 0x0000 |
126 | .align 2 | |
c655fad0 | 127 | PECRL4_A: .long 0xFFFE3A10 |
ed56fb1d NI |
128 | PECRL4_D0: .word 0x0000 |
129 | .align 2 | |
c655fad0 | 130 | PECRL3_A: .long 0xFFFE3A12 |
ed56fb1d NI |
131 | PECRL3_D: .word 0x0000 |
132 | .align 2 | |
c655fad0 | 133 | PEIORL_A: .long 0xFFFE3A06 |
ed56fb1d NI |
134 | PEIORL_D0: .word 0x1C00 |
135 | PEIORL_D1: .word 0x1C02 | |
c655fad0 | 136 | PCIORL_A: .long 0xFFFE3906 |
ed56fb1d NI |
137 | PCIORL_D: .word 0x4000 |
138 | .align 2 | |
c655fad0 | 139 | PFCRH2_A: .long 0xFFFE3A8C |
ed56fb1d NI |
140 | PFCRH2_D: .word 0x0000 |
141 | .align 2 | |
c655fad0 | 142 | PFCRH3_A: .long 0xFFFE3A8A |
ed56fb1d NI |
143 | PFCRH3_D: .word 0x0000 |
144 | .align 2 | |
c655fad0 | 145 | PFCRH1_A: .long 0xFFFE3A8E |
ed56fb1d NI |
146 | PFCRH1_D: .word 0x0000 |
147 | .align 2 | |
c655fad0 | 148 | PFIORH_A: .long 0xFFFE3A84 |
ed56fb1d NI |
149 | PFIORH_D: .word 0x0729 |
150 | .align 2 | |
c655fad0 | 151 | PECRL1_A: .long 0xFFFE3A16 |
ed56fb1d NI |
152 | PECRL1_D0: .word 0x0033 |
153 | .align 2 | |
c655fad0 NI |
154 | |
155 | ||
156 | WTCSR_A: .long 0xFFFE0000 | |
ed56fb1d NI |
157 | WTCSR_D0: .word 0xA518 |
158 | WTCSR_D1: .word 0xA51D | |
c655fad0 | 159 | WTCNT_A: .long 0xFFFE0002 |
ed56fb1d NI |
160 | WTCNT_D: .word 0x5A84 |
161 | .align 2 | |
c655fad0 | 162 | FRQCR_A: .long 0xFFFE0010 |
ed56fb1d NI |
163 | FRQCR_D: .word 0x0104 |
164 | .align 2 | |
c655fad0 | 165 | |
ed56fb1d NI |
166 | PCCRL4_D1: .word 0x0010 |
167 | PECRL1_D1: .word 0x0133 | |
c655fad0 NI |
168 | |
169 | CMNCR_A: .long 0xFFFC0000 | |
170 | CMNCR_D: .long 0x00001810 | |
ed56fb1d NI |
171 | CS0BCR_A: .long 0xFFFC0004 |
172 | CS0BCR_D: .long 0x10000400 | |
c655fad0 NI |
173 | CS0WCR_A: .long 0xFFFC0028 |
174 | CS0WCR_D: .long 0x00000B41 | |
ed56fb1d NI |
175 | PECRL4_D1: .word 0x0100 |
176 | .align 2 | |
c655fad0 NI |
177 | CS1WCR_A: .long 0xFFFC002C |
178 | CS1WCR_D: .long 0x00000B01 | |
ed56fb1d NI |
179 | PCCRL4_D2: .word 0x0011 |
180 | .align 2 | |
c655fad0 | 181 | PCCRL3_A: .long 0xFFFE3912 |
ed56fb1d NI |
182 | PCCRL3_D: .word 0x0011 |
183 | .align 2 | |
c655fad0 | 184 | PCCRL2_A: .long 0xFFFE3914 |
ed56fb1d NI |
185 | PCCRL2_D: .word 0x1111 |
186 | .align 2 | |
c655fad0 | 187 | PCCRL1_A: .long 0xFFFE3916 |
ed56fb1d | 188 | PCCRL1_D: .word 0x1010 |
c4f07be2 | 189 | .align 2 |
c655fad0 | 190 | PDCRL4_A: .long 0xFFFE3990 |
ed56fb1d NI |
191 | PDCRL4_D: .word 0x0011 |
192 | .align 2 | |
c655fad0 | 193 | PDCRL3_A: .long 0xFFFE3992 |
ed56fb1d NI |
194 | PDCRL3_D: .word 0x00011 |
195 | .align 2 | |
c655fad0 | 196 | PDCRL2_A: .long 0xFFFE3994 |
ed56fb1d NI |
197 | PDCRL2_D: .word 0x1111 |
198 | .align 2 | |
c655fad0 | 199 | PDCRL1_A: .long 0xFFFE3996 |
ed56fb1d NI |
200 | PDCRL1_D: .word 0x1000 |
201 | .align 2 | |
c655fad0 NI |
202 | CS3BCR_A: .long 0xFFFC0010 |
203 | CS3BCR_D: .long 0x00004400 | |
204 | CS3WCR_A: .long 0xFFFC0034 | |
205 | CS3WCR_D: .long 0x00002892 | |
206 | SDCR_A: .long 0xFFFC004C | |
207 | SDCR_D: .long 0x00000809 | |
208 | RTCOR_A: .long 0xFFFC0058 | |
209 | RTCOR_D: .long 0xA55A0041 | |
210 | RTCSR_A: .long 0xFFFC0050 | |
211 | RTCSR_D: .long 0xa55a0010 | |
212 | ||
c655fad0 NI |
213 | SDRAM_MODE: .long 0xFFFC5040 |
214 | REPEAT_D: .long 0x00009C40 |